CN104182205B - SoC processor instruction verification method - Google Patents
SoC processor instruction verification method Download PDFInfo
- Publication number
- CN104182205B CN104182205B CN201410406272.1A CN201410406272A CN104182205B CN 104182205 B CN104182205 B CN 104182205B CN 201410406272 A CN201410406272 A CN 201410406272A CN 104182205 B CN104182205 B CN 104182205B
- Authority
- CN
- China
- Prior art keywords
- instruction
- data
- dom
- depositor
- verification method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a kind of SoC processor instruction verification method, comprise the following steps that 1) according to instruction format Format3, set up director data combination<rs1, rs2, rd>, wherein rs1, rs2, rd ∈ r depositor or f depositor；2) according to SPARC V8 depositor organizational structure, set up the data dependence of data rd and rs1, rs2, obtain interaction data composite set Rdom={ < rsi,rsj, rd > | rd=rsiOr rd=rsj, i, j=0 ..., 31}；3) by RdomData in set are inserted in the order code of Format3 form, obtain data interaction instruction set Idom；4) according to instruction flow line line series, from IdomIn arbitrarily choose pipeline stages several instruction composition intersect instruction verify.SoC processor instruction verification method of the present invention, it is possible to achieve the instruction to having data interaction function is verified, can be greatly improved the coverage rate of test checking, make SoC processor reliability index level improve.
Description
[technical field]
The present invention relates to a kind of SoC instruction set cross validation method based on SPARC V8 framework, specifically relate to
And one SoC processor instruction verification method.
[background technology]
SPARC V8 framework is widely used in design and the application of domestic SoC processor.SPARC V8 framework
The soft core of microprocessor IP of increasing income increased income is provided, comprises integer hardware multiplication and divider, double coprocessor
Interface (FPU floating point processing unit and Co-processor coprocessor), the instruction and data bus of separation；
There is provided AMBA-AHB bus at a high speed realize instruction buffer and data buffer storage respectively with Memory Controller Hub and height
The external interface mutual data transmission of speed；The AMBA-APB bus providing low speed realizes connecing of On-Chip peripheral
Mouthful.This soft core has the best configurability and portability, on the basis of VHDL source code,
Add, in conjunction with real needs, the arithmetic element customized and Peripheral Interface just can set up domestic SoC system.But
It is that domestic SoC wants to obtain the accreditation of domestic industry and further application still needs in terms of functional reliability
Do systematic test checking, especially will realize computing as SoC chip and to control micro-place of leitungskern
The checking of reason device instruction set function is placed on first of reliability demonstration work.
The most systematic verification method of existing command verification, is substantially according in SPARC V8 handbook
The IU listed and FPU instruction carry out the checking of individual instructions function, have ignored instruction and connect at a high speed with memorizer etc.
Mouth interaction data is vulnerable to design sequential and logic adverse effect the most rigorous, nonstandard, there is test checking
The shortcoming that spreadability is not enough.
[summary of the invention]
Present invention aims to the deficiencies in the prior art, it is provided that a kind of SoC processor instruction checking
Method.
For achieving the above object, the present invention adopts the following technical scheme that:
SoC processor instruction verification method, it is characterised in that comprise the following steps that
1) according to instruction format Format3, director data combination<rs1, rs2, rd>, wherein rs1, rs2, rd are set up
∈ r depositor or f depositor；
2) according to SPARC V8 depositor organizational structure, the data dependence of data rd and rs1, rs2 is set up,
Obtain interaction data composite set Rdom={ < rsi,rsj, rd > | rd=rsiOr rd=rsj, i, j=0 ..., 31}；
3) by RdomData in set are inserted in the order code of Format3 form, obtain data interaction instruction
Set Idom；
4) according to instruction flow line line series, from IdomIn arbitrarily choose pipeline stages several instruction composition interdigital
Order is verified.
The present invention further improvement is that, for floating-point single precision data manipulation instruction (fmuls rs1, rs2,
Rd), its command verification method comprises the following steps that
A) data combination<rs1, rs2, rd>, wherein rs1, rs2, rd ∈ f depositor are set up；
B) according to f depositor organizational structure, interaction data composite set R is obtaineddom；
C) by RdomCarry out order code filling, obtain floating-point single precision punishment instruction set；
D) from floating-point single precision punishment instruction set, arbitrarily choose 5 instructions and be combined obtaining interdigital
Order；
So far, the checking to floating-point single precision data manipulation instruction (fmuls rs1, rs2, rd) is completed.
The present invention further improvement is that, in step b), according to f depositor organizational structure, is counted alternately
According to composite set Rdom, part combination is as follows:
<f0,f0,f0>,<f0,f1,f0>,<f0,f2,f0>,……
<f1,f0,f0>,<f2,f0,f0>,<f3,f0,f0>,……
……
<f1,f31,f31>,<f2,f31,f31>,<f3,f31,f31>,……。
The present invention further improvement is that, in step c), by RdomCarry out order code filling, obtain floating-point list
The part instruction of precision punishment instruction set is as follows:
The present invention further improvement is that, in step d), from floating-point single precision punishment instruction set, arbitrarily
Choosing 5 instructions, to be combined obtaining intersecting instruction as follows:
Compared with prior art, the present invention has a following beneficial effect:
SoC processor instruction verification method of the present invention, it is possible to achieve the instruction to having data interaction function is entered
Row checking, can be greatly improved the coverage rate of test checking, make SoC processor reliability index level improve.
[accompanying drawing explanation]
Fig. 1 is SPARC instruction format figure.
[detailed description of the invention]
The present invention is described in more detail below in conjunction with the accompanying drawings.
Each function that processor correctly performs is the sequential combination of fundamental type instruction.In order to investigate instruction
Between interactivity, processor instruction set checking should from instruction stream perform sequential combination angle to classes of instructions
Divide, thus it is consistent with processor logic checking correctness to realize command function checking effectiveness.
Instruction set can be divided into read-write operation instruction, data manipulation instruction and three instruction class of control operational order
Not.Read-write operation instruction is first link of processor functional realiey, completes to realize the data needed for function
Preparation.Contrasting with Fig. 1, the form of such instruction belongs to Format 3.Data manipulation instruction is processor
Second link of functional realiey, completes the data evaluation work realized needed for function.Contrast with Fig. 1, should
The form of class instruction belongs to Format 3.Control the 3rd link that operational order is processor functional realiey, root
The control work of cpu logic is realized according to the data result of calculation of second link.Contrasting with Fig. 1, such refers to
The form of order belongs to Format 1 and Format 2.
Three classes of instructions exist and carries out the instruction of data interaction with the high-speed interface such as memorizer and mainly have read-write
Operational order and data manipulation instruction.Meanwhile, read-write operation and data oriented instruction broadly fall into instruction format
Format 3, data interaction is mainly realized by depositor rd, rs1 and rs2.
See Fig. 1, SoC processor instruction verification method of the present invention, comprise the following steps that
1) according to instruction format Format3, director data combination<rs1, rs2, rd>, wherein rs1, rs2, rd are set up
∈ r depositor or f depositor；
2) according to SPARC V8 depositor organizational structure, the data dependence of data rd and rs1, rs2 is set up,
Obtain interaction data composite set Rdom={ < rsi,rsj, rd > | rd=rsiOr rd=rsj, i, j=0 ..., 31}；
3) by RdomData in set are inserted in the order code of Format3 form, obtain data interaction instruction
Set Idom；
4) according to instruction flow line line series, from IdomIn arbitrarily choose pipeline stages several instruction composition interdigital
Order is verified.
In conjunction with a floating-point single precision data manipulation instruction (fmuls rs1, rs2, rd) present invention made into
One step describes:
A) data combination<rs1, rs2, rd>, wherein rs1, rs2, rd ∈ f depositor are set up；
B) according to f depositor organizational structure, interaction data composite set R is obtaineddom, part combination is as follows:
<f0,f0,f0>,<f0,f1,f0>,<f0,f2,f0>,……
<f1,f0,f0>,<f2,f0,f0>,<f3,f0,f0>,……
……
<f1,f31,f31>,<f2,f31,f31>,<f3,f31,f31>,……
C) by RdomCarrying out order code filling, the part instruction obtaining floating-point single precision punishment instruction set is as follows:
D) from floating-point single precision punishment instruction set, arbitrarily choose 5 instructions and be combined obtaining interdigital
Make as follows:
So far, the checking to floating-point single precision data manipulation instruction (fmuls rs1, rs2, rd) is completed.
From intersecting instruction it can be seen that the data that this verification method both can verify instruction internal are correlated with, also
Can verify that the data between instruction are correlated with, reach the checking purpose of data interaction.
Claims (5)
1.SoC processor instruction verification method, it is characterised in that comprise the following steps that
1) according to instruction format Format3, director data combination<rs1, rs2, rd>, wherein rs1, rs2, rd are set up
∈ r depositor or f depositor；
2) according to SPARC V8 depositor organizational structure, the data dependence of data rd and rs1, rs2 is set up,
Obtain interaction data composite set Rdom={ < rsi,rsj, rd > | rd=rsiOr rd=rsj, i, j=0 ..., 31}；
3) by RdomData in set are inserted in the order code of Format3 form, obtain data interaction instruction
Set Idom；
4) according to instruction flow line line series, from IdomIn arbitrarily choose pipeline stages several instruction composition interdigital
Order is verified.
SoC processor instruction verification method the most according to claim 1, it is characterised in that for floating
Point single precision data manipulation instruction, its command verification method comprises the following steps that
A) data combination<rs1, rs2, rd>, wherein rs1, rs2, rd ∈ f depositor are set up；
B) according to f depositor organizational structure, interaction data composite set R is obtaineddom；
C) by RdomCarry out order code filling, obtain floating-point single precision punishment instruction set；
D) from floating-point single precision punishment instruction set, arbitrarily choose 5 instructions and be combined obtaining interdigital
Order；
So far, the checking to floating-point single precision data manipulation instruction is completed.
SoC processor instruction verification method the most according to claim 2, it is characterised in that step b)
In, according to f depositor organizational structure, obtain interaction data composite set Rdom, part combination is as follows:
<f0,f0,f0>,<f0,f1,f0>,<f0,f2,f0>,……
<f1,f0,f0>,<f2,f0,f0>,<f3,f0,f0>,……
……
<f1,f31,f31>,<f2,f31,f31>,<f3,f31,f31>,……。
SoC processor instruction verification method the most according to claim 2, it is characterised in that step c)
In, by RdomCarrying out order code filling, the part instruction obtaining floating-point single precision punishment instruction set is as follows:
SoC processor instruction verification method the most according to claim 2, it is characterised in that step d)
In, from floating-point single precision punishment instruction set, arbitrarily choose 5 instructions and be combined obtaining intersecting instructing
As follows:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410406272.1A CN104182205B (en) | 2014-08-18 | 2014-08-18 | SoC processor instruction verification method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410406272.1A CN104182205B (en) | 2014-08-18 | 2014-08-18 | SoC processor instruction verification method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104182205A CN104182205A (en) | 2014-12-03 |
| CN104182205B true CN104182205B (en) | 2016-08-31 |
Family
ID=51963287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410406272.1A Active CN104182205B (en) | 2014-08-18 | 2014-08-18 | SoC processor instruction verification method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104182205B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102902906A (en) * | 2012-09-26 | 2013-01-30 | 中国航天科技集团公司第九研究院第七七一研究所 | Microprocessor instruction set validation method |
| CN103902252A (en) * | 2014-03-28 | 2014-07-02 | 中国航天科技集团公司第九研究院第七七一研究所 | Analysis method for assembly line instruction correlation |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7156305B2 (en) * | 2004-12-23 | 2007-01-02 | T3C Inc. | Apparatus and method for authenticating products |
-
2014
- 2014-08-18 CN CN201410406272.1A patent/CN104182205B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102902906A (en) * | 2012-09-26 | 2013-01-30 | 中国航天科技集团公司第九研究院第七七一研究所 | Microprocessor instruction set validation method |
| CN103902252A (en) * | 2014-03-28 | 2014-07-02 | 中国航天科技集团公司第九研究院第七七一研究所 | Analysis method for assembly line instruction correlation |
Non-Patent Citations (2)
| Title |
|---|
| 基于 SPARC V8 的事务级 SoC 验证平台设计;杨奕 等;《微电子学与计算机》;20140331;第31卷(第3期);159-163 * |
| 基于SPARC V8 的事务级SOC验证平台设计;杨奕;《中国优秀硕士学位论文全文数据库信息科技辑》;20140331(第3期);正文13-34页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104182205A (en) | 2014-12-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Martin Jr et al. | HELLP syndrome and composite major maternal morbidity: importance of Mississippi classification system | |
| Lyles et al. | A risk scoring system to predict in-hospital mortality in patients with cirrhosis presenting with upper gastrointestinal bleeding | |
| DE102018000886A1 (en) | Virtual machine communication on a hardware basis | |
| Gupta et al. | Temporal trends of respiratory syncytial virus–associated hospital and ICU admissions across the United States | |
| CN109542713B (en) | Verification method and verification device | |
| CN103049710B (en) | Field-programmable gate array (FPGA) chip for SM2 digital signature verification algorithm | |
| US9235564B2 (en) | Offloading projection of fixed and variable length database columns | |
| CN107111572A (en) | Method and circuit for avoiding deadlock | |
| CN102663270A (en) | Method for processing alignment results of sequence alignment algorithm based on GPU | |
| CN104182205B (en) | SoC processor instruction verification method | |
| Natanegara et al. | Statistical opportunities to accelerate development for COVID-19 therapeutics | |
| Gortazar et al. | Trends in prevalence of diabetes among twin pregnancies and perinatal outcomes in Catalonia between 2006 and 2015: the DIAGESTCAT Study | |
| US20230252263A1 (en) | Point to point connected processing elements with data joiner components | |
| CN104753741A (en) | Network card test performance adjustment method and device | |
| Marcinek et al. | Variable delayed dual-core lockstep (vdcls) processor for safety and security applications | |
| CN105608205B (en) | The finger-mark check method and device of structural data | |
| CN103902252B (en) | A kind of analysis method for instruction pipeline dependency | |
| CN105320630A (en) | Heterogeneous multi-core CPU-GPU (Central Processing Unit-Graphics Processing Unit) system architecture based on intelligent flash cache | |
| US20150323602A1 (en) | Monitoring method, monitoring apparatus, and electronic device | |
| Afrati et al. | Matching bounds for the all-pairs MapReduce problem | |
| Hussain et al. | Savior: A reliable fault resilient router architecture for network-on-chip | |
| CN104899371B (en) | Survey of Transmission Line method and device | |
| US20170228486A1 (en) | Selective boundary overlay insertion for hierarchical circuit design | |
| CN107423249A (en) | It is a kind of based on AHB lite bus protocols from end bus control unit design method | |
| CN106844003A (en) | The method of calibration and device of a kind of virtual machine image |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |