CN103902252A - Analysis method for assembly line instruction correlation - Google Patents
Analysis method for assembly line instruction correlation Download PDFInfo
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- CN103902252A CN103902252A CN201410131434.5A CN201410131434A CN103902252A CN 103902252 A CN103902252 A CN 103902252A CN 201410131434 A CN201410131434 A CN 201410131434A CN 103902252 A CN103902252 A CN 103902252A
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Abstract
The invention discloses an analysis method for assembly line instruction correlation, and provides a verification method for analyzing minimum instruction sequences from the perspective of user application. Through LEON instruction correlation analysis, correlation verification requirements can be met under the condition that at least three-level instruction correlation is verified. In consideration of protection to function program codes written by users, input files used in the method are 32bit machine codes generated after compiling of the users, and instruction sequences used by the users can be acquired through analysis; correlation of the instruction sequences is analyzed to acquire used and repeatedly used instruction sequence analysis results, instruction correlation verification is guided, and instruction verification is ensured to effectively meet application requirements of the users.
Description
Technical field
The present invention relates to processor instruction verification technique field, relate to a kind of analytical approach for instruction pipeline correlativity.
Background technology
LEON processor is the soft core of a microprocessor of increasing income, and comprises integer hardware multiplication and divider, two coprocessors (FPU floating point processing unit and coprocessor), the instruction and data bus of separation.This framework has comprised input and output I/O mouth, Memory Management Unit, the sub-construction system of cache (MMU) and super authority software, memory model etc.; This soft core has very good configurability and portability, on VHDl source code basis, adds the arithmetic element of customization and Peripheral Interface just can set up domestic SOC system in conjunction with real needs.This processor comprises 172 usual instructions, 40～520 registers, the very complicated correctness that therefore needs large-scale instruction checking guarantee LEON functional processor of instruction set.
The 5 stage pipeline structure designs of LEON processor adopting, instruction execution is divided into value (FE), decoding (DE), carries out (EX), memory access (ME), writes back (WR) five function phases, may there is pipelining conflict while execution in instruction, therefore in checking work, need the correlativity of instruction pipeline to verify.The correlation circumstance of SPARC V8 instruction dependency and register is very complicated, supposes that an instruction can be used 10 kinds of register combinations, and relevant situation may occur in five-stage pipeline (172*10)
5, adding the different-format of every instruction, the instruction sequence situation that may occur is more, relies on current verification condition cannot complete by the verification method that travels through all instruction sequences, therefore can not ensure the comprehensive and validity of checking.
Summary of the invention
The problem that the present invention solves is to provide a kind of analytical approach for instruction pipeline correlativity, the program that may use by large scale analysis user, obtain instruction sequences used and that use is maximum, and the correlativity to these instruction sequences is analyzed, and then teaching instruction checking work.
The present invention is achieved through the following technical solutions:
1, for an analytical approach for instruction pipeline correlativity, it is characterized in that, comprise following operation:
1) to pending analytic target, being translated into by compiler is the machine code file of 32, as analyzing the input file using;
2) obtain order format and register coding according to the instruction encoding form of compiler; According to the formation in order format coding, determine instruction encoding and register coding that it adopts; And the instruction encoding called after particular value identical to type, then particular value is arranged according to instruction sequences;
3) selected specified n level correlation analysis, from Article 1 instruction, is associated n-1 instruction thereafter, the particular value sequence after statistical correlation; Then analyze the associated situation of the corresponding instruction of this particular value sequence and register;
4) number of times that the instruction sequence that the instruction of statistics generation secondary is relevant and this sequence occur, and relevant quantity and the register correlation type occurring of instruction;
Instruction particular value sequence, register particular value sequence are normalized, obtain the probability that same instructions particular value sequence in all instructions, identical register particular value sequence occur, obtain secondary instruction correlated results;
5) number of times that the instruction sequence that three grades of instructions of statistics generation are relevant and this sequence occur, and relevant quantity and the register correlation type occurring of instruction;
Instruction particular value sequence, register particular value sequence are normalized, obtain the probability that same instructions particular value sequence in all instructions, identical register particular value sequence occur, obtain three grades of instruction correlated results;
6) secondary instruction correlated results, three grades of instruction correlated results are gathered to viewing pipeline correlation analysis result.
2, the analytical approach for instruction pipeline correlativity as claimed in claim 1, it is characterized in that, described being translated into by SPARC V8 compiler is the machine code file of 32, then obtains order format and register coded format according to SPARC V8 instruction encoding form.
3, the analytical approach for instruction pipeline correlativity as claimed in claim 1, it is characterized in that, the associated situation of the described analysis corresponding instruction of this particular value sequence and register, by the correlativity of the corresponding register of Article 1 instruction and follow-up n-1, the corresponding register of n-2 bar instruction, obtain register dependencies sequence, and by its called after register particular value.
4, the analytical approach for instruction pipeline correlativity as claimed in claim 1, is characterized in that, described secondary instruction dependency is the analysis of the correlativity of two instructions of contact, and relative particular value sequence is carried out association;
Three grades of described instruction dependencies are the analysis of the correlativity of three instructions of contact, and relative particular value sequence is carried out association.
Compared with prior art, the present invention has following useful technique effect:
The present invention is directed to instruction pipeline correlativity checking workload large, verify what the problem such as incomplete proposed.Propose a kind of angle analysis using from user, drawn the verification method that meets user demand, for analyzing minimizing instruction sequence, by LEON instruction dependency is analyzed, needed at least three grades of instructions of checking to be correlated with and could meet correlativity checking demand.Consider the function program code that protection user writes; the Study document that the method is used is 32 machine codes of rear generation for user compiles; obtain by analysis the associated instruction sequences that user uses; and the correlativity of analysis instruction sequence; obtain use with nonexpondable instruction sequence analysis result; the checking of teaching instruction correlativity, ensures that instruction checking work effectively meets user's user demand.
Analyze by the function program file that user is used, obtain instruction dependency analysis result, can solve the comprehensive and validity problem that cannot ensure instruction dependency checking in instruction checking work, the instruction sequence likely using is covered in guarantee checking work, reduce instruction checking workload, improve checking work efficiency.
Can obtain the number of times of all instruction sequence combinations and packing of orders appearance by the present invention, the correlativity of the packing of orders.Can greatly reduce the workload of checking.Thereby verify targetedly.By the repertoire program using in certain model leon processor system checking is analyzed to (totally 18408 row), analysis result shows that the sequence that two instructions occur continuously has 108 kinds of situations, article three, the sequence that instruction occurs continuously has 253 kinds of situations, the quantity of calculating much smaller than theory.
Brief description of the drawings
Fig. 1 is schematic flow sheet of the present invention;
Fig. 2 is the schematic diagram of mandatory correlation analysis.
Embodiment
Below in conjunction with specific embodiment, the present invention is described in further detail, and the explanation of the invention is not limited.
The present invention proposes a kind of analytical approach for instruction pipeline correlativity, the method is a kind of verification method of the angle analysis minimizing instruction sequence using from user, by LEON instruction dependency is analyzed, need at least three grades of instructions of checking to be correlated with and could meet correlativity checking demand.Consider the function program code that protection user writes; the input file that the method is used is 32 machine codes of rear generation for user compiles; obtain by analysis the instruction sequence that user uses; and the correlativity of analysis instruction sequence; obtain used and nonexpondable instruction sequence analysis result; the checking of teaching instruction correlativity, ensures that instruction checking work effectively meets user's user demand.
For an analytical approach for instruction pipeline correlativity, comprise following operation:
1) to pending analytic target, being translated into by compiler is the machine code file of 32, as analyzing the input file using;
2) obtain order format and register coding according to the instruction encoding form of compiler; According to the formation in order format coding, determine instruction encoding and register coding that it adopts; And the instruction encoding called after particular value identical to type, then particular value is arranged according to instruction sequences;
3) selected specified n level correlation analysis, from Article 1 instruction, is associated n-1 instruction thereafter, the particular value sequence after statistical correlation; Then analyze the associated situation of the corresponding instruction of this particular value sequence and register;
4) number of times that the instruction sequence that the instruction of statistics generation secondary is relevant and this sequence occur, and relevant quantity and the register correlation type occurring of instruction;
Instruction particular value sequence, register particular value sequence are normalized, obtain the probability that same instructions particular value sequence in all instructions, identical register particular value sequence occur, obtain secondary instruction correlated results;
5) number of times that the instruction sequence that three grades of instructions of statistics generation are relevant and this sequence occur, and relevant quantity and the register correlation type occurring of instruction;
Instruction particular value sequence, register particular value sequence are normalized, obtain the probability that same instructions particular value sequence in all instructions, identical register particular value sequence occur, obtain three grades of instruction correlated results;
6) secondary instruction correlated results, three grades of instruction correlated results are gathered, obtain instruction dependency result, viewing pipeline correlation analysis result.
Provide specific embodiment below in conjunction with concrete analytic process.
Step 1: correlation analysis needs user that the machine code file of 32 is provided, user uses C language or assembly language to write function program, become the machine code file of 32 by SPARC V8 compiler or the compiling of user's specific compiler, as analyzing the input file using.
Step 2: obtain according to SPARC V8 instruction encoding form: SPARC V8 order format is as shown in table 1; Register coding is as shown in table 2.
Table 1: part order format coding
Table 2: register coding
| register | code |
| %g0～%g7 | 0x0～0x7 |
| %o0～%o7 | 0x8～0xF |
| %l0～%l7 | 0x10～0x17 |
| %i0～%i7 | 0x18～0x1F |
| %f0～%f31 | 0x0～0x31 |
Step 3: carry out routine analyzer according to table 1, table 2.
32 are divided into five parts, determine according to the corresponding numeral of its Q-character instruction encoding and the register coding that it adopts;
And the instruction encoding called after particular value identical to type, then particular value is arranged according to instruction sequences;
Selected specified n level correlation analysis, from Article 1 instruction, is associated n-1 instruction thereafter, the particular value sequence after statistical correlation;
(the corresponding register of Article 1 instruction is in the correlativity of follow-up n-1, the corresponding register of n-2 bar instruction to analyze the associated situation of the corresponding instruction of this particular value sequence and register thereof, obtain register dependencies sequence, and by its called after register particular value);
Concrete: 32 are divided into five parts, determine according to the corresponding numeral of its Q-character instruction encoding and the register coding that it adopts;
Input file obtains every instruction that machine code is corresponding by routine analyzer, calculates the number of times that every kind of instruction sequence occurs.
Input file obtains by routine analyzer rs1, rs2, the rd type that every machine code is used, and calculates the quantity that effective register correlation circumstance occurs.
By all instructions, n level is relevant one by one, the number of times that statistics instruction particular value sequence occurs, and the number of times occurring for same instruction particular value sequential analyzer register particular value sequence,
Step 4: the number of times that instruction sequence that 2 grades (instruction of two of front and back) is relevant and this sequence occur occurs statistics, and relevant quantity and the register correlation type occurring of instruction.
Instruction particular value sequence, register particular value sequence are normalized, obtain the probability that same instructions particular value sequence in all instructions, identical register particular value sequence occur, output report;
Step 5: the number of times of listing 3 grades of relevant instruction sequences that occur and the appearance of this instruction sequence by step above.And the relevant quantity type relevant with register occurring of instruction.
Step 6: the correlativity type viewing pipeline correlation analysis being obtained by step 3 and step 4 is reported.
Concrete referring to Fig. 2, provide following concrete instruction particular value sequence:
2 grades of relevant its particular value sequences are: 12,23,34,45,56;
3 grades of relevant its particular value sequences are: 123,234,345,456;
And the register series that particular value sequence in relevant for 2 grades is 23 is:
Add：%01、%02、%02；
Subcc：%02、%03、%04；
Secondary register series particular value 201
Three grades of register series particular values 301 of called after
The register series particular value that particular value sequence is 23 is 201.
In end product, correlativity is presented as: in add, the association of subcc two-stage, particular register arrangement mode 201 is a%.
According to the present invention, the viewing pipeline correlation analysis result of output is only carried out the checking of specific instruction, particular register sequence, avoids repeatability there is no the work of purpose.
Claims (4)
1. for an analytical approach for instruction pipeline correlativity, it is characterized in that, comprise following operation:
1) to pending analytic target, being translated into by compiler is the machine code file of 32, as analyzing the input file using;
2) obtain order format and register coding according to the instruction encoding form of compiler; According to the formation in order format coding, determine instruction encoding and register coding that it adopts; And the instruction encoding called after particular value identical to type, then particular value is arranged according to instruction sequences;
3) selected specified n level correlation analysis, from Article 1 instruction, is associated n-1 instruction thereafter, the particular value sequence after statistical correlation; Then analyze the associated situation of the corresponding instruction of this particular value sequence and register;
4) number of times that the instruction sequence that the instruction of statistics generation secondary is relevant and this sequence occur, and relevant quantity and the register correlation type occurring of instruction;
Instruction particular value sequence, register particular value sequence are normalized, obtain the probability that same instructions particular value sequence in all instructions, identical register particular value sequence occur, obtain secondary instruction correlated results;
5) number of times that the instruction sequence that three grades of instructions of statistics generation are relevant and this sequence occur, and relevant quantity and the register correlation type occurring of instruction;
Instruction particular value sequence, register particular value sequence are normalized, obtain the probability that same instructions particular value sequence in all instructions, identical register particular value sequence occur, obtain three grades of instruction correlated results;
6) secondary instruction correlated results, three grades of instruction correlated results are gathered to viewing pipeline correlation analysis result.
2. the analytical approach for instruction pipeline correlativity as claimed in claim 1, it is characterized in that, described being translated into by SPARC V8 compiler is the machine code file of 32, then obtains order format and register coded format according to SPARC V8 instruction encoding form.
3. the analytical approach for instruction pipeline correlativity as claimed in claim 1, it is characterized in that, the associated situation of the described analysis corresponding instruction of this particular value sequence and register, by the correlativity of the corresponding register of Article 1 instruction and follow-up n-1, the corresponding register of n-2 bar instruction, obtain register dependencies sequence, and by its called after register particular value.
4. the analytical approach for instruction pipeline correlativity as claimed in claim 1, is characterized in that, described secondary instruction dependency is the analysis of the correlativity of two instructions of contact, and relative particular value sequence is carried out association;
Three grades of described instruction dependencies are the analysis of the correlativity of three instructions of contact, and relative particular value sequence is carried out association.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104182205A (en) * | 2014-08-18 | 2014-12-03 | 中国航天科技集团公司第九研究院第七七一研究所 | SOC (system on chip) processor instruction verification method |
| CN109725904A (en) * | 2017-10-31 | 2019-05-07 | 中国科学院微电子研究所 | A kind of low-power consumption program instruction Compilation Method and system |
| CN112445528A (en) * | 2019-08-29 | 2021-03-05 | 无锡江南计算技术研究所 | Result self-checking instruction sequence filling method based on pipeline constraint |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104182205A (en) * | 2014-08-18 | 2014-12-03 | 中国航天科技集团公司第九研究院第七七一研究所 | SOC (system on chip) processor instruction verification method |
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| CN109725904A (en) * | 2017-10-31 | 2019-05-07 | 中国科学院微电子研究所 | A kind of low-power consumption program instruction Compilation Method and system |
| CN109725904B (en) * | 2017-10-31 | 2021-10-22 | 中国科学院微电子研究所 | Low-power-consumption program instruction compiling method and system |
| CN112445528A (en) * | 2019-08-29 | 2021-03-05 | 无锡江南计算技术研究所 | Result self-checking instruction sequence filling method based on pipeline constraint |
| CN112445528B (en) * | 2019-08-29 | 2022-09-13 | 无锡江南计算技术研究所 | Result self-checking instruction sequence filling method based on pipeline constraint |
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