CN104170267A

CN104170267A - CMOS based TX/RX switch

Info

Publication number: CN104170267A
Application number: CN201380004662.XA
Authority: CN
Inventors: A·莫斯托夫; Y·哈森; R·蓬格拉茨
Original assignee: DSP Group Ltd
Current assignee: DSP Group Ltd
Priority date: 2012-09-25
Filing date: 2013-09-25
Publication date: 2014-11-26
Anticipated expiration: 2033-09-25
Also published as: CN104170267B9; CN104160553B; WO2014052417A1; CN104170267B; WO2014052413A1; CN104160553A

Abstract

A novel and useful radio frequency (RF) front end module (FEM) circuit provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard CMOS processes. The FEM circuit includes a power amplifier made up of one or more sub-amplifiers having high and low power circuits and whose outputs are combined to yield the total desired power gain. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provide efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers.

Description

TX/RX switch based on CMOS

Quoting of priority application

The application requires following priority: the sequence number No.61/704 that on September 23rd, 2012 submits to, 510, the U. S. application that is entitled as " An Integrated Transformer (integrated transformer) ", the sequence number No.61/705 that on September 25th, 2012 submits to, 150, the U. S. application that is entitled as " A Method and System for Noise Reduction in Wireless Communication (for the method and system of radio communication noise reduction) ", the sequence number No.61/720 that on October 30th, 2012 submits to, 001, the U. S. application that is entitled as " System and Method for Radio Frequency Signal Amplification (system and method that radiofrequency signal is amplified) ", the sequence number No.61/726 that on November 15th, 2012 submits to, 699, the U. S. application that is entitled as " DC DC Converter with Fast Output Voltage Transitions (the DC-DC transformer with quick output voltage conversion) ", the sequence number No.61/726 that on November 15th, 2012 submits to, 717, the U. S. application that is entitled as " High-Efficiency Envelop Tracking Method and System Utilizing DC-DC Converter With Fast Output Voltage Transitions (utilization has efficient envelope tracking and the system of the DC-DC transformer of quick output voltage conversion) ", the sequence number that on November 16th, 2012 submits to is No.61/727, 120, be entitled as " A Method and Device for Self Aligned PA and LNA VSWR Out/In Improvement, Dynamically Adjust to Antenna (improves for autoregistration PA and LNA VSWR input/output, the dynamic method and apparatus of adjusting antenna) " U. S. application, the sequence number No.61/727 that on November 16th, 2012 submits to, 121, the U. S. application that is entitled as " A Method and Device for Self Aligned Linearity Driven LNA Improvement (the improved method and apparatus of autoregistration Linear Driving LNA) ", its all the elements are hereby incorporated by.

Technical field

The present invention relates to radio frequency (RF) circuit, more specifically, relate to RF front-end module (FEM) circuit with high linearity and high efficiency power amplifier.

Background technology

At present, wireless communication system finds application the many scenes that relate to the communication from any to another point, and has the extensive form of the specific needs be suitable for meeting each scene.These systems comprise cell phone and the two-way radio for remote speech communication, and for short distance data network of computer system etc.In general, radio communication relates to radio frequency (RF) carrier signal and the modulation that meets the signal of one group of standard of modulating to represent data, sends, receives and demodulates.For radio data network, example standards comprises WLAN (IEEE802.11), bluetooth (IEEE802.15.1) and ZigBee (IEEE802.15.4), they are time domain duplex system normally, wherein emulation two-way link on time-division communication channel.

An element of wireless communication system is the transceiver that comprises reflector and acceptor circuit.The transceiver with digital baseband subsystem is modulated to baseband signal and by baseband signal digital data coding together with RF carrier signal.Modulation for WLAN comprises OFDM (OFDM), Quadrature Phase Shift Keying (QPSK) and quadrature amplitude modulation (16QAM, 64QAM); Modulation for WLAN comprises GFSK and 4/8-DQPSK; And comprise BPSK and OQPSK (or MSK) for the modulation of Zigbee.

From antenna is received signal, this transceiver is RF signal down-conversion, demodulated base band signal and being decoded by the represented numerical data of baseband signal.The antenna that is connected to transceiver converts the electrical signal to electromagnetic wave and vice versa.According to concrete configuration, described transceiver can comprise the special-purpose sending/receiving line that (TX) line and special-purpose reception (RX) line or transceiver can have combination that sends.In the situation that independent TX and RX line send line and are conventionally attached to individual antenna with reception line, especially for low-cost and/or undersized application.

Circuit between transceiver and antenna is commonly referred to front-end module (FEM).This FEM comprises RF power amplifier (PA), and it generates output transmitted signal by the weak input signal amplifying in the wireless device such as cellular handset.Many these communication equipments are configured to work at the different frequency bands for different communication systems.For example, the third generation (3G) cellular communication system, 4G honeycomb (LTE) system, 802.11WLAN system etc.

Therefore, wish a kind of front-end module, the performance requirement that it can meet modern wireless standards (as 802.11,3G and 4G cellular system), reduces simultaneously and manufactures complexity, size and cost.

Summary of the invention

The present invention is a kind of novelty and useful radio frequency (RF) front-end module (FEM) circuit, it provides high linearity and power efficiency, and meets the requirement of Modern wireless communication standard (such as 802.11WLAN, 3G and 4G cellular standards, bluetooth, ZigBee etc.).The configuration of FEM circuit allows to use semiconductor fabrication common, relatively low cost, as standard CMOS process.Described FEM circuit comprises bimodulus power amplifier, and it comprises one or more sub-amplifier, and the output of this little amplifier is combined to produce total required power gain.Many tapped transformers with the primary and secondary winding of arranging with novel configuration provide efficient power synthesize and send the power that independent sub-amplifier was generated to antenna.

Therefore, according to the present invention, provide a kind of semiconductor duplexer, it comprises: first day line cap, and it is for being coupled to the first antenna; Second day line cap, it is for being coupled to the second antenna; Sending/receiving port, it is for being coupled to described the first antenna or described the second antenna; Matching network, it is coupled to described sending/receiving port; The first switch, it is series coupled between described first day line cap and described matching network; And second switch, it is series coupled between described second day line cap and described matching network.

According to the present invention, a kind of semiconductor duplexer is also provided, it comprises: first day line cap, it is for being coupled to the first antenna; Second day line cap, it is for being coupled to the second antenna; Sending/receiving port, it is for sending RF signal coupling to described the first antenna or described the second antenna or be coupled from the reception RF signal of described the first antenna or described the second antenna; The first field-effect transistor (FET) switch, it has source electrode, drain and gate terminal, described drain terminal is coupled to described first day line cap, described source-coupled is to described sending/receiving port, and described gate terminal can operate to receive for controlling the first enable signal of a described FET switch; And second field-effect transistor (FET) switch, it has source electrode, drain and gate terminal, described drain terminal is coupled to described second day line cap, described source-coupled is to described sending/receiving port, and described gate terminal can operate to receive for controlling the second enable signal of described the 2nd FET switch.

Accompanying drawing explanation

Here with reference to accompanying drawing, only by way of example the present invention is described, in the accompanying drawings:

Fig. 1 shows according to the present invention and the block diagram of the example two-band multi-chip front-end module (FEM) that builds;

Fig. 2 shows according to the present invention and the block diagram of the example single-chip FEM circuit that builds;

Fig. 3 shows according to the present invention and the block diagram of the example DC-DC transducer that builds;

Fig. 4 shows according to the present invention and the block diagram of the example RX path part of the FEM circuit that builds;

Fig. 5 shows the block diagram of the first example TX path part of FEM circuit;

Fig. 6 shows the block diagram of the second example TX path part of FEM circuit;

Fig. 7 shows the block diagram of the 3rd example TX path part of FEM circuit;

Fig. 8 shows the block diagram of the 4th example TX path part of FEM circuit;

Fig. 9 shows the block diagram of the 5th example TX path part of FEM circuit;

Figure 10 shows the block diagram of the 6th example TX path part of FEM circuit;

Figure 11 is the block diagram that shows in more detail the low and high part of power amplifier circuit;

Figure 12 A shows the schematic diagram of the first example difference PA circuit;

Figure 12 B is the schematic diagram that shows in more detail the first example difference PA circuit with transformer connection;

Figure 13 A shows the schematic diagram of the second example difference PA circuit;

Figure 13 B is the schematic diagram that shows in more detail the second example difference PA circuit with transformer connection;

Figure 14 shows the schematic diagram of the 3rd example difference PA circuit;

Figure 15 shows the layout for the first example integrated transformer of power amplifier of the present invention;

Figure 16 shows the layout for the second example integrated transformer of power amplifier of the present invention;

Figure 17 shows the layout for the 3rd example integrated transformer of power amplifier of the present invention;

Figure 18 shows the layout for the 4th example integrated transformer of power amplifier of the present invention;

Figure 19 A shows the layout for the 5th example integrated transformer of power amplifier of the present invention;

Figure 19 B shows the layout for the 6th example integrated transformer of power amplifier of the present invention;

Figure 19 C shows the layout for the 7th example integrated transformer of power amplifier of the present invention;

Figure 20 shows the layout for the 8th example integrated transformer of power amplifier of the present invention;

Figure 21 shows the layout for the 9th example integrated transformer of power amplifier of the present invention;

Figure 22 shows the layout for the tenth example integrated transformer of power amplifier of the present invention;

Figure 23 shows the layout for the 11 example integrated transformer of power amplifier of the present invention;

Figure 24 shows the block diagram of the 7th example TX path part of FEM circuit;

Figure 25 shows the block diagram of the 8th example TX path part of FEM circuit;

Figure 26 A shows the AS block diagram of example DC-DC transducer of the present invention;

Figure 26 B shows the high level block diagram of the synchronous DC-DC step-down controller of example of the present invention;

Figure 27 shows the block diagram of the example DC-DC transducer that comprises fine-adjusting unit of the present invention;

Figure 28 shows the figure of the output voltage of DC-DC converter circuit;

Figure 29 shows the figure of rising edge of the output voltage of DC-DC converter circuit;

Figure 30 shows the figure of trailing edge of the output voltage of DC-DC converter circuit;

Figure 31 shows the block diagram of the 9th example TX path part of FEM circuit;

Figure 32 shows the block diagram of the example DC-DC transducer that comprises a plurality of fine-adjusting units of the present invention;

Figure 33 shows the figure for the output voltage of the DC-DC change-over circuit of RF input;

Figure 34 is the figure that has been shown in further detail the output voltage of the DC-DC change-over circuit of inputting for RF;

Figure 35 shows the schematic diagram of the first example TX/RX switch;

Figure 36 shows the schematic diagram of the second example TX/RX switch;

Figure 37 shows the schematic diagram of example antenna RF switch;

Figure 38 shows the curve chart of the power added efficiency (PAE) that depends on power output;

Figure 39 shows the curve chart of the power output that depends on input power;

Figure 40 shows the AM2AM of power amplifier circuit and the curve chart of AM2PM response;

Figure 41 shows the linearizing curve chart that power amplifier circuit of the present invention is realized;

Figure 42 shows the curve chart that power amplifier is kept out of the way working region RF signal before and afterwards;

Figure 43 shows the curve chart for the frequency spectrum of the power amplifier of QAM64;

Figure 44 shows the curve chart of dynamically keeping out of the way time domain RF ofdm signal before and afterwards for QAM64;

Figure 45 shows the curve chart for the reception of QAM64 and transmission planisphere;

Figure 46 shows the curve chart for the frequency spectrum of the power amplifier of QAM256;

Figure 47 shows the curve chart of dynamically keeping out of the way time domain RF ofdm signal before and afterwards for QAM256;

Figure 48 shows the curve chart for the reception of QAM256 and transmission planisphere; And

Figure 49 shows the high level block diagram of the exemplary wireless device that comprises FEM circuit of the present invention.

Embodiment

RF circuit such as transceiver is manufactured to integrated circuit conventionally, because microdevice size and lower cost, described integrated circuit is used complementary metal oxide semiconductors (CMOS) (CMOS) technology conventionally.Small size cmos device reduces Current draw and requires lower cell voltage, thereby is suitable for having the portable use of a large amount of power consumption constraints.Wireless communication link must be reliably and width from there is high data throughput, this needs higher power level at antenna output end.For example, above-mentioned WLAN and Bluetooth require conventionally as 20dBm (being 100mW) or more power level.

But higher power stage requires higher electric current and voltage levvl in RF circuit.Current many cmos devices adopt 0.18 micron of explained hereafter, and AS utilizes 130 nanometers, 90 nanometers, 65 nanometers and 45 nanometer technologies.Due to the puncture voltage of the reduction of the semiconductor device in integrated circuit, resulting integrated circuit operating voltage at 1.8V to the scope lower than 1.2V.Particularly for there is the signal of envelope variation in the situations such as OFDM, QPSK, QAM, be difficult to reach 1.8V+power level of 20dBm.Increase power requirement and conventionally can cause decrease in efficiency, this is because more the power of vast scale is lost as heat, subsequently shorter battery life.In addition,, for having the identical power level that increases electric current, impedance has been lowered.Considering that most RF circuit are designed to have 50Ohm impedance, due to the power loss increasing, is also problematic for the design of the match circuit of the impedance that is lowered.

Conventional transceiver for honeycomb, WLAN, Bluetooth, ZigBee etc. conventionally can not generate enough power or not have enough RX sensitivity, and communication reliably needs enough RX sensitivity under many circumstances.Current integrated circuit transceiver components has the transmit power level lower than 0dBm, although also there are some devices to have 10 or the power level of 20dBm, but still is lower than required 20-25dBm.Therefore, the adjusting of extra RF signal is necessary.

Circuit between transceiver and antenna is commonly called front-end module or FEM.Described FEM comprises the low noise amplifier (LNA) for increasing the power amplifier of transmitted power and raising receiving sensitivity.Can also comprise the various filter circuits such as band pass filter, clean transmitted signal to be provided at antenna place and to protect receiving circuit to avoid arriving the external blocking signal of antenna.Described FEM also comprises RF switch, to switch fast between reception and sending function, and prevents the interference in the transition process between sending and receiving.Described RF switch can be controlled by the universal input/output line of transceiver and/or the control protocol of deciding through consultation in advance.Described RF switch is understood to individual antenna to be connected to the single-pole double-throw switch (SPDT) of the input of low noise amplifier or the output of power amplifier.The transceiver (transceiver for example using in conjunction with bluetooth and ZigBee system) with shared sending and receiving line comprises the 2nd RF switch at the input of power amplifier and the output of low noise amplifier conventionally, for suitably controlling the sending and receiving line of transceiver end.Described the 2nd RF switch (it has strengthened TX/RX isolation) can be controlled by same universal input/output line of controlling the transceiver of a described RF switch.Described power amplifier also can open or cut out by the output that enables from transceiver.Described enable line can change voltage with ride gain or power amplifier bias electric current is set.

Associated performance, manufacture and Cost Problems make to be necessary to manufacture RF switch on the different substrate of the substrate from power amplifier and low noise amplifier.Power amplifier is manufactured conventionally on GaAs (GaAs) substrate, and it provides high-breakdown-voltage and reliability.Also can utilize other substrate, as SiGe (SiGe).In addition, power amplifier can utilize heterojunction bipolar transistor (HBT), metal-semiconductor field effect transistor (MESFET) or High Electron Mobility Transistor (HEMT), and wherein HBT manufacturing cost is minimum.Low noise amplifier also can be manufactured on to be had on the transistorized GaAs substrate of HBT.Yet, due to high insertion loss or low isolation, adopt the transistorized RF switch of HBT to there is poor performance characteristics.

A solution of the problems referred to above comprises uses Multi-core configuration, and in this configuration, power amplifier and low noise amplifier are manufactured on one and use on the transistorized tube core of HBT, and RF switch is manufactured on another and for example uses on the transistorized tube core of HEMT.Subsequently, two tube cores are encapsulated in single package.Compare traditional silicon substrate, the cost of the increase associated with GaAs substrate and complicated packaging technology have further promoted the cost of front-end module circuit.Another kind of solution relates to the compound GaAs substrate for power amplifier, low noise amplifier and RF switch, and it has HBT and HEMT transistor.But this integrated circuit manufacturing cost is higher.Alternatively, silicon substrate can be used for low noise amplifier, power amplifier and RF switch.Yet, because the isolation of silicon substrate is poor, the solution that possible use cost is higher, for example silicon on insulator (SOI).These integrated circuits need negative voltage generator conventionally, and this causes larger tube core for biasing circuit.In addition, by the glitch on the wide frequency ranges of the charge pump transmitting for negative voltage generator, need physical isolation, this has further increased die-size.

The invention provides a kind of FEM circuit, solved the problem of above-mentioned proposition.FEM circuit of the present invention provides high linearity and power efficiency and has met the requirement of Modern wireless communication standard (such as 802.11WLAN, 3G and 4G cellular standards etc.).In addition, the configuration of FEM circuit allows to use semiconductor fabrication common, relatively low cost, such as the CMOS technique that provided on the market.

Fig. 1 shows according to the present invention and the block diagram of the example two-band multi-chip front-end module (FEM) that builds.Described double frequency-band FEM module (being denoted as generally 10) comprises four modules, comprising duplexer 52,2.4GHz FEM circuit module 40,5GHz FEM circuit module 28 and Power Management Unit (PMU) module 12.Described 2.4GHz FEM circuit 28 operationally receives and transmitted signal at 2.4GHz ISM frequency band, and 5GHz FEM circuit operationally receives and transmitted signal at 5GHz ISM frequency band.Described in each, module can be structured on independent integrated circuit, and printing or wire bond that described independent integrated circuit has between chip connect.Alternatively, FEM module can comprise single integrated circuit and/or can process single frequency band.

Duplexer 52 work is with by one or more antenna-coupleds to 2.4 and 5GHz antenna port.PMU12 is optional in circuit, it can comprise following partly or entirely: DC-DC transducer 24 (for example, 3.3V), electrify restoration circuit 20, the oscillating circuit 22 for generation of clock signal, biasing circuit and RF power ramping rise control, the DC-DC change-over circuit 26 for the power amplifier (PA) of 2.4GHz, DC-DC change-over circuit 18, clock monitoring circuit 18 and the control logic 14 for 5GHz PA.

Described 2.4GHz FEM circuit module 40 comprises TX/RX switch 46, power amplifier circuit 42, low noise amplifier (LNA) circuit 44, control logic 48 and interface (I/F) logic 50.Described PA42 work to amplify baseband circuit output for by the TX signal of antenna broadcast.Described LNA44 work to amplify from antenna reception to reception signal, and export RX signal so that by baseband circuit demodulation code.

Similarly, described 5GHz FEM circuit module 28 comprises TX/RX switch 34, power amplifier circuit 30, low noise amplifier (LNA) circuit 32, control logic 36 and interface (I/F) logic 38.Described PA30 work to amplify baseband circuit output for by the TX signal of antenna broadcast.Described LNA32 work to amplify from antenna reception to reception signal, and export RX signal so that by baseband circuit demodulation code.

Fig. 2 shows according to the present invention and the block diagram of the example single-chip FEM circuit that builds.Single-chip FEM circuit (being denoted as generally 130) comprising: PA circuit 132, for amplifying from the TX signal of baseband circuit, to pass through one or more antennas 140, broadcast; LNA134, for amplify from one or more antenna receptions to signal and export RX signal so that by baseband circuit demodulation code; TX/RX switch 136, for being coupled to antenna by PA or LNA; Optional duplexer 138, for being coupled to TX/RX switch on one or more antennas 140; Control logic 142; I/F logical one 44 and DC-DC change-over circuit 146.

For example, in the system that adopts space diversity, can use a plurality of antennas 140.In mimo system, adopt a plurality of antennas but each antenna has and its own relevant FEM circuit, wherein, in baseband circuit, by signal, processes the generation of synthetic and a plurality of transmitted signals of carrying out a plurality of reception signals.

Fig. 3 show according to the present invention and build the block diagram of example DC-DC transducer.Described DC-DC converter circuit (being denoted as generally 700) comprises synchronous DC-DC transducer 708, vernier control logic 704, one or more fine-adjusting unit 706, one or more trimmer capacitor 710, one or more output capacitor 712 and one or more output inductor 714.The function of described DC-DC converter circuit is to generate output voltage according to the vernier control command signal that is input to vernier control logic.Envelope detector (not shown) can be used for generating vernier control order, makes generated output voltage follow the tracks of RF input signal.Be described in more detail hereinafter the operation of described DC-DC converter circuit.

Fig. 4 shows according to the present invention and the block diagram of the example TX path part of the FEM circuit that builds.Described TX path circuit (being denoted as generally 150) comprise from described reflector or transceiver (TRX) receive the matching network 152, programmable delay 154 of RF input signal, for generating PA156, control logic module 158, the envelope detector 160 of RF output, 170, low pass filter (LPF) 162,172, power detector 164,174 and analog to digital converter (ADC) 166,176.

In this exemplary embodiment, envelope detected is used to RF input and RF output, to optimize the operation of PA.Follow the tracks of gain and optional other parameter (by control logic module 158) of described RF input signal and adjustment PA, to improve to greatest extent the power consumption of the linearity and minimizing circuit.

Fig. 5 shows the block diagram of the first example TX path part of FEM circuit.Described TX path (being denoted as generally 180) comprises programmable delay 182, bimodulus power amplifier circuit 184, many tapped transformers 188, pattern/biasing control 198, envelope detector 190,200, LPF192, ADC194,202 and control logic 196.

In this exemplary embodiment, use envelope detected to follow the tracks of RF input and RF output signal.The envelope signal generating is for configuring one or more operating parameters of bimodulus PA184, to improve to greatest extent the linearity, gain etc., and reducing to greatest extent power consumption.Hereinafter be described in more detail the operation of double mode PA.In operation, feedforward arithmetic is carried out envelope detected at the input end to power amplifier.A/D converter sampled envelope signal.Digital control logic work is controlled to drive PA to setover according to envelope level, thereby enables corresponding PA transistor, via the synthetic transistorized output of corresponding PA of many tapped transformers.Programmable delay work is with the delay between compensation envelope detector and RF signal path.The use of feedforward arithmetic has realized the improved efficiency showing, and as shown in Figure 41, wherein, trace 540 represents to carry out the power added efficiency (PAE) before linearisation by the feedforward arithmetic of Fig. 5, the PAE that trace 542 represents after linearisation.

The wireless standard in many modern times, for example 802.11 and 802.11ac particularly, its modulation generating causes signal to have larger peak-to-average force ratio.Consider for example orthogonal frequency division modulated (OFDM), peak-to-average force ratio increases with sub-carrier number object and is approximately 20log (sub-carrier number).For example, adopt the OFDM of 256 subcarriers to modulate the peak-to-average force ratio that can produce 10-12dB.In addition, in each subcarrier, adopt 256QAM to need Error Vector Magnitude (EVM) relatively preferably, for example ,-32dB.Non-linear, the adjacent channel leakage ratio (ACLR) of the phase noise of noise, distortion, glitch, IQ mismatch and PLL, power amplifier all makes EVM reduce.Therefore, to the overall linearity of power amplifier and FEM circuit, require relative strict.In addition, expectation reduces the consumption of battery as far as possible, therefore requires the circuit of FEM to have high efficiency.

In addition, in one embodiment, complementary metal oxide semiconductors (CMOS) (CMOS) integrated circuit technique of expectation use standard builds FEM circuit.Alternatively, described FEM circuit can be used any suitable semiconductor technology, as GaAs (GaAs), SiGe (SiGe), indium gallium phosphide (InGaP), gallium nitride (GaN) etc.But, wish that using CMOS technology is due to lower cost and complexity, and can analog circuit and Digital Logic is integrated.

In one embodiment, with a plurality of sub-power amplifiers or sub-amplifier 186, build described power amplifier circuit 184.Input signal is by shunt and be fed to every sub-amplifier, and it provides a part for total required gain of described power amplifier.The output of every sub-amplifier is synthesized to generate RF output signal.In one embodiment, synthesizer unit comprises many tapped transformers, will be described in more detail below an example of described many tapped transformers.

In operation, the envelope that envelope detector 190 is read RF input and generation signal represents, then by its filtration and digitlization, and is input to control logic circuit 196.Read equally described RF output, and the digitlization envelope that generates signal represents, and is input to control logic circuit 196.The biasing of sub-amplifier 186 is biased control circuit 198 and controls, and it is driven by the one or more control signal from controlling logical one 96.Described programmable delay has compensated by the signal delay of envelope detector and digitization step.

Fig. 6 shows the block diagram of the second example TX path part of FEM circuit.This TX path (being designated as generally 210) comprises that bimodulus power amplifier 218, power controller 212, DC-DC transducer 214 and effect are the ouput power detection circuits 216 of reading RF output.

In the present embodiment, the gain of power amplifier is controlled by power control signal.In response to power control signal and power output level, power controller generates the control signal for DC-DC transducer, the supply voltage of its modulation power amplifier.Depend on specific implementation, described power amplifier 218 can comprise one or more sub-amplifiers.

Fig. 7 shows the block diagram of the 3rd example TX path part of FEM circuit.Described TX path (being denoted as generally 220) comprises limiter 232, bimodulus power amplifier 234, envelope detector 222, programmable delay 224, adjuster/buffer 226, ADC228 and quick DC-DC transducer 230.In operation, described circuit amplifies TX signal in the mode of polarity, and wherein, the confined TX signal of isolating amplitude is imported into PA.The gain of controlling and adjusting described PA is to follow the tracks of the amplitude of initial TX signal.Read described RF input and generate envelope and carry out digitlization by ADC228.DC-DC transducer 226 driving regulators or buffer circuits 226 are to generate the gain (or power supply) of PA234 fast.Depend on specific implementation, described power amplifier 234 can comprise one or more sub-amplifiers.

Fig. 8 shows the block diagram of the 4th example TX path part of FEM circuit.This TX path (being denoted as generally 240) comprises drive circuit/buffer 242, power splitter 244, one or more difference subspace amplifier 246 and power combiner 250.In operation, RF input signal is imported into drive circuit, and the output of drive circuit is imported into splitter.This splitter work is to provide input signal to arrive every sub-amplifier 246.In one embodiment, splitter comprises that to have 248, one of many tapped transformers of armature winding and a plurality of secondary winding secondary for every sub-amplifier.Every sub-amplifier can be suitable for processing difference (as shown in the figure) or single-ended input signal.The difference output of every sub-amplifier is coupled to the respective primary winding of the synthetic transformer 252 of many taps.At secondary winding place generating output signal, and provide the RF of TX path circuit to export.The impedance that it should be noted that each tapping is suitable for being about 12.5Ohm, to produce the expectation RF output impedance of about 50Ohm.

In operation, each of synthon amplifier exports to generate RF output signal.Every sub-amplifier provides a part for the required gross power of power amplification circuit.By the many tapped transformers of synthesizer, the power that synthetic every sub-amplifier generates, to generate the RF output signal with synthetic total RF power.

They it should be noted that differential amplifier (or balance amplifier) is preferred, because can make the voltage swing that can be applied in equally loaded double.This will make power output change quadruple, and can on transistor, not produce any extra stress.Therefore, utilize difference subspace amplifier stage and realize high efficiency power amplifier.

In one embodiment, splitter and synthetic transformer are all manufactured and are integrated on same tube core with other analogy and digital circuit with CMOS.In alternative, transformer adopting other technologies are manufactured, as GaAs, InGaP, GaN etc.Described transformer comprises air-core and may take any suitable shape and configuration.A plurality of examples of integrated many tapped transformers will be described in more detail hereinafter.Note, in one embodiment, transformer is configured to relative broadband, can be applicable to 2.4 and 5.8GHz WLAN signal.Alternatively, from two transformers and two band pass filters, build duplexers, transformer and band pass filter are for a frequency band.It should be noted that FEM circuit of the present invention can not only be applied to WLAN signal, also can be applied to any modulation scheme that represents high peak-to-average force ratio, for example, 3G, 4G LTE etc.

Fig. 9 shows the block diagram of the 5th example TX path part of FEM circuit.This TX path (being denoted as generally 259) comprises driver/demultiplexer circuit 241, one or more difference subspace amplifier 251 and power combiner 243.Described driver/demultiplexer circuit 241 comprises many tapped transformers 245, and it has armature winding and two secondary winding, and a secondary winding is corresponding to a differential driver 247.Many tapped transformers 255 comprise one to one to two transformers, and each has the armature winding that is associated with driver 247 and for the secondary winding of two sub-amplifiers 251.Synthesizer 243 comprises many tapped transformers 253, and it has the armature winding that is associated with every sub-amplifier 251 and for generating the secondary winding of RF output signal.

In operation, RF input signal is imported into drive circuit 241, and it is two signals by RF input signal along separate routes.Each signal is imported into driver 247, and the output of driver 247 is further two signals along separate routes.Described splitter work is to provide input signal to arrive every sub-amplifier 251.In one embodiment, splitter comprises transformer 245,255 and drive circuit 247.Every sub-amplifier can be suitable for processing difference (as shown in the figure) or single-ended input signal.The difference output of every sub-amplifier is coupled to the respective primary winding of the synthetic transformer 253 of many taps.Generating output signal in secondary winding, and provide the RF of TX path circuit to export.The impedance that it should be noted that each tapping is suitable for being about 12.5Ohm to produce the RF output impedance of required approximately 50Ohm.

In operation, from the synthetic of each output of sub-amplifier, generate described RF output signal.Every sub-amplifier contributed a part for the gross power of required power amplification circuit.The power generating by the synthetic every sub-amplifier of described synthetic many tapped transformers, to generate the RF output signal with synthetic total RF power.

In one embodiment, splitter and synthetic transformer are all manufactured with CMOS, and are integrated on same tube core with other analogy and digital circuit.In alternative, described transformer uses other technology manufacture, such as GaAs, GaN etc.Described transformer comprises air-core and may take any suitable shape and configuration.A plurality of examples of integrated many tapped transformers will be described in more detail hereinafter.

Figure 10 shows the block diagram of the 6th example TX path part of FEM circuit.This TX path (being denoted as generally 260) comprises drive circuit 262, power splitter 264, four the sub-power amplifiers 266 of bimodulus and power combiners 272.In operation, RF input signal is imported into drive circuit.Then the output of driver is by along separate routes and be fed to every sub-amplifier.In the present embodiment, the quantity of sub-amplifier is 4, but also can use any amount according to concrete realization.Every sub-amplifier provides a part for total required gain.The output of described sub-amplifier is synthesized to generate RF output signal.

In one embodiment, parallel running every the sub-amplifier forming in the one or more sub-power amplifier of power amplifier are identical, comprise independently high and low amplifier.Described high amplifier is operated in relatively large keeping out of the way (backoff) (for example 12dB), is suitable for processing visible peak value input amplitude in about 5% time.In one embodiment, described high amplifier is implemented as C quasi-nonlinear amplifier, and it has suitable biasing to amplify expeditiously peak signal.Low amplifier is operated in lower keeping out of the way (for example 6dB), and is suitable for processing visible lower average input amplitude in about 95% time.In one embodiment, described low amplifier is implemented as AB class linear amplifier, its have suitable biasing with high linearity amplify average signal.It should be noted that in alternative, every sub-amplifier can comprise plural amplifier and can be implemented as the amplifier using outside AB class and C class, and this depends on specific application.

It should be noted that, in every sub-amplifier, use independently high and low amplifier, this will make power amplifier and FEM circuit meet the strict linearity of modern wireless standards (such as 802.11Wi-Fi (especially 802.llac), LTE, 3G, 4G etc.) and the requirement of spectrum efficiency, but the signal of these standards has higher peak-to-average force ratio, provide relatively high efficiency, cause battery consumption to minimize.

Figure 11 shows the block diagram of the low and high part of power amplifier circuit in more detail.Described circuit (being denoted as generally 280) represents a sub-amplifier of power amplification circuit 266 (Figure 10).In one embodiment, four identical sub-amplifiers are used to generate total power demand gain.Although in alternative, they may be not identical.Described circuit 280 comprises high circuit paths and low circuit path.Described high path comprises match circuit 282,286 and high power amplifier 285.Described low path comprises match circuit 290,294 and power amplifier 292.The output of power combiner (for example, many tapped transformers) 288 synthetic height and low amplifier, to generate the RF output of a sub-amplifier.The in the situation that of high and low circuit path, the synthetic transformer of many taps comprises for forming the height of every sub-amplifier (being 4 in this exemplary embodiment) and the tap of low sub-amplifier output of described power amplifier.

Figure 40 shows high and the AM2AM in low circuit path and the curve chart of AM2PM performance.Track 530 represents low circuit response, and track 534 represents to depend on the high Circuit responce of power output.Track 526 represents synthetic response.Equally, track 532 represents low circuit response, and track 536 represents to depend on the high Circuit responce of power output.Track 528 represents synthetic response.

Figure 12 A shows in detail the schematic diagram of the first example of sub-amplifier circuit.Described sub-amplifier circuit (being denoted as generally 360) work is to amplify the difference RF input signal that is applied to PA IN+ and PA IN-end.Described circuit comprises that transistor current modulation topology is to amplify described RF input signal.The output of one or more examples of sub-amplifier is combined to, to generate the RF output signal with required overall gain.The positive side of sub-amplifier comprises capacitor 362,368,377, resistor 372,374, transistor 364,370,378, low-power biasing circuit 376, high power biasing circuit 366 and there are power amplifier armature winding 384 (L _pA) and the transformer 379 of secondary winding 382.Equally, the minus side of sub-amplifier comprises capacitor 402,398,393, resistor 404,406, transistor 400,396,394, low-power biasing circuit 390, high power biasing circuit 392 and there are power amplifier armature winding 386 (L _pA) and the transformer 380 of secondary winding 388.

In operation, the low power transistor of positive negative circuit is biased, and with the linear A/AB class A amplifier A with acting on mean amplitude of tide input, and the high-capacity transistor of positive negative circuit is biased, with the high efficiency C class A amplifier A with acting on peak amplitude input.By electric current, synthesize the power that the height of sub-amplifier and lower part are generated synthetic in transformer circuit (370,364 and 396,400).The sub-amplifier output that Figure 12 B shows integrated transformer 381 in more detail connects.

Figure 13 A shows the schematic diagram of the second example of sub-amplifier circuit in more detail.Described sub-amplifier circuit (being denoted as generally 300) work is to amplify the difference RF input signal that is applied to PA IN+ and PA IN-end.The output of one or more examples of sub-amplifier is combined to, to generate the RF output signal with required overall gain.

The positive side of described sub-amplifier comprises capacitor 302,317,319,322, resistor 304,329, transistor 318,320 and 308,324, low-power biasing circuit 326 and high power biasing circuit 328 and there are low armature winding 312 (L _lO), high armature winding 316 (L _hI) and the transformer 310 of secondary winding 314 (PA OUT+).Equally, the minus side of sub-amplifier comprises capacitor 330,347,349,352, resistor 332,359, transistor 348,350 and 334,354, low-power biasing circuit 356 and high power biasing circuit 358 and there are low armature winding 342 (L _lO), high armature winding 346 (L _hI) and the transformer 340 of secondary winding 344 (PA OUT-).

In operation, the low power transistor of positive negative circuit is biased, and with the linear A/AB class A amplifier A with acting on mean amplitude of tide input, and the high-capacity transistor of positive negative circuit is biased, with the high efficiency C class A amplifier A with acting on peak amplitude input.In the present embodiment, by electric current, synthesize the power that the height of sub-amplifier and lower part are generated synthetic in transformer circuit (312,316 and 342,346).The sub-amplifier output that Figure 13 B shows described integrated transformer 341 in more detail connects.

In one embodiment, high and low armature winding 312,316 (342,346) is corresponding to the height in Figure 16 and low armature winding 502,504.Secondary winding 314 (344) is corresponding to the secondary winding 518 in Figure 16.

Figure 14 shows the schematic diagram of the 3rd example of sub-amplifier circuit in more detail.This sub-amplifier circuit is similar with and circuit high-capacity transistor path low having shown in Figure 13.Difference is to have increased the second high-capacity transistor (HP1) that is parallel to low power transistor (LP).

Described sub-amplifier circuit (being denoted as generally 410) work is to amplify the differential input signal that is applied to PA IN+ and PA IN-end.The output of one or more examples of described sub-amplifier is combined to, to generate the RF output signal with required overall gain.

The positive side of described sub-amplifier comprises capacitor 412,416,440,419,433, resistor 415,419,443, transistor 418 (LP), 414 (HP1), 442 (HP2) and 420,434, low-power biasing circuit 417, high power 1 biasing circuit 413 and high power 2 biasing circuits 441 and have low armature winding 422 (L _lO), high armature winding 426 (L _hI) and the transformer 419 of secondary winding 424 (PA OUT+).Equally, the minus side of sub-amplifier comprises capacitor 446,450,454,435,437, resistor 447,451, and 455, transistor 448 (LP), 452 (HP1), 444 (HP2) and 436,438, low-power biasing circuit 449, high power 1 biasing circuit 453 and high power 2 biasing circuits 445 and there are low armature winding 432 (L _lO), high armature winding 428 (L _hI) and the transformer 421 of secondary winding 430 (PA OUT-).

In operation, the low power transistor of positive negative circuit is biased, with the linear A/AB class A amplifier A with acting on mean amplitude of tide input, and high power 1 and high power 2 transistors of positive negative circuit are biased, with the high efficiency C class A amplifier A with acting on peak amplitude input.In the present embodiment, the power that the height of sub-amplifier and lower part generate is magnetically synthesized in transformer circuit (422,426 and 428,432).

In one embodiment, high and low armature winding 422,426 (432,428) is corresponding to the height in Figure 16 and low armature winding 502,504.Secondary winding 424 (430) is corresponding to the secondary winding 518 in Figure 16.

The power synthetic technique of FEM circuit utilization of the present invention based on transformer is to generate RF output signal.The synthetic use of power based on transformer has increased the power output ability of FEM.Power amplifier is divided into a plurality of sub-amplifiers (being in this example 4), and 1/4th every sub-amplifier series connection of power is provided.The particular technology that depends on employing, this can reduce or eliminate the problem of any transistor stress to greatest extent.Each 1/4th (being sub-amplifier) is further divided into height and partial low-power.Than using the sub-amplifier of single transistor, this makes efficiency increase by 40% at most.

With reference to figure 8 and 9, armature winding is by independent sub-amplifier PA1, PA2, and PA3, PA4 drives, and secondary winding is connected in series.The power that is delivered to load equals the summation of the power output generating of every sub-amplifier.It should be noted that some power may consume in being coupled to any matching network of transformer.

Therefore, not only effectively the superposeed alternating voltage of each sub-amplifier of power combiner, has also realized the function of impedance transformation.On secondary winding due to each transformer, carry identical electric current, therefore described sub-amplifier is coupled to each other.Therefore the impedance of, being seen by every sub-amplifier is determined by output voltage and the output impedance of other sub-amplifier.As fruit amplifier has identical output impedance, generates identical output voltage and transformer has identical turn ratio, the impedance that every sub-amplifier seen is determined by the turn ratio of each transformer and the quantity of parallel stage (being 4 in this exemplary embodiment).

Figure 15 shows for synthesize the layout of integrated transformer according to the first example power of power amplifier of the present invention.Described transformer (being denoted as generally 460) comprises four armature windings arranging with two dimension (2D) square, wherein, winding 462 is coupled to the output of sub-power amplifier 1, winding 464 is coupled to the output of sub-amplifier 2, winding 466 is coupled to the output of sub-power amplifier 3, and winding 468 is coupled to the output of sub-power amplifier 4.Secondary winding 470 is wrapped in four armature windings around and is coupled to TX/RX switch.It should be noted that in the present embodiment, magnetic field is around line of symmetry 461 and 463 and symmetrical.Width, spacing and thickness that described transformer has air-core and metal level are configured to for example, enough performances are provided and make input and output impedance meet required inductance and the Q factor at each frequency band (, 2.4GHz and 5GHz).It should be noted that according to different application, can implement the alternative arrangements of Transformer Winding.For example, primary and secondary winding can be realized on identical or different metal level.

Figure 16 shows the layout for the second example integrated transformer of power amplifier of the present invention.Described transformer (being denoted as generally 500) comprises four groups of octagonal armature windings and a square secondary winding.Each is organized armature winding in parallel and comprises He Di loop, high loop, for example to adapt to height and the low amplifier at the sub-amplifier shown in Figure 12 A, 12B, 13A, 13B, 14.The interior winding of each group armature winding from high amplifier and outer winding from low amplifier.Middle winding is secondary winding, and it extends between armature winding.It should be noted that separated advantage high and that low-power winding has has been to provide the method for the phase distortion of controlling better every sub-amplifier, thereby synthetic control of improvement of total phase distortion of power amplifier is provided.In addition, outer (or interior) winding of stretching winding is also for compensating the phase distortion between PA amplifier.Use multiple technologies described herein can make FEM reach maximum efficiency and minimum EVM.

Specifically, integrated transformer comprises winding 502,504,506,508,510,512,514,516 and secondary winding 518, and wherein, winding 504 is coupled to the low difference output of sub-amplifier 1, and winding 502 is coupled to the high difference output of sub-amplifier 1; Winding 508 is coupled to the low difference output of sub-amplifier 2, and winding 506 is coupled to the high difference output of sub-amplifier 2; Winding 512 is coupled to the low difference output of sub-amplifier 3, and winding 510 is coupled to the high difference output of sub-amplifier 3; Winding 516 is coupled to the low difference output of sub-amplifier 4, and winding 514 is coupled to the high difference output of sub-amplifier 4.It should be noted that the outer armature winding of each transformer is coupled to low output rather than the interior winding of sub-amplifier, this is because outer winding is longer and inductance is larger.The shorter interior winding coupled of length arrives the high-power output of every sub-amplifier.Secondary winding 518 is wrapped in four between the armature winding of '+' and '-', and is coupled to TX/RX switch.Between '+' and '-' armature winding, extend secondary winding and can improve magnetic coupling between the two.Width, spacing and thickness that described transformer has air-core and metal level are configured to for example, enough performances are provided and make input and output impedance meet required inductance and the Q factor at each frequency band (, 2.4GHz and 5GHz).It should be noted that according to different application, can implement the alternative arrangements of Transformer Winding.

Figure 17 shows the layout for the 3rd example integrated transformer of power amplifier of the present invention.Described transformer (being denoted as generally 570) comprises four groups of octagonal armature windings and a square secondary winding.Each group armature winding comprises two parallel windings.Middle winding is secondary winding, and it extends between parallel armature winding.This has reduced current crowding (approaching) effect, thereby reduces loss because electric current is more evenly dispersed in secondary winding.

Specifically, integrated transformer comprises four groups of windings, and each group is associated with a differential amplifier respectively.Every group of winding comprises parallel armature winding 572,574 and secondary winding 576.Described parallel armature winding is coupled to sub-amplifier PA1, PA2, PA3 and PA4.Parallel armature winding can make transformer process higher electric current.Secondary winding 576 is wrapped between four parallel armature windings and is exported to generate PA by connector 579, the TX/RX switch that described PA output is coupled to subsequently.Between parallel armature winding, extending secondary winding has improved magnetic coupling between the two and has alleviated closing effect mentioned above.Width, spacing and thickness that described transformer has air-core and metal level are configured to for example, enough performances are provided and make input and output impedance meet required inductance and the Q factor at each frequency band (, 2.4GHz and 5GHz).It should be noted that according to different application, can implement the alternative arrangements of Transformer Winding.

Figure 18 shows the layout for the 4th example integrated transformer of power amplifier of the present invention.Described transformer (being denoted as generally 560) comprises four groups of octagonal armature windings and a secondary winding, and they are arranged to continuous or linear array configurations.Each group armature winding comprises two parallel windings.This has reduced current crowding (approaching) effect, thereby reduces loss because electric current is more evenly dispersed in secondary winding.This has also increased the current handling capability of this transformer.Middle winding is secondary winding, and it extends between parallel armature winding.

Specifically, integrated transformer comprises four groups of windings, and each group is associated with a differential amplifier respectively.Every group of winding comprises parallel armature winding 562,564 and secondary winding 566.Parallel armature winding is coupled to sub-amplifier PA1, PA2, PA3 and PA4.Secondary winding 566 is wrapped between four parallel armature windings to generate the output of PA by connector 568, and described PA output is coupled to TX/RX switch subsequently.Between parallel armature winding, extending secondary winding has improved magnetic coupling between the two and has alleviated closing effect mentioned above.Width, spacing and thickness that described transformer has air-core and metal level are configured to for example, enough performances are provided and make input and output impedance meet required inductance and the Q factor at each frequency band (, 2.4GHz and 5GHz).It should be noted that according to different application, can implement the alternative arrangements of Transformer Winding.

In the circuit of Figure 19 A, the centre cap 588 of each transformer is connected to V _dD.Except the centre cap 588 of the transformer in Figure 19 A, parallel armature winding 582,584 and the operation class of secondary winding 586 are similar to the integrated transformer in Figure 18.

Figure 19 A shows the layout for the 6th example integrated transformer of power amplifier of the present invention.Described integrated transformer (being denoted as generally 571) comprises that each group is associated with a difference subspace amplifier respectively with four groups of windings of linear rows configuration.Each group winding comprises armature winding 581,583 and the secondary winding 585 of pair of parallel.Parallel armature winding in each group is coupled to height and the low circuit output of the sub-amplifier of in PA1, PA2, PA3 and PA4.In every group of winding, internal inductance device loop is used to the sub-amplifier of low-power and dispatch from foreign news agency sensor loop for the sub-amplifier of high power, for example, and at two cascade amplifiers shown in Figure 12 A, 12B, 13A, 13B.The centre cap 587 of each transformer is connected to V _dD.Secondary winding is placed between four groups of parallel armature windings by connector, and to generate the output of PA, described PA output is coupled to TX/RX switch subsequently.Between parallel armature winding, placing secondary winding has improved magnetic coupling between the two and has alleviated closing effect mentioned above.Width, spacing and thickness that described transformer has air-core and metal level are configured to for example, enough performances are provided and make input and output impedance meet required inductance and the Q factor at each frequency band (, 2.4GHz and 5GHz).It should be noted that according to different application, can implement the alternative arrangements of Transformer Winding.

Figure 19 C shows the layout for the 7th example integrated transformer of power amplifier of the present invention.Described integrated transformer (being denoted as generally 491) comprises that each group is associated with a difference subspace amplifier respectively with four groups of windings of linear rows configuration.Each group winding comprises armature winding 501,503 and the secondary winding 505 of pair of parallel.Parallel armature winding in each group is coupled to height and the low circuit output of the sub-amplifier of in PA1, PA2, PA3 and PA4.The centre cap 507 of each transformer is connected to V _dD.Should be noted that to be, for the winding of PA1 and PA4, be longer than the winding of (stretching) PA2 and PA3.The phase mismatch that this produces for compensating PA amplifier.

Secondary winding is placed between four groups of parallel armature windings by connector, and to generate the output of PA, described PA output is coupled to TX/RX switch subsequently.Between parallel armature winding, placing secondary winding has improved magnetic coupling between the two and has alleviated closing effect mentioned above.Width, spacing and thickness that described transformer has air-core and metal level are configured to for example, enough performances are provided and make input and output impedance meet required inductance and the Q factor at each frequency band (, 2.4GHz and 5GHz).It should be noted that according to different application, can implement the alternative arrangements of Transformer Winding.The configuration of this configuration and any integrated transformer as described herein can be used for the configuration of any sub-amplifier mentioned above, i.e. Figure 12 A, 12B, 13A, 13B and 14 circuit.

Figure 20 shows the layout for the 8th example integrated transformer of power amplifier of the present invention.Described transformer (being denoted as generally 590) comprises 594, four sub-amplifiers 604 of splitter and synthesizer 606.Described splitter comprises an armature winding 600 and four groups of octagonal secondary winding, and they are arranged to continuous or linear row array configurations.Every group of secondary winding comprises two parallel windings 596,598.This has increased the current handling capability of transformer.Middle winding is armature winding, and it extends between parallel secondary winding.

In order to reduce and to compensate any phase mismatch between each transformer in that difference between outside two PA1, PA4 transformer and inner two PA2, PA3 transformer causes, splitter as far as possible, difference output is intersecting between PA1 and PA2 winding and between PA3 and PA4 winding.

Described synthesizer comprises four groups of octagonal armature windings 610,608 and a secondary winding 611, and they are arranged to continuous or linear row array configurations.Each group armature winding comprises two parallel windings.This has reduced current crowding (approaching) effect, thereby reduces loss because electric current is more evenly dispersed in secondary winding.This has also increased the current handling capability of this transformer.Middle winding is secondary winding, and it extends between parallel armature winding.

Specifically, splitter and synthesizer all comprise four groups of windings, and each group is associated with in difference subspace amplifier PA1, PA2, PA3 and PA4 one.Described RF input signal is imported into buffer 592, and its difference output is applied to the armature winding of splitter transformer.The parallel secondary winding of each transformer of described splitter is coupled to the corresponding difference input of sub-amplifier.Armature winding 600 is wrapped between four groups of parallel secondary winding, to be generated to four signal inputs of sub-amplifier.The output of every sub-amplifier is imported into corresponding transformer in synthesizer.Secondary winding 611 is wrapped between four groups of parallel armature windings 610,608 and exports to generate PA, and described PA output is coupled to TX/RX switch subsequently.Width, spacing and thickness that transformer in described splitter and synthesizer all has air-core and metal level are configured to for example, enough performances are provided and make input and output impedance meet required inductance and the Q factor at each frequency band (, 2.4GHz and 5GHz).It should be noted that according to different application, can implement the alternative arrangements of Transformer Winding.

In a kind of substitute technology of any phase mismatch that overcomes transformer, tuning capacitor is added to each armature winding in synthesizer.But described capacitor may damage, thus the power gain of reduction power amplifier.Such circuit as shown in figure 21.The use of capacitor can make transformer realize the better phase compensation across Transformer Winding.It has also reduced parasitic drain and has caused lower phase place and fault in enlargement.

Described transformer (being denoted as generally 620) comprises splitter 624, four sub-amplifiers 634 and synthesizers 636.Described splitter comprises an armature winding 630 and four groups of octagonal secondary winding, and they are arranged to continuous or linear row array configurations.Every group of secondary winding comprises two parallel windings 626,628.This has increased the current handling capability of transformer.Middle winding is armature winding, and it extends between parallel secondary winding.

Described synthesizer comprises four groups of octagonal armature windings 638,640, secondary winding 642 and a capacitor 646, and they are arranged to continuous or linear row array configurations.Each group armature winding comprises two parallel windings.This has reduced current crowding (approaching) effect, thereby reduces loss because electric current is more evenly dispersed in secondary winding.This has also increased the current handling capability of this transformer.Middle winding is secondary winding, and it extends between parallel armature winding.

Specifically, splitter and synthesizer all comprise four groups of windings, and each group is associated with in difference subspace amplifier PA1, PA2, PA3 and PA4 one.Described RF input signal is imported into buffer 622, and its difference output is applied to the armature winding of splitter transformer.The parallel secondary winding of each transformer of described splitter is coupled to the corresponding difference input of sub-amplifier.Armature winding 630 is wrapped between four groups of parallel secondary winding, to be generated to four signal inputs of sub-amplifier.The output of every sub-amplifier is imported into the corresponding transformer in synthesizer.Secondary winding 642 is wrapped between four groups of parallel armature windings 638,640 and exports to generate PA, and described PA output is coupled to TX/RX switch subsequently.Width, spacing and thickness that the transformer of described splitter and synthesizer all has air-core and metal level are configured to for example, enough performances are provided and make input and output impedance meet required inductance and the Q factor at each frequency band (, 2.4GHz and 5GHz).It should be noted that according to different application, can implement the alternative arrangements of Transformer Winding.

In the another kind of substitute technology of any phase mismatch that overcomes transformer, make the armature winding (that is, PA2 and PA3 winding) of two internal transformers of described synthesizer be longer than the winding (that is, PA1 and PA4 winding) of two external transformers.This is effectively by the inductance value of being increased to L+ Δ L of two inner armature windings, and wherein L represents the inductance of two outside armature windings.This makes without the input to difference subspace amplifier is intersected.Such circuit as shown in figure 22.It should be noted that inductance increases the amount Δ L of approximately 20% (that is, every side 10%), is effective for reduce phase mismatch as far as possible.It is also to be noted that, the variation that changes the inductance L of ± 20%, PVT when the capacitor C 646 of the circuit for Figure 20 is roughly ± and 8%.

Described transformer (being denoted as generally 650) comprises splitter 654, four sub-amplifiers 662 and synthesizers 663.Described splitter comprises an armature winding 657 and four groups of octagonal secondary winding, and they are arranged to continuous or linear row array configurations.Every group of secondary winding comprises two parallel windings 656,658.This has increased the current handling capability of this transformer.Middle winding is armature winding, and it extends between parallel secondary winding.

Described synthesizer comprises four groups of octagonal armature windings (664,666) and (674,672) and a secondary winding 668,676, and they are arranged to continuous or linear row array configurations.As described above, corresponding to PA2 and PA3 two groups inner windings, there is longer winding, cause larger inductance L+Δ L.Each group armature winding comprises two parallel windings.This has reduced current crowding (approaching) effect, thereby reduces loss because electric current is more evenly dispersed in secondary winding.This has also increased the current handling capability of described transformer.Middle winding is secondary winding, and it extends between parallel armature winding.

Specifically, splitter and synthesizer all comprise four groups of windings, and each group is associated with in difference subspace amplifier PA1, PA2, PA3 and PA4 one.Described RF input signal is imported into buffer 652, and its difference output is applied to the armature winding of splitter transformer.The parallel secondary winding of each transformer of described splitter is coupled to the corresponding difference input of sub-amplifier.Armature winding 657 is wrapped between four groups of parallel secondary winding, to be generated to four signal inputs of sub-amplifier.The output of every sub-amplifier is imported into the corresponding transformer in synthesizer.Secondary winding 668,676 is wrapped between four groups of parallel armature windings (664,666) and (674,672) and exports to generate PA, and described PA output is coupled to TX/RX switch subsequently.Width, spacing and thickness that the transformer of described splitter and synthesizer all has air-core and metal level are configured to for example, enough performances are provided and make input and output impedance meet required inductance and the Q factor at each frequency band (, 2.4GHz and 5GHz).It should be noted that according to different application, can implement the alternative arrangements of Transformer Winding.

Figure 23 shows the layout for the 11 example integrated transformer of power amplifier of the present invention.In this alternate embodiment, in order to overcome the phase mismatch of transformer, make the armature winding (being PA2 and PA3 winding) of two internal transformers of synthesizer be longer than the armature winding (being PA1 and PA4 winding) of two external transformers.This is effectively by the inductance value of being increased to L+ Δ L of two inner armature windings, and wherein L represents the inductance of two outside armature windings.This makes without the input to difference subspace amplifier is intersected.Should be noted that to be, inductance increases the amount Δ L of approximately 20% (being every side 10%), for reduce phase mismatch as far as possible, is effective.It is also to be noted that, the variation that changes the inductance L of ± 20%, PVT when the capacitor C 646 of the circuit for Figure 20 is roughly ± and 8%.

Described transformer (being denoted as generally 680) comprises splitter 690, four sub-amplifiers 688 and synthesizers 692.This splitter comprises an armature winding 686 and four groups of rectangle secondary winding 684, and they are arranged to continuous or linear row array configurations.

Described synthesizer comprises armature winding 694 and a secondary winding 696 of four groups of rectangles, and they are arranged to continuous or linear row array configurations.As described above, corresponding to PA2 and PA3 two groups inner windings, there is longer winding, cause larger inductance L+Δ L.

Specifically, splitter and synthesizer all comprise four groups of windings, and each group is associated with in difference subspace amplifier PA1, PA2, PA3 and PA4 one.Described RF input signal is imported into buffer 682, and its difference output is applied to the armature winding of splitter transformer.The parallel secondary winding of each transformer of described splitter is coupled to the corresponding difference input of sub-amplifier.Armature winding 686 is around four groups of secondary winding, to be generated to four signal inputs of sub-amplifier.The output of every sub-amplifier is imported into the corresponding transformer in synthesizer.Secondary winding 696 is around four groups of armature windings 694 to generate PA output, and described PA output is coupled to TX/RX switch subsequently.Width, spacing and thickness that the transformer of described splitter and synthesizer all has air-core and metal level are configured to for example, enough performances are provided and make input and output impedance meet required inductance and the Q factor at each frequency band (, 2.4GHz and 5GHz).It should be noted that according to different application, can implement the alternative arrangements of Transformer Winding.

In battery-operated wireless system (as mobile phone), the normally the most significant power consumption assembly of RF power amplifier (PA).For minimizing power dissipation, system-level power management scheme is designed to operate RF PA in very wide output power range.When supply voltage is fixed, in the efficiency of the RF of lower power levels PA, be low-down, average power consumption and battery life are had a negative impact.In order to improve the overall efficiency of RF PA on broad power band, implement the dynamic control of supply voltage.

Efficiency power amplifier (PAE) is the key factor during the RF of modern wireless systems designs.For example, in cellular basestation, power consumption spends operator's millions of dollar every year.In smart mobile phone, because battery life declines and mobile phone heating, more pay close attention to the efficiency of PA.This poor efficiency be due to the 3G of most of up-to-date more speeds and 4G utilization such as the WCDMA of the quadrature amplitude modulation (QAM) on OFDM (OFDM) and the modulator approach Long Term Evolution (LTE).All these Technology Needs are the lower linear PA of efficiency in essence.Typical linear RF PA is operated in category-A or AB class realizes its linearity.Maximum theoretical efficiency is 50%, but in practice, the highest efficiency is in 30% to 35% scope.When amplifier is when compressing or moving, realize best this efficiency near compression point.When input signal in or compress while approaching its peak value.In up-to-date modulator approach, peak-to-average power ratio (PAPR) is very high.So for majority transmission, PA is operated in far below under compression point, thereby the outstanding linearity is provided, and efficiency average out to 20% or still less.The increased power that this can cause as heat dissipation, the overcurrent being drawn by PA can cause shorter battery life.

The present invention utilizes envelope-tracking to solve this problem, and it has replaced for the fixing DC power supply of the tradition of PA dynamically to follow the tracks of the amplitude of RF signal or the fast-changing DC power supply of envelope.It is two kinds of technology that are used for realizing efficient linear RF power amplifier that envelope-tracking (ET) and envelope are eliminated with recovering (EER).As shown in Figure 24 and Figure 25, in these two kinds of technology, the power supply after efficient modulation offers RF power amplifier by variable voltage.

Figure 24 shows the block diagram of the 7th example TX path part of the FEM circuit that comprises envelope-tracking.Described circuit (being denoted as generally 760) comprises input coupler 762, envelope detector 764, modulation power source 766 and linear RF power amplifier 768.In operation, by envelope detector, generated the envelope of described RF input signal and be entered into the power supply after modulation, the power supply after modulation generates the DC voltage output V consistent with the envelope of RF input signal _oUT.This Voltage-output is as the supply voltage of linear RF PA.It should be noted that DC-DC converter output voltage can be directly connected to PA supply voltage, so power buffer is optional because power amplifier is based on linear topology (being ET).

Figure 25 shows and comprises that envelope is eliminated and the block diagram of the 8th example TX path part of the FEM circuit of recovery.Described circuit (being denoted as generally 770) comprises power supply 776, limiter 778 and the linear R F power amplifier 779 after input coupler 772, envelope detector 774, modulation.In operation, envelope detector generates the envelope of RF input signal and is entered into the power supply after modulation, and the power supply after modulation generates the DC voltage output V consistent with the envelope of RF input signal _oUT.Described limiter generates phase reference signal, and phase reference signal is imported into non-linear PA.Described Voltage-output V _oUTsupply voltage as linear R F PA.It should be noted that because described PA, based on nonlinear topology (being EER), is not optional so use power buffer in this circuit.

By being described below, use the DC-DC transducer with very fast output voltage transformation to realize the technology of high efficiency envelope-tracking system.

Figure 26 A shows and realizes the system block diagram of controlling by the closed loop RF power of power supply.Described circuit (being denoted as generally 950) comprises RF power amplifier 956, output power detector 958, power controller piece 952 and DC-DC transducer 954.Output RF power is read out by detector 958, and compares with power control command signal.In response to the error between the RF power of reading and order power, the vernier control of described DC-DC transducer 954 is adjusted output voltage (V _oUT).Under stable state, the power output of measurement equals power control command ideally.In this system, with respect to the supply voltage for RF PA wherein, be constant more traditional realization, whole efficiency is improved and is depended on DC-DC transducer, and it can keep very high efficiency on very wide output voltage range and in power output level.The challenge facing at traditional DC-DC transducer of implementing for RF PA is the variation that the output voltage that need to provide very fast changes to respond RF PA power output.By what describe, be a kind of new method below, for provide output voltage very fast to change at described DC-DC transducer.

Figure 26 B show the synchronous DC-DC transducer of example AS block diagram (step-down (buck) topology for illustration purposes only, but can use boost, normal shock (forward) and any other DC-DC converter configurations).Described circuit (being denoted as generally 720) comprises input voltage V _in722, switch 724,726, switch driver 736, inductor L ₀728, capacitor C ₀730, resistor R ₁, pulse width modulation (PWM) maker 734 and error amplifier 732.In operation, use step-down controller from higher DC input voltage (V _in) the lower output voltage (V of generation _oUT).If the loss in switch (high side and downside FET) and inductor is all left in the basket, duty ratio or ON time account for the ratio of the total time of transducer and can be expressed as

D = \frac{V_{out}}{V_{in}} - - - (1)

As shown in Figure 26 B, duty ratio is determined by the output of error amplifier (Verr) and PWM ramp voltage (Vosc).In this and other embodiment, Vosc signal can comprise sine, triangle, sawtooth or any other suitable signal.Described ON time starts from the trailing edge of PWM ramp voltage, when ramp voltage equals the output voltage of error amplifier, stops.The output of described error amplifier (Verr) is set to again make output voltage (V _oUT) feedback fraction equal internal reference voltage (Vref).This closed loop feedback system makes output voltage control in required level.Normally, the resistive divider network shown in Figure 26 B (R1 and R2) is used to a part of output voltage to feed back to the end of oppisite phase of error amplifier.This voltage and Vref are compared, and during steady-state adjustment, the output of error amplifier will can not equal the required voltage of Vref lower than maintenance feedback voltage.Therefore, output voltage can be expressed as:

V_{out} = Vref (1 + \frac{R 1}{R 2}) - - - (2)

Can find out from equation (2), by changing reference voltage (Vref), can change output voltage (V _oUT).

In order to provide very fast output voltage to change, will the method for a kind of novelty provided by the present invention be described below in DC-DC transducer.Figure 27 shows the high level block diagram of the synchronous DC-DC step-down controller that comprises the quick output voltage transfer circuit of example.Described circuit (being denoted as generally 740) comprises input voltage source Vin742, switch 744,746, switch driver 759, output inductor L ₀748, output capacitor C ₀749, fine-adjusting unit 750, vernier control piece 754, resistor R ₁, R ₂, error amplifier 756 and PWM maker 758.Described fine-adjusting unit comprises fine setting buffer 752, capacitor Ctrim and switch S 1, S2.

In operation, under equilibrium mode, switch S 1 is connected and switch S 2 is turn-offed.Capacitor Ctrim is charged to Vtrim by fine setting buffer.Under this pattern, transducer is worked as the DC-DC transducer in Figure 26 B and its output voltage values can be used equation (2) to calculate.Output capacitor (C ₀) be charged to output voltage (V _oUT).Once vernier control order is applied to, raise order (being that output voltage increases), switch S 1 is turn-offed and switch S 2 connections, thereby described trimmer capacitor (Ctrim) is connected in series to output capacitor (C ₀).Voltage on these two capacitors is defined as: V _oUT+ Vtrim, like this output voltage (V _oUT) very rapidly increase (being almost moment) to the new value being provided by following formula:

V _{out_trim_up}＝V _out+Vtrim (3)

For the feedback loop of DC-DC transducer is remained on to limit, reference voltage (Vref) increases the incremental voltage being provided by following formula

ΔVref = Vtrim (\frac{R 2}{R 1 + R 2}) - - - (4)

From output voltage (V _oUT) to new voltage (V _{out_trim_up}) transformation occur very soon, this is because do not need output capacitor (C ₀) and trimmer capacitor (Ctrim) charging.

Applying downward control command (being that output voltage declines), before, the stable state of DC-DC transducer should be as follows.When described trimmer capacitor (Ctrim) is connected in series to output capacitor (C ₀) and by fine setting buffer while being charged to Vtrim voltage, switch S 1 be turn-off and switch S 2 is connected.Under this pattern, transducer is worked as the traditional DC-DC transducer in Figure 25, and its output voltage values can be used equation (2) to calculate.After applying and lowering control command, switch S 1 is connected and switch S 2 is turn-offed, thus by trimmer capacitor (Ctrim) from output capacitor (C ₀) disconnect.Output capacitor (C ₀) on voltage equal V _oUT-Vtrim, thereby output voltage (V _oUT) decline rapidly (being almost moment) for as undefined new value:

V _{out_trim_down}＝V _out-V _trim (5)

For the feedback loop of DC-DC transducer is remained on to limit, the incremental voltage that reference voltage must decline and be provided by following formula

ΔVref = Vtrim (\frac{R 2}{R 1 + R 2}) - - - (6)

From output voltage (V _oUT) to new voltage (V _{out_trim_down}) transformation occur very soon, this is because do not need output capacitor (C ₀) charging.

The converter circuit that utilizes synchronous DC-DC buck topology to come emulation to propose by following parameter: C ₀=Ctrim=22 μ F; L ₀=6.8 μ H; Fsw=1.15MHz; V _oUT=1.2V and the Vtrim up=1.2V for raising; V _oUT=2.4V and the Vtrim down=1.4V for lowering; Iload=500mA; V _in=3V.Simulation result is presented in Figure 28,29 and 30.Figure 28 shows the analog electrical output corrugating for synchronous DC-DC step-down controller.Figure 29 shows the rise output waveform of amplification, and Figure 30 shows the downward waveform of amplification.

It should be noted that simulation result shows to exist the very voltage transition of fast (being less than 0.1 μ Sec) between the rising of output voltage and decrement phase.The use of these results and the conventional DC-DC step-down controller theoretical rising and falling time that formula calculates is below compared:

trise / tfall = \sqrt{\frac{2 LC}{Dm (1 - Dm) (\frac{1}{| ΔD |} + 0.5)}} - - - (7)

Wherein Dm=(D1+D2)/2 and | Δ D|=D2-D1.D1 is initial steady state duty ratio, and D2 is final stable state duty ratio.

Use the identical parameters for above-mentioned simulation result, the D1=0.4 for raising wherein, D2=0.8 and the D1=0.8 for lowering, D2=0.333, we obtain result of calculation below:

trise＝20.4μSec

tfall＝21.5μSec

Figure 31 shows and utilizes the efficient envelope tracking of example of the DC-DC transducer with quick output voltage transformation mentioned above and the high level block diagram of system.Described system (being denoted as generally 780) comprises envelope detector 782, analog to digital converter (ADC) 784, has DC-DC transducer 786, programmable delay 788 and RF power amplifier (buffer) 789 that quick output voltage mentioned above changes.DC-DC converter output voltage it should be noted that power buffer is optional, because can be directly connected to the supply voltage of PA.

In operation, the RF envelope signal of envelope detector 782 (envelope input) output is applied simultaneously A/D converter and PA power buffer (by postponing 788).Described A/D converter work, so that analog RF envelope signal is quantified as to digital signal, has the DC-DC transducer that quick output voltage changes described in then described digital signal is applied to as digital trimming control bus.In one embodiment, an attribute of vernier control bus is to only have a position for high (being logical one) a moment, and other positions are low value (being logical zero).The content of digital trimming control bus is for changing output voltage (the DC-DC V of described DC-DC transducer _oUT).This output voltage is followed the tracks of RF envelope signal and is provided variable supply voltage to PA power amplifier (buffer).Described DC-DC V _oUTchange with RF envelope signal one, greatly increased PA power buffer efficiency and entire system efficiency.Described programmable delay is for compensating the delay between envelope detector and RF signal path.

In an alternative, another subsystem or can provide with envelope signal the phase information of digital form such as the element of baseband subsystems.In this case, the dispensable and digital envelope of described A/D converter module can be used by vernier control circuit and without A/D converter, thereby has reduced element and cost.

Described DC-DC transducer comprises as shown in Figure 27 and at DC-DC transducer mentioned above.In order to be configured for DC-DC transducer RF envelope-tracking system of the present invention, that have quick output voltage transformation, described transducer is implemented as the DC-DC transducer with many discrete output voltages.In order to realize this goal, increase n fine-adjusting unit, wherein n is the figure place of vernier control command line.In addition, vernier control module generates n Vtrim voltage (wherein n is the figure place of vernier control command line) and variable Vref voltage.

Figure 32 shows the block diagram of the example DC-DC transducer that comprises a plurality of fine-adjusting units of the present invention.Described transducer (being denoted as generally 790) comprises voltage source V _in, switch 792,794, output inductor L ₀, output capacitor C ₀, switch driver 793, trimming circuit 796, resistor R1, R2, error amplifier 806 and PWM maker 808.Described trimming circuit 796 comprises a plurality of fine-adjusting units 798, switch S 1, vernier control module 802 and NOR gate 804.Each fine-adjusting unit 798 comprises fine setting buffer 800, trimmer capacitor Ctrim and switch S 2.

When all vernier control bus signals have " 0 " value, the output of door 804 is all turn-offed all S2 switches in switch S 1 connection and n fine-adjusting unit.Ctrim capacitor in each fine-adjusting unit is charged to suitable Vtrim by its fine setting buffer separately.Under this pattern, described transducer is worked and can be used following formula (8) to calculate its output voltage values as traditional DC-DC transducer.Output capacitor (C ₀) be charged to initial output voltage (V _{out_init}).

V_{out_init} = Vref (1 + \frac{R 1}{R 2}) - - - (8)

For example, if when " 0 " of vernier control bus position becomes high level (" 1 " value), switch S 1 is turn-offed and switch S 2 connections, thereby the trimmer capacitor of fine-adjusting unit ' 0 ' (Ctrim) is connected serially to output capacitor (C ₀).Voltage on these two capacitors is defined as V _{out_init}+ Vtrim<0>, makes output voltage (V _out) very rapidly (being almost moment) increase to new value:

V _{out_trim}<0>＝V _{out_init}+Vtrim<0> (9)

For the feedback loop of DC-DC transducer is remained on to limit, reference voltage (Vref) increases use following formula and definite incremental voltage:

ΔVref = Vtrim < 1 > (\frac{R 2}{R 1 + R 2}) - - - (10)

From output voltage (V _{out_init}) to new voltage, (be V _{out_trim}during <l>) transformation occur very soon, this is because without the output capacitor (C in fine-adjusting unit ' 1 ' ₀) and trimmer capacitor (Ctrim) charging.

Can find out, by changing the numerical value of described vernier control bus, can change the output voltage of described DC-DC transducer, as follows:

V_{out} = V_{out_init} + Σ_{i = 0}^{n} a_{i} {Vreim}_{i} - - - (11)

A wherein _inumerical value for the i position of n position vernier control bus.

The advantage that it should be noted in the discussion above that envelope-tracking method and system of the present invention is: described DC-DC transducer can be used the low switching frequency of transducer to follow the tracks of the input envelope signal with relative high bandwidth, has therefore kept its high efficiency.

Should also be noted that and have the perfect linear PA that enough power supplys suppress, at its supply voltage, between tour, its linearity is influenced by minimally.Therefore, in most of the cases, do not use necessity of smoothing circuit.

Yet in reality, due to the fast transition of the supply voltage of PA, the linearity of described PA is affected, and particularly requires in the situation of low EVM (being high linearity).Therefore, preferably in circuit, use smoothing circuit module, for example power buffer.If we consider non-linear PA (such as in envelope elimination and recovery or the system based on the utmost point (polar) transmitter), wherein all amplitude informations are on PA power supply, and this power buffer is necessary.This " power buffer " can comprise the buffer that gain equals 1, and wherein its input is that envelope signal and its power supply are stair-stepping, the rough output from described DC-DC transducer.Output voltage after it is level and smooth is used to the power supply of PA.

By the following parameter in DC-DC buck converter topology, carry out emulation tracking circuit of the present invention: Quick-type A/D converter; Vernier control bus=7; C ₀=Ctrim<0:6>=22 μ F; L ₀=6.8 μ H; FSW=1.15MHz; V _{out_init}=0.8V, V _in=3V; Vtrim<0>=150mV; Vtrim<1>=300mV; Vtrim<2>=450mV; Vtrim<3>=600mV; Vtrim<4>=750mV; Vtrim<5>=900mV; Vtrim<6>=1050mV; The input of RF envelope comprises that frequency is the sinusoidal waveform of 10MHz.

Figure 33 shows the figure for the output voltage of the DC-DC change-over circuit of RF input, and wherein track 810 represents PA power buffer supply voltage, and track 812 represents PA power buffer output voltage.Figure 34 illustrates in greater detail the figure for the output voltage of the DC-DC change-over circuit of RF input, and wherein track 814 represents that PA power buffer supply voltage and track 816 represent the output voltage of PA power buffer.Figure 33 and 34 analogous diagram demonstrate the extraordinary tracking of DC-DC converter output voltage to RF envelope signal.

Figure 35 shows the schematic diagram of the first example TX/RX switch.Described switching circuit (being denoted as generally 480) comprises and is coupled to the TX input port of resistor R482, the inductor L484 that is coupled to RX output port, antenna port, capacitor C486, transistor Q488, low pass filter 490 and control logic circuit 498.Each low pass filter comprises resistor 492,496 and is coupled to the capacitor 494 on ground, and they connect with T-shape configuration.

In operation, by transistor Q is turn-offed, described TX/RX switch is placed under receiving mode.Under this pattern, signal path is to pass through inductor L to LNA circuit from antenna.In one embodiment, described inductor can be included as the inductance of 1.4nH.In addition, inductor may be implemented as the closing line that is connected to the suitable thickness of having of dummy pad (for example, 0.7mil) and length.

For TX/RX switch is placed under sending mode, make transistor Q conducting.Under this pattern, capacitor C and inductor L are combined into antiresonant circuit, thereby the output of transmitter is presented to high impedance, show the low insertion loss that is less than 0.5dB simultaneously.Power from transmitter is transferred to antenna by resistor R.

In one embodiment, switch utilizes standard CMOS technology to realize.In another embodiment, use PIN diode to realize switch with together with suitable peripheral cell for setovering with matching network.In an alternative, use the switch based on GaAs (GaAs) to realize RF switch.Switch based on GaAs provides the good linearity and isolation, and low on-resistance and shutoff electric capacity.Yet the shortcoming of GaAs comprises: (1), due to their N-raceway groove depletion-mode configuration, the grid voltage of negate to turn-off; (2) drive GaAs switch conventionally to need extra interface element; And (3) are difficult to integrated other functions such as logic control and memory on same chip.

In one embodiment, RF switch is realized with CMOS completely and is presented high power, low current and high isolation, simultaneously can andlogic control circuit and other functions based on digital circuit integrated.Such RF switch can be included into wireless device, and as mobile phone, cordless telephone etc., it will describe in more detail hereinafter.

The wireless device of consideration such as comprising the cordless telephone of base and one or more hand-held stations.Described hand-held station generally include there is nearest manufacturer's trend single antenna to realize antenna diversity in hand-held station.Due to the relatively little physical size of hand-held station, conventional space diversity is unpractiaca.Therefore, cordless phone manufacturers realizes polarization diversity in hand-held station, and one of them antenna is perpendicular polarization, and second antenna is horizontal polarization.On the statistics of about 10dB of the diversity antenna in pedestal is improved, this can be by the highest improvement of link performance 6dB.In hand-held station (HS), antenna diversity in the situation that, integrated CMOS DPDT switch of the present invention has extra advantage, comprising: require less PCB area, this is vital in HS design; Be easy to integrated; And low BOM.Base station can comprise one or two antenna, and they are placed with space angle relative to each other.In each time point implementation space diversity, for example, direct wave and reflected wave are set up the antenna of constructive interference rather than destructive interference.

Logic control circuit 498 is for generating the bias voltage of drain electrode, source electrode and the gate terminal of transistor Q.Offset signal is applied to drain electrode, source electrode and the grid of transistor Q by low-pass filter network 490.The function of LPF circuit 490 is that the RF suppressing from drain electrode, source electrode and grid to logic control circuit 498 reveals.It should be noted that as known in the art, can use other RC mode filter networks and not depart from scope of the present invention.It should be noted that the needs that use RC FL-network to avoid RF choke, and need RF choke (choke) when switch is realized in cmos circuit.Alternatively, can use RF choke or be integrated in chip in chip exterior.

In one embodiment, in order to make switch for example, at relatively high TX power level (>25dBm) and high VSWR, by dark N trap CMOS technique, build N channel fet 488.

In one embodiment, in order to make transistor Q conducting, relatively high voltage (for example 3.6V) is applied to grid, and drain electrode and source terminal are connected to ground.Therefore, V _gStransistor forward bias for 3.6V.For transistor Q is turn-offed, high voltage (for example 3.6V) is applied to drain electrode and source electrode, and grid is connected to ground.Therefore, V _gStransistor reverse bias for-3.6V.It should be noted that, reverse bias transistor so that its turn-off, rather than by grid, drain electrode and source electrode be connected to (or only control gate extreme and keep drain electrode and source-biased constant) will make RF switch realize remarkable higher isolation (being approximately 17 decibels).

Low-pass filter network 490 on described source electrode, drain and gate end also can connect for providing end, thereby makes antenna have constant impedance with respect to ground.The main purpose of LPF is the radio-frequency leakage suppressing from drain electrode, grid and source electrode to logic control circuit, thereby prevents the RF loss of signal in logic control circuit.This realizes by deploy switch circuit, thereby the impedance of nmos pass transistor is only for example, by the physical parameter of nmos pass transistor (R itself _dS-ON, C _dS-OFF, C _g, C _d, C _s) determine that also andlogic control circuit is irrelevant.

Should be appreciated that described logic control circuit is exemplary, can use with other elements and make transistor Q work, thus according to specific application with correct sequential and synchronous turn-on and turn-off.Described transistor Q and all related elements can be placed on chip, thereby reduce costs.

It is to be further understood that for the RC network of low pass filter and other element being associated with transistor Q be an example, can use the circuit of other execution similar functions, this is known in electronic applications.

Described logic control circuit is controlled grid, drain electrode and the source electrode of transistor Q.Switch compared to existing technology, the configuration of CMOS technology and use provide the low-power consumption with microammeter, and high-isolation and flexibility.

It should be noted that disclosed RF switch also can be used in the environment that one or more antennas can use, for example, at tool, be with or without antenna diversity and tool is with or without in the hand-held station of MIMO function.Described RF switch is not limited to the equipment for any type, and can be used in any environment that requires a plurality of switches such as wireless local network connecting point (WLAN AP), cell phone, cordless telephone, communication system, radar system etc.

In an alternative, described RF switch configuration can be expanded to comprise that extra transistor and control circuit for switching between extra port, for example, and extra antenna, TX and RX port.Can use switch matrix, N * Metzler matrix element for example, wherein each element is implemented as single nmos pass transistor, L series parallel combination or T or PI combination.These combinations can be implemented as complementary switch arbitrarily, comprise NMOS and PMOS.Should be appreciated that and can design various modifications and variations.For example, can use different peripheral cells and control circuit.

As described above, SPDT switch comprises three outside terminals (being pin or port): antenna, TX and RX.In one embodiment, for each terminal (pin), all have the bonding line of one or more parallel connections and/or series connection, it is connected to the inside SPDT end (being bonding welding pad) on tube core by external terminal.In one embodiment, the diameter measurement of bonding line is nominal 0.7mil and is made by copper or gold.This bonding line is not only for being connected to the internal circuit on semiconductor element the external terminal of equipment packages, also for the electric capacity of tuning or offseting transistor.One or more bonding lines of each pin show the relatively high Q factor, this contribute to connect compared with low insertion loss.The quantity of the parallel bonding line of specific die site and use is suitable for tuning nmos switch input capacitance, thereby has simplified outside matching network, and realizes lower insertion loss for antenna.This will describe in more detail hereinafter.

Specifically, the one or more bonding lines that outside TX pin are coupled to semiconductor element can operate the capacitance of drain with tuning nmos pass transistor Q.The one or more bonding lines that exterior antenna pin are coupled to semiconductor element can operate the source capacitance with tuning nmos pass transistor Q.One or more bonding lines that outside RX pin is coupled to semiconductor element can operate the capacitance of drain of tuning nmos pass transistor Q.Described bonding line and the shunt capacitor based on exterior PC B be combined to form the matching network arranging between TX, RX and antenna and switching transistor Q.

At each node, circuit is seen twice capacitance of drain or twice source capacitance.For example, due to the relatively large area (approximately 1 mm wide) of nmos device, so this electric capacity is greatly about 0.5 to 1.5pF.The electric capacity of seeing in order to be tuned at this input port, the inductance being shown by (one or more parallel connections and/or series connection) bonding line and the combination of PCB copper cash are suitable for producing resonance and form tuning circuit in required frequency range.Outside sheet on PCB, parallel connection outside capacitor is for combining with the inductance of bonding line, TX, RX and antenna port are presented to the impedance of the 50Ohm of a coupling.It should be noted that it is 0.7 for example, a part to the encapsulation of 1mil (square, flat, without lead-in wire or QFN) that bonding line normally has diameter, and by gold, copper or aluminum construction.

Figure 36 shows the schematic diagram of the second example TX/RX switch.Described switch comprises integrated TX and RX Ba Lun and the common single-ended antenna port of TX/RX.High pass filter can be realized relative high TX/RX isolation and low chip area with the combination of shunt nmos switch Q1.Described switch (being denoted as generally 820) comprises for the difference input from power amplifier is coupled to transmitting portion and the receiving unit for the signal coupling receiving is exported to the difference of low noise amplifier (LNA) circuit of antenna on antenna.Described transmitting portion comprises capacitor 851,853,873,878,892,894, inductor 880,882,874,876, the TX Ba Lun 828 that comprises Transformer Winding 868,870,872, transistor 884,886,888,890 and resistor 891,893,896,898.Described receiving unit comprises capacitor C1,836,838,842,848,854,856,850,852,, inductor 862,864,844,846, the RX Ba Lun 826 that comprises Transformer Winding 830,832,834, transistor Q1,866,860,840,858 and resistor 822,824,823.

The operation of described switch comprises suitable control signal is applied to RX control inputs and TX control inputs.For TX/RX switch is placed under receiving mode, RX control is configured to turn-off Q1 and TX control is configured to turn-off transistor 886,888.Turn-offing Q1 will allow the reception signal from antenna to arrive difference transistor to 866,860 by RX Ba Lun 826.The differential signal generating is output to LNA circuit (for example 134 in Fig. 2).

For TX/RX switch is placed under sending mode, RX controls and is configured to make Q1 conducting and TX control to be configured to make transistor 886,888 conductings.Make Q1 conducting that prevention transmitted signal is entered to receiving circuit path.Differential signal input from power amplifier input will be imported into transistor 886,888, be applied to subsequently TX Ba Lun 828, and the output of TX Ba Lun 828 is imported into antenna port.

Figure 37 shows the schematic diagram of example antenna RF switch.Described duplexer (being denoted as generally 900) comprises for antenna port being coupled to antenna 1902 and antenna 2948 to realize two antenna ports of antenna diversity.In single antenna application, one of nmos switch is disabled, thereby realizes lower insertion loss.Described switch comprises capacitor 904,906,908,924,926,944,946,940,942,949, the matching network 922 that comprises capacitor 923,925 and transformer 927, low pass filter 912,918,932,936, inductor 910,946, transistor 914,931, control logic module 920,938 and resistor 916,928,930,934.

In operation, control logic block configuration transistor switch 914,931 is to be coupled to antenna port at any one time antenna 1 or antenna 2.For antenna 1 is coupled to antenna port, control logic module 920 makes transistor 914 conductings by antenna l control signal, and control logic module 938 turn-offs transistor 931 by antenna 2 control signals.For antenna 2 is coupled to antenna port, control logic module 920 turn-offs transistor 914 by antenna l control signal, and control logic module 938 makes transistor 931 conductings by antenna 2 control signals.The class of operation of low pass filter 912,918,932,936 and control logic module 920,932 is similar to low pass filter 490 and the control logic module 494 of the TX/RX switch in Figure 35.

Figure 38 shows the curve chart of the power added efficiency (PAE) that depends on power output.Track 520 represents to be operated in the PAE-power output that conventional power amplifier is a little kept out of the way in various thick and thin work.Track 522 represents the PAE-power output of FEM circuit of the present invention and power amplifier, and it,, by adopting high/low sub-amplifier technology in conjunction with synchronous DC-DC transducer and the envelope-tracking system based on fine-adjusting unit, effectively presents a plurality of keeping out of the way a little.

Figure 39 shows the curve chart of the power output that depends on input power.Track 524 represents the power output-input power of a plurality of DC2DC working region, according to Mean Input Power, through envelope-tracking system by mentioned earlier, selects thick, thin working point.

Figure 40 shows the AM2AM of power amplifier circuit and the curve chart of AM2PM response.

Figure 42 shows the curve chart that power amplifier is kept out of the way working region RF signal before and afterwards.Track 540 represents the example RF signal of the input of power amplifier of the present invention.The RF signal that track 542 represents after power amplifier.Track 544 represents the dynamic buffer region adopting in the exemplary embodiment.

Figure 43 shows the curve chart for the frequency spectrum of the power amplifier of QAM64.Dashed trace represents the transmitted signal before power amplifier, and solid line track represents the signal receiving.Figure 44 shows the curve chart of dynamically keeping out of the way time domain RF ofdm signal before and afterwards for QAM64.Fine line represents the signal before power amplifier, and heavy line represents dynamically to keep out of the way power amplifier signal afterwards.What thick two-wire represented first keeps out of the way threshold value TH1, and thin two-wire represents that second keeps out of the way threshold value TH2.Figure 45 shows the figure for the reception of QAM64 and transmission planisphere.Choice refreshments represents the data of the transmission before power amplifier, and thick point represents the data that receive.

Figure 46 shows the curve chart for the frequency spectrum of the power amplifier of QAM256.Dashed trace represents the transmitted signal before power amplifier, and solid line track represents the signal receiving.Figure 47 shows the curve chart of dynamically keeping out of the way time domain RF ofdm signal before and afterwards for QAM256.Fine line represents the signal before power amplifier, and heavy line represents dynamically to keep out of the way power amplifier signal afterwards.Thick two-wire represents that first keeps out of the way threshold value TH1, and thin two-wire represents that second keeps out of the way threshold value TH2.Figure 48 shows the figure for the reception of QAM256 and transmission planisphere.Choice refreshments represents the data of the transmission before power amplifier, and thick point represents the data that receive.

Figure 49 shows the high level block diagram of the exemplary wireless device that comprises FEM circuit of the present invention.Flat board/mobile device is preferably the bi-directional communication device with voice and/or its communication ability.In addition, described equipment has the ability communicating via internet and other computer systems alternatively.It should be noted that, this equipment can comprise any suitable wired or wireless equipment, as multimedia player, mobile communication equipment, cell phone, cordless telephone, smart mobile phone, PDA, PNA, bluetooth equipment, dull and stereotyped computing equipment, such as iPad, Galaxy etc.Only for purposes of illustration, described equipment is shown as mobile device, as the phone based on honeycomb, cordless telephone, smart mobile phone or super mobile phone.The present invention it should be noted that this example is not intended to limit the scope of described mechanism, because can realize in communication equipment widely.Mobile device shown in further should be appreciated that be deliberately simplify so that some assembly to be only shown, and described mobile device can also comprise and exceeds shown other assemblies and subsystem.

Described mobile device (being denoted as generally 60) comprising: one or more processors 62, and it can comprise baseband processor, CPU, microprocessor, DSP etc.; Selectively there is analog-and digital-part.Described mobile device can comprise a plurality of wireless devices 102 (for example cell phone, cordless telephone etc.), have according to the present invention and the FEM circuit 103 of the power amplifier 105 of constructing and the one or more antennas 104 that are associated.Can comprise for other wireless standards of wireless link and any amount and the wireless device of wireless access technology (RAT).Example comprises, but be not limited to, DECT (DECT), code division multiple access (CDMA), personal communication service (PCS), global mobile communication (GSM)/GPRS/EDGE3G system, WCDMA, the WiMAX of WiMAX wireless connections is provided when within the scope of WiMAX wireless network, the bluetooth that provides when within the scope of blue tooth radio network blue teeth wireless to connect, the 802.11WLAN of wireless connections is provided when at focus or within the scope of dedicated network, WLAN based on infrastructure or net (WLAN), near-field communication, UWB, the GPS receiver of the GPS radio signal that reception sends from one or more track gps satellites, make user can listen to FM broadcast and in untapped FM radio station, with low-power, send the audio frequency FM transceiver of (so that such as thering is playback on the automobile of FM receiver or home stereo systems or digital broadcast television etc.).

Described mobile device can also comprise inner volatile memory 64 (for example RAM), non-volatile storage 68 (for example ROM) and flash memory 66.The also executable application of storage of processor 62 of non-volatile storage 68, comprises associated data files, and described application is used associated data files to carry out its predetermined function with permission equipment 60.Some optional user interface facilities comprise: trace ball/finger wheel, and it can comprise presses finger wheel/trace ball, for navigation, choice menus, selects and confirm to move; Such as being arranged as QWERTY form so that the keypad/keyboard of input alphabet numerical data; Numeric keypad, for input dial numeral and other controls and input (keyboard also may comprise symbol, function and the command key such as dial/end key of phone, Menu key and ESC Escape); Earphone 88; Receiver 86 and/or loud speaker 84; Microphone and the audio codec or other multimedia coding-decoders that are associated; Warning user's vibrator; One or more video cameras and interlock circuit 110,112; Display (a plurality of) 122 and associated display controller 106 and touch screen controller 108.Serial port comprises micro USB port 76, relevant USB PHY74 and miniature SD port 78.Other interfaces connect may comprise SPI, SDIO, PCI, USD etc., for computer or other equipment that provides serial link to arrive user.SIM/RUIM card 80 is provided to user's SIM card or the interface of RUIM card, so as storage user data, such as address book entries, user ID etc.

The battery 72 that is coupled to electric power management circuit 70 provides compact power.By USB power supply or the AC/DC adapter that is connected to electric power management circuit, provide external power source, described electric power management circuit can operate to manage the charging and discharging of battery.Except battery and AC/DC external power source, extra optional power supply all has self power limitations, comprising: intercommunication telephone, DC/DC power supply and any bus-powered power supply (as the USB device under bus-powered pattern).

The operating system software being carried out by processor 62 is preferably stored in non-volatile storage (being ROM68) or flash memory 66, but also can be stored in the memory device of other types.In addition, systems soft ware, specific device applications or part wherein can be loaded into volatile memory 64, such as random access memory (RAM) temporarily.The signal of communication being received by mobile device also can be stored in RAM.

Processor 62, except its operation system function, can executive software application on equipment 60.One group of predetermined application controlling basic device operations (as data and voice communication) can be installed during manufacture.Additional application (or application program) can be downloaded from the Internet, and is arranged in memory to carry out on processor.Alternatively, software can be by any other suitable agreement, as downloads such as SDIO, USB, the webservers.

Other assemblies of described mobile device comprise accelerometer 114, the magnetometer 116 for detection of magnetic field of the earth, FM radio 118 and antenna 120, bluetooth radio 98 and antenna 100, the Wi-Fi radio 94 based on 802.11 (for example comprising ' a ', ' b ', ' g ', ' n ', ' ac ' standard) (comprising FEM circuit 95 and one or more antenna 96 with the power amplifier 97 building according to the present invention), GPS90 and the antenna 92 for detection of device action and direction.

According to the present invention, mobile device 60 is suitable for electric catalog system to be embodied as the combination of hardware, software or hardware and software.In one embodiment, be embodied as software task, operation with realize the program code of electric catalog system be performed as on processor 62 operation one or more tasks and: (1) is stored in one or more memories 64,66,68; Or (2) are stored in the local storage within processor 62 is own.

Term used herein is just in order to describe the object of specific embodiment, rather than plan restriction the present invention.As used herein, singulative " ", " one " and " being somebody's turn to do " are also intended to comprise plural form, unless context separately has clear indication.It is also to be understood that, with term in this manual, " comprise " and/or " comprising " specified the existence of feature, integer, step, operation, element and/or the parts of stating, but do not get rid of existence or the interpolation of one or more further features, integer, step, operation, element, parts and/or their group.

The device that counter structure in following claim, material, operation and all functions limit or step be equal to replacement, be intended to comprise any for other unit with specifically noting in the claims combined carry out structure, material or the operation of this function.Its object of the given description of this invention is signal and describes, and is not exhaustive, is not also the present invention to be limited to explained form.Because many modifications and variations are easily expected to those skilled in the art, so the present invention is not intended to be confined to a limited number of embodiment disclosed herein.Correspondingly, should be appreciated that, all suitable modification things, modification thing and equivalent all can be attributed to or fall in the spirit and scope of the present invention.To the selection of embodiment and explanation, be in order to explain best principle of the present invention and practical application, person of an ordinary skill in the technical field can be understood, the present invention can have the various execution modes with various changes that are applicable to desired special-purpose.

Claims

1. a sending/receiving switch, comprising:

TX port, it is for being coupled to RF transmitted signal;

RX port, it receives signal for being coupled to RF;

Antenna port, it is for being coupled to antenna;

Inductor, itself and described antenna port and described RX port series coupled; And

The tandem compound of capacitor and field-effect transistor (FET) switch, it is across described inductor parallel coupled, wherein said FET switch has source electrode, drain and gate terminal, and described gate terminal can operate to receive for controlling the control signal of described FET switch.

2. sending/receiving switch according to claim 1, wherein said switch presents conducting under sending mode, thereby sets up the high impedance antiresonant circuit of described inductor and described capacitor.

3. sending/receiving switch according to claim 1, wherein when described switch presents conducting under sending mode, the operation of the high impedance antiresonant circuit by described inductor and described capacitor, stops described RF transmitted signal from described RX port.

4. sending/receiving switch according to claim 1, wherein said switch presents not conducting under receiving mode, thereby by described inductor be coupled described antenna port and described receiving port.

5. sending/receiving switch according to claim 1, is also included in the resistor of connecting between described transmit port and described antenna port.

6. sending/receiving switch according to claim 1, wherein said inductor comprises lumped inductance device.

7. sending/receiving switch according to claim 1, wherein said inductor comprises one or more bonding lines.

8. sending/receiving switch according to claim 1, wherein said FET switch is manufactured with the semiconductor technology being selected from following group, and described group comprises: complementary metal oxide semiconductors (CMOS) (CMOS), GaAs (GaAs), SiGe (SiGe) and gallium nitride (GaN).

9. sending/receiving switch according to claim 1, wherein said sending/receiving switch is suitable for the signal that sending and receiving meets the wireless standard that is selected from following group, and described group comprises: 802.11WLAN, LTE, WiMAX, HDTV, 3G honeycomb, 4G honeycomb and DECT.

10. a sending/receiving switch, comprising:

TX port, it is for being coupled to RF transmitted signal;

RX port, it receives signal for being coupled to RF;

Antenna port, it is for being coupled to antenna;

The first transformer Balun, it can operate so that described RF is received to signal and be coupled to described RX port from described antenna port;

Capacitor, it is connected with described the first transformer Balun;

Field-effect transistor (FET) switch, it is across the armature winding parallel coupled of described the first transformer Balun; And

The second transformer Balun, it can operate that described RF transmitted signal is coupled to described antenna port from described TX port.

11. sending/receiving switches according to claim 10, wherein said FET switch presents conducting under sending mode, thereby makes to be coupled to the input end grounding of the low noise amplifier (LNA) of described RX port.

12. sending/receiving switches according to claim 10, wherein said FET switch presents conducting under sending mode, thereby described RF transmitted signal is sent to described antenna port from described TX port, stops described RF transmitted signal to enter described RX port simultaneously.

13. sending/receiving switches according to claim 10, wherein said FET switch presents conducting under sending mode, and the resultant impedance of described capacitor, the described FET switch in conducting state and the reflected umpedance that is coupled to the low noise amplifier (LNA) of described RX port present relatively high impedance to described RF transmitted signal thus.

14. sending/receiving switches according to claim 10, are also included in the matching network being coupled between described TX port and power amplifier circuit.

15. sending/receiving switches according to claim 10, are also included in the matching network being coupled between described RX port and low noise amplifier.

16. sending/receiving switches according to claim 10, wherein said FET switch presents not conducting under receiving mode, thereby by described the first transformer Balun be coupled described antenna port and described receiving port.

17. sending/receiving switches according to claim 10, also comprise tuned oscillator circuit, and it is coupled to described the first transformer Balun to carry out impedance matching with the low noise amplifier (LNA) that is coupled to described RX port.

18. sending/receiving switches according to claim 10, wherein said sending/receiving switch is manufactured with the semiconductor technology being selected from following group, and described group comprises: complementary metal oxide semiconductors (CMOS) (CMOS), GaAs (GaAs), SiGe (SiGe) and gallium nitride (GaN).

19. sending/receiving switches according to claim 10, wherein said sending/receiving switch is suitable for the signal that sending and receiving meets the wireless standard that is selected from following group, and described group comprises: 802.11WLAN, LTE, WiMAX, HDTV, 3G honeycomb, 4G honeycomb and DECT.