CN104166286A - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN104166286A CN104166286A CN201410366241.8A CN201410366241A CN104166286A CN 104166286 A CN104166286 A CN 104166286A CN 201410366241 A CN201410366241 A CN 201410366241A CN 104166286 A CN104166286 A CN 104166286A
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- array base
- base palte
- display panel
- receiving part
- store electricity
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Abstract
The invention discloses an array substrate and a display panel and relates to the technical field of display. The array substrate comprises grid lines and a pixel electrode. The array substrate is divided into multiple pixel units. The pixel electrode comprises first storage capacitor portions located outside the pixel units and first liquid crystal capacitor portions located in the pixel units. The orthographic projection of the first storage capacitor portions and the orthographic projection of the grid lines on a substrate body of the array substrate at least overlap partially. The display panel comprises the array substrate and a box-to-box substrate. The box-to-box substrate is provided with a common electrode. The common electrode comprises second storage capacitor portions and second liquid crystal capacitor portions located in the pixel units. The first liquid crystal capacitor portions and the second liquid crystal capacitor portions correspondingly form liquid crystal capacitors. The first storage capacitor portions and the second storage capacitor portions correspondingly form storage capacitors. The array substrate and the display panel can increase the aperture ratio of pixels and lower power consumption.
Description
Technical field
The present invention relates to display technique field, the display panel that relates in particular to a kind of array base palte and comprise this array base palte.
Background technology
For display panel, aperture opening ratio is a very important design parameter, represents the ratio of effective transmission region and entire area, and aperture opening ratio is larger, and the relative brightness of display panel is higher, thereby it is lower to reach the power consumption of display panel of same brightness.
In the middle of the display panel of traditional TN (Twisted Nematic) structure, when scanning grid line, thin film transistor (TFT) (TFT) is opened, thereby be memory capacitance charging, and memory capacitance is full of, at other constantly, memory capacitance electric discharge, keep the electric field of liquid crystal capacitance, thereby make the liquid crystal between liquid crystal capacitance maintain rotation or irrotational state.
For example, in Fig. 1, grid line 1 connects the grid of thin film transistor (TFT) 3, data line 2 connects the source electrode of thin film transistor (TFT) 3, pixel electrode 4 connects the drain electrode of thin film transistor (TFT) 3 by via hole, memory capacitance is formed between public electrode wire 5 and pixel electrode 4, and public electrode wire 5 is parallel to grid line 1 and is arranged on array base palte.In realizing process of the present invention, inventor finds at least to exist in prior art following problem: arranging of public electrode wire can take a part of transmitance, causes the aperture opening ratio of pixel can not maximize raising.
Summary of the invention
The object of the present invention is to provide a kind of array base palte and display panel, to improve pixel aperture ratio.
For solving the problems of the technologies described above, as first aspect of the present invention, a kind of array base palte is provided, described array base palte comprises grid line and pixel electrode, described array base palte is divided into a plurality of pixel cells, described pixel electrode comprises the first store electricity receiving part being positioned at outside described pixel cell and the first liquid crystal capacitance portion that is positioned at described pixel cell, and described the first store electricity receiving part and the orthogonal projection of described grid line on the underlay substrate of described array base palte are overlapping at least partly.
Preferably, described the first memory capacitance portion is positioned at described grid line top.
Preferably, between described grid line and described the first store electricity receiving part, be formed with the first insulation course, described the first insulation course contacts with described the first store electricity receiving part, and makes the height of the described underlay substrate of described the first store electricity receiving part distance be greater than described the first liquid crystal capacitance portion apart from the height of described underlay substrate.
As second aspect of the present invention, a kind of display panel is also provided, described display panel comprise array base palte and with this array base palte box is arranged to box substrate, described array base palte is above-mentioned array base palte provided by the present invention, described to being provided with public electrode on box substrate, described public electrode comprises the second store electricity receiving part being positioned at outside described pixel cell and is positioned at the second liquid crystal capacitance portion of described pixel cell, described the first liquid crystal capacitance portion and described the second liquid crystal capacitance portion corresponding formation liquid crystal capacitance, described the first store electricity receiving part and the corresponding formation of described the second store electricity receiving part memory capacitance.
Preferably, described the first memory capacitance portion is positioned at described grid line top.
Preferably, between described grid line and described the first store electricity receiving part, be formed with the first insulation course, described the second memory capacitance subordinate side is formed with the second insulation course, described array base palte and described box substrate is contacted with each other in position corresponding to described the second insulation course.
Preferably, described the first store electricity receiving part top is provided with oriented layer, and described the second insulation course below is provided with oriented layer.
Preferably, described the second insulation course is the chock insulator matter layer that is formed on described the second memory capacitance subordinate side.
Preferably, the material of described the first insulation course and/or described the second insulation course is resin.
Preferably, the orthogonal projection of the black matrix of described memory capacitance and described display panel on the underlay substrate of described array base palte is overlapping at least partly.
Array base palte of the present invention does not comprise public electrode wire, in the position corresponding to grid line, adopted that to using the subregion of pixel electrode and the subregion of public electrode be that the capacitance structure that forms of two-plate is as the memory capacitance of pixel, can improve pixel aperture ratio, improve display panel brightness, reduce power consumption, reduce the difficulty of wires design.
Accompanying drawing explanation
Accompanying drawing is to be used to provide a further understanding of the present invention, and forms a part for instructions, is used from explanation the present invention, but is not construed as limiting the invention with embodiment one below.
Fig. 1 is the floor map of array substrate pixel structure in prior art;
Fig. 2 is the diagrammatic cross-section according to the display panel of an embodiment of the present invention;
Fig. 3 is the floor map according to the array base palte of an embodiment of the present invention.
In the accompanying drawings, 1: grid line; 2: data line; 3: thin film transistor (TFT); 4,40: pixel electrode; 401: the first store electricity receiving parts; 402: the first liquid crystal capacitance portions; 5: public electrode wire; 50: public electrode; 501: the second store electricity receiving parts; 502: the second liquid crystal capacitance portions; 6: the first insulation courses; 7: the second insulation courses; 8: oriented layer; 9: liquid crystal; 10: black matrix; 11: chromatic filter layer; 12: passivation layer.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is elaborated.Should be understood that, embodiment described herein only, for description and interpretation the present invention, is not limited to the present invention.
" upper and lower " direction of mentioning in the embodiment of the present invention all refers to arrow institute target direction in Fig. 2, wherein, " U " expression " on " direction, " D " represents D score direction.
First the present invention provides a kind of array base palte, as shown in Figure 2.Described array base palte comprises grid line 1 and pixel electrode 40, described array base palte is divided into a plurality of pixel cells, pixel electrode 40 comprises that orthogonal projection and the orthogonal projection of grid line 1 on described underlay substrate on the underlay substrate of described array base palte of the first liquid crystal capacitance portion 402, the first store electricity receiving parts 401 of being positioned at the first store electricity receiving part 401 outside described pixel cell and being positioned at described pixel cell is overlapping at least partly.
Pixel cell refers to the unit that comprises basic protochrome and half-tone information of arranging by matrix in display frame.Conventionally on array base palte, comprise many grid lines and many data lines, many described grid lines are arranged in parallel, and many described data lines are also arranged in parallel, and described grid line and described data line intersect vertically, and described array base palte is divided into a plurality of pixel cells.Be arranged in described pixel cell and refer to and be positioned at the region that described display unit can printing opacity, be positioned at described pixel cell and refer to lighttight regions such as being positioned at grid line outward.
In Fig. 2, the first store electricity receiving part 401 is positioned at grid line 1 top, and the first store electricity receiving part 401 in pixel electrode 40 has covered a part for grid line 1, and " covering " here refers to perpendicular to blocking in the direction of array base palte.In the present invention, on array base palte, do not comprise public electrode wire, and described the first store electricity receiving part 401 can with accordingly the public electrode 50 on box substrate is formed to electric capacity above grid line 1, this electric capacity can be used as memory capacitance, make memory capacitance miniaturization, and owing to having saved public electrode wire, reached the object that improves pixel aperture ratio, increase light efficiency, reduces power consumption and reduction wires design difficulty.
Preferably, the first store electricity receiving part 401 be positioned at grid line 1 directly over, the memory capacitance now forming is minimum on the impact of pixel aperture ratio, can make the aperture opening ratio of pixel improve substantially.
In addition, in prior art, data line and public electrode wire are all produced on array base palte, cause the coupling between data line and public electrode wire serious, and under large panel size, the situations such as undercompensation, over-compensation, easily appear in compensation difficulty.Here " compensation " refers to for the overlap capacitance between data line and public electrode wire and compensates, to reduce the signal fluctuation of public electrode wire.
The present invention is owing to having cancelled the public electrode wire on array base palte, can also improve to a certain extent due to the formed color offset phenomenon of the coupling between data line and public electrode wire, make to comprise that the color of image that the display panel of described array base palte shows is truer.
In order to prevent the interference of the signal of grid line 1 to described memory capacitance, can between grid line 1 and the first store electricity receiving part 401, the first insulation course 6 be set.The first insulation course 6 contacts with the first store electricity receiving part 401, and makes the height of the described underlay substrate of the first store electricity receiving part 401 distance be greater than the first liquid crystal capacitance portion 402 apart from the height of described underlay substrate.The material of the first insulation course 6 can be resin, preferably, can be transparent resin.
Conventionally utilize formula C=ε S/d to calculate the electric capacity of electric capacity, wherein ε is the specific inductive capacity of medium between electric capacity two-plate, and S is relative area between two-plate, and d is the distance between two-plate.
In the present invention, between the first store electricity receiving part 401 and grid line 1, can produce stray capacitance.The two-plate of stray capacitance is respectively the first store electricity receiving part 401 part overlapping with grid line 1 projection on the underlay substrate of array base palte.By the first insulation course 6 is set, the first store electricity receiving part 401 is padded, can reduce stray capacitance, therefore can effectively completely cut off the interference to described memory capacitance of signal in grid line 1.In addition, the first insulation course 6 being set has also shortened the first store electricity receiving part 401 and to the distance between the public electrode 50 on box substrate, has promoted the ability of described memory capacitance stored charge.
The present invention also provides a kind of display panel, described display panel comprise array base palte and with this array base palte box is arranged to box substrate, described array base palte is above-mentioned array base palte provided by the present invention.
Fig. 2 is the diagrammatic cross-section according to the display panel of an embodiment of the present invention, and the first store electricity receiving part 401 in figure on array base palte is positioned at described grid line top.Described to being provided with public electrode 50 on box substrate, public electrode 50 comprises the second liquid crystal capacitance portion 502 that is positioned at the second store electricity receiving part 501 outside described pixel cell and is positioned at described pixel cell, the first liquid crystal capacitance portion 402 on described array base palte and the second liquid crystal capacitance portion 502 corresponding formation liquid crystal capacitance on box substrate, and the first store electricity receiving part 401 on described array base palte and the corresponding formation of the second store electricity receiving part 501 memory capacitance on box substrate.
Here to box substrate, can be the color membrane substrates that comprises black matrix 10 and chromatic filter layer 11.
When scanning grid line 1, the memory capacitance forming between the first store electricity receiving part 401 and the second store electricity receiving part 501 is recharged, and when the end of scan, described memory capacitance is discharged to liquid crystal capacitance, thereby continue to maintain the deflection state of liquid crystal 9, until next sweep signal arrives.
Compared with prior art, in display panel provided by the invention, used a kind of new dot structure, public electrode wire is removed from array base palte, above grid line 1, form the memory capacitance that does not take pixel aperture ratio, improved the aperture opening ratio of pixel, aperture opening ratio is larger, and the relative brightness of described display panel is higher, thereby described in while reaching same brightness, the power consumption of display panel is lower.
In the present invention, the second store electricity receiving part 501 belows are formed with the second insulation course 7, described array base palte the and described position in the second insulation course 7 correspondences contacts with each other to box substrate, and the material of the second insulation course 7 can be resin.
The second insulation course 7 can directly be used the chock insulator matter layer on box substrate, and without other making.Conventionally the chock insulator matter on box substrate is divided into main chock insulator matter and time chock insulator matter, main chock insulator matter is thick for supporting the box of display panel, fully contact, and the height of inferior chock insulator matter is less than main chock insulator matter, for cushioning external force with array base palte.The second insulation course 7 in the present invention can be used main chock insulator matter, is located between the first store electricity receiving part 401 and the second store electricity receiving part 501, has both played and has supported the thick effect of display panel box, also plays dielectric effect of serving as memory capacitance.
The effect that as mentioned above, can form the first insulation course 6, the first insulation courses 6 between the grid line 1 of described array base palte and the first store electricity receiving part 401 is in order to prevent that the signal of grid line 1 from disturbing described memory capacitance.Because the first insulation course 6 is padded by the first store electricity receiving part 401, shortened the first store electricity receiving part 401 and to the distance between the public electrode 50 on box substrate, promoted the ability of described memory capacitance stored charge.
Conventionally, before making pixel electrode 40, can first make one deck passivation layer 12, first insulation course 6 here can be with passivation layer 12 by forming with a composition technique, the first insulation course 6 is made as integral structure with passivation layer 12, can save one-time process step like this.
In Fig. 2 is color membrane substrates to box substrate, is provided with black matrix 10 and chromatic filter layer 11 on it.The orthogonal projection of the black matrix 10 of the first store electricity receiving part 401 and the formed memory capacitance of the second store electricity receiving part 501 and described display panel on the underlay substrate of described array base palte is overlapping at least partly.
That is to say, the main chock insulator matter using in the second insulation course 7 is the main chock insulator matter corresponding to the position of black matrix 10.In display panel pixel structure, the position of memory capacitance is corresponding to the position of black matrix 10 on display panel.
For the inceptive direction of liquid crystal 9 is set, conventionally at array base palte with on to box substrate, be also provided with oriented layer 8.In Fig. 2, pixel electrode 40 tops on described array base palte are provided with oriented layer 8, described public electrode 50 belows on box substrate are provided with to oriented layer 8.Conventionally oriented layer 8 is that whole layer applies formation, for the memory capacitance part in the present invention, the first store electricity receiving part 401 tops are provided with oriented layer, the second insulation course 7 (can be chock insulator matter layer here) below is provided with oriented layer, in so described memory capacitance, uses chock insulator matter and oriented layer jointly as dielectric.
Fig. 3 is the floor map of array substrate pixel structure in the present invention, as can be seen from the figure, pixel electrode 40 is overlapping with the projection section of grid line 1 on the underlay substrate of described array base palte, between the first store electricity receiving part 401 of pixel electrode 40 and grid line 1, is provided with the first insulation course 6.
Comparison diagram 1 can find out, in the present invention, the aperture opening ratio of pixel is improved.Make a concrete analysis of as follows:
Memory capacitance of the prior art shown in Fig. 1 is provided by public electrode wire 5 and pixel electrode 4, and formed memory capacitance is parallel with grid line 1, and described memory capacitance and grid line 1 be all positioned at the pixel display area on array base palte, has taken the aperture opening ratio of pixel.
And dot structure in the present invention shown in Fig. 3 has removed public electrode wire, utilization is arranged on the pixel electrode on array base palte and is arranged on the public electrode on box substrate has been formed to the memory capacitance that does not take pixel aperture ratio that is positioned at the outer grid line of pixel region top, replace original memory capacitance, make memory capacitance miniaturization, promoted the aperture opening ratio of pixel, reduce the power consumption of display panel, promoted the brightness of display panel.In addition, due on array base palte without making public electrode wire, reduced the difficulty of pair array substrate wires design.
Dielectric in described memory capacitance can utilize existing chock insulator matter and oriented layer to form, and without other making, saves manufacture craft.
In addition, the coupling in prior art between data line and public electrode wire is serious, and the present invention, owing to having cancelled the public electrode wire on array base palte, can also improve to a certain extent due to the formed color offset phenomenon of the coupling between data line and public electrode wire.
Be understandable that, above embodiment is only used to principle of the present invention is described and the illustrative embodiments that adopts, yet the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (10)
1. an array base palte, it is characterized in that, described array base palte comprises grid line and pixel electrode, described array base palte is divided into a plurality of pixel cells, described pixel electrode comprises the first store electricity receiving part being positioned at outside described pixel cell and the first liquid crystal capacitance portion that is positioned at described pixel cell, and described the first store electricity receiving part and the orthogonal projection of described grid line on the underlay substrate of described array base palte are overlapping at least partly.
2. array base palte according to claim 1, is characterized in that, described the first memory capacitance portion is positioned at described grid line top.
3. array base palte according to claim 1 and 2, it is characterized in that, between described grid line and described the first store electricity receiving part, be formed with the first insulation course, described the first insulation course contacts with described the first store electricity receiving part, and makes the height of the described underlay substrate of described the first store electricity receiving part distance be greater than described the first liquid crystal capacitance portion apart from the height of described underlay substrate.
4. a display panel, described display panel comprise array base palte and with this array base palte box is arranged to box substrate, it is characterized in that, described array base palte is array base palte claimed in claim 1, described to being provided with public electrode on box substrate, described public electrode comprises the second store electricity receiving part being positioned at outside described pixel cell and is positioned at the second liquid crystal capacitance portion of described pixel cell, described the first liquid crystal capacitance portion and described the second liquid crystal capacitance portion corresponding formation liquid crystal capacitance, described the first store electricity receiving part and the corresponding formation of described the second store electricity receiving part memory capacitance.
5. display panel according to claim 4, is characterized in that, described the first memory capacitance portion is positioned at described grid line top.
6. display panel according to claim 5, it is characterized in that, between described grid line and described the first store electricity receiving part, be formed with the first insulation course, described the second memory capacitance subordinate side is formed with the second insulation course, described array base palte and described box substrate is contacted with each other in position corresponding to described the second insulation course.
7. display panel according to claim 6, is characterized in that, described the first store electricity receiving part top is provided with oriented layer, and described the second insulation course below is provided with oriented layer.
8. according to the display panel described in claim 6 or 7, it is characterized in that, described the second insulation course is the chock insulator matter layer that is formed on described the second memory capacitance subordinate side.
9. according to the display panel described in claim 6 or 7, it is characterized in that, the material of described the first insulation course and/or described the second insulation course is resin.
10. according to the display panel described in any one in claim 4-7, it is characterized in that, the orthogonal projection of the black matrix of described memory capacitance and described display panel on the underlay substrate of described array base palte is overlapping at least partly.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410366241.8A CN104166286A (en) | 2014-07-29 | 2014-07-29 | Array substrate and display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410366241.8A CN104166286A (en) | 2014-07-29 | 2014-07-29 | Array substrate and display panel |
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| CN104166286A true CN104166286A (en) | 2014-11-26 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104517583A (en) * | 2015-01-15 | 2015-04-15 | 京东方科技集团股份有限公司 | Display panel, driving method thereof and display device |
| CN106094298A (en) * | 2015-04-30 | 2016-11-09 | 三星显示有限公司 | Liquid crystal display |
-
2014
- 2014-07-29 CN CN201410366241.8A patent/CN104166286A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104517583A (en) * | 2015-01-15 | 2015-04-15 | 京东方科技集团股份有限公司 | Display panel, driving method thereof and display device |
| CN106094298A (en) * | 2015-04-30 | 2016-11-09 | 三星显示有限公司 | Liquid crystal display |
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Application publication date: 20141126 |