CN110308600A - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN110308600A CN110308600A CN201910580876.0A CN201910580876A CN110308600A CN 110308600 A CN110308600 A CN 110308600A CN 201910580876 A CN201910580876 A CN 201910580876A CN 110308600 A CN110308600 A CN 110308600A
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- pixel
- film transistor
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- tft
- thin film
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Abstract
The embodiment of the invention discloses a kind of array substrate, display panel and display devices, the array substrate includes: scan line, data line and pixel group, pixel group is arranged in array, and each pixel group includes the first son and the second sub-pixel set gradually along line direction；Every group of scan line includes the first and second scan lines, and between same group of the first and second scan lines, data line is set between the first and second sub-pixels of same row pixel group same pixel group；Pixel group further includes the first and second thin film transistor (TFT)s；The input terminal of first and second thin film transistor (TFT)s of same pixel group is electrically connected with the data line for being located at the pixel group, and the output end of the first and second thin film transistor (TFT)s is electrically connected with the first and second sub-pixels respectively；In the plane for being parallel to underlay substrate, the direction of the input terminal direction output end of first film transistor and the input terminal direction direction of output end of the second thin film transistor (TFT) are identical.Image quality can be promoted as a result, improve properties of product.
Description
Technical field
The present invention relates to field of display technology, and in particular to a kind of array substrate, display panel and display device.
Background technique
In field of display technology, display panel and display device generally use thin film transistor (TFT) and are driven.With aobvious
Show the development of technology, to reduce cost, generallys use half source electrode (also referred to as bigrid, dual gate) driving method driving pixel
Array.Two grid driving method can be such that the number of data line halves relative to the number of the data line in conventional ADS driving mode,
To reduce source electrode drive circuit quantity, and then driving chip quantity is reduced, reduces cost.
But in the existing display panel using bigrid driving method, different tft placements is variant, leads
It causes in technical process, different film layers cause parasitic capacitance variant when having contraposition deviation, so as to cause product (including display panel
And display device) display performance it is poor, such as occur vertical line, flashing, ghost show bad phenomenon.
Summary of the invention
The embodiment of the invention provides a kind of array substrate, display panel and display devices, to promote image quality, are conducive to change
The display performance of kind display panel and display device.
In a first aspect, the embodiment of the invention provides a kind of array substrates, comprising:
Underlay substrate；
It is set to the multiple scanline groups, multiple data lines and multiple pixel groups of underlay substrate side, the multiple picture
Element group is arranged in array, and each pixel group includes the first sub-pixel and second sub-pixel set gradually along line direction；
Each scanline groups include the first scan line and the second scan line, and described in the same pixel group
One sub-pixel and second sub-pixel be located at the same scanline groups first scan line and the second scan line it
Between, the data line is set between first sub-pixel of pixel group described in same row and second sub-pixel；
The pixel group further includes first film transistor and the second thin film transistor (TFT)；Described the of the same pixel group
The input terminal of the input terminal of one thin film transistor (TFT) and second thin film transistor (TFT) be located at described the of the pixel group
Data line electrical connection among one sub-pixel and second sub-pixel, the output end of the first film transistor and institute
The electrical connection of the first sub-pixel is stated, the output end of second thin film transistor (TFT) is electrically connected with second sub-pixel；
In the plane for being parallel to the underlay substrate, the input terminal of the first film transistor is directed toward the side of output end
To for first direction；The direction that the input terminal of second thin film transistor (TFT) is directed toward output end is also first direction.
Second aspect, the embodiment of the invention also provides a kind of display panel, any battle array provided including first aspect
Column substrate further includes the color membrane substrates being oppositely arranged with the array substrate, and is located at the array substrate and the color film
Liquid crystal layer between substrate.
The third aspect, the embodiment of the invention also provides a kind of display devices, provide including second aspect any aobvious
Show panel.
Array substrate provided in an embodiment of the present invention, by being arranged in the plane for being parallel to underlay substrate, the first film
The direction that the input terminal of transistor is directed toward output end is first direction；The input terminal of second thin film transistor (TFT) is directed toward the side of output end
To also be first direction.I.e. by being arranged in the plane for being parallel to underlay substrate, the input terminal of first film transistor is directed toward
The direction of output end is identical as the input terminal of the second thin film transistor (TFT) direction direction of output end, can make in film crystal as a result,
In the preparation process of pipe, although other knots in the input terminal of thin film transistor (TFT) and the film layer and thin film transistor (TFT) where output end
There are contraposition deviations in technique for film layer where structure (such as control terminal), but the first film caused by the film layer contraposition deviation is brilliant
The electric property of body pipe variation it is identical as the variation of the electric property of the second thin film transistor (TFT), i.e., first film transistor source/
It drains identical as the parasitic capacitance Cgs that grid generates.To even if there are film layer contraposition deviations, due to first film transistor
Consistent with the variation of the second thin film transistor (TFT), the voltage change of pixel electrode is consistent, the feed-trough voltage (feedthrough) of generation
Unanimously, be conducive to improve vertical line, reduce and show uneven and image retention risk in flashing picture, thus be conducive to promote image quality, into
And be conducive to be promoted the display performance of display panel and display device, it in addition can avoid the Compensation Design of coupled capacitor, to have
Conducive to ensuring higher aperture opening ratio and lesser feedtrough voltage.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram for array substrate that the prior art provides；
Fig. 2 is a kind of structural schematic diagram of array substrate provided in an embodiment of the present invention；
Fig. 3 is the enlarged structure schematic diagram of thin film transistor (TFT) in Fig. 2；
Fig. 4 is the structural schematic diagram of thin film transistor (TFT) in another array substrate provided in an embodiment of the present invention；
Fig. 5 is the structural schematic diagram of thin film transistor (TFT) in another array substrate provided in an embodiment of the present invention；
Fig. 6 is the structural schematic diagram of another array substrate provided in an embodiment of the present invention；
Fig. 7 is the schematic diagram of the section structure of the A1-A2 along Fig. 3；
Fig. 8 is a kind of structural schematic diagram of display panel provided in an embodiment of the present invention；
Fig. 9 is a kind of structural schematic diagram of display device provided in an embodiment of the present invention.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing and it is not all.
Fig. 1 is a kind of structural schematic diagram for array substrate that the prior art provides, and shows the structure of thin film transistor (TFT).Ginseng
According to Fig. 1, which includes scan line 011, data line 012, pixel 013, compensating electric capacity 014 and thin film transistor (TFT) 020；
Thin film transistor (TFT) 020 includes control terminal 021, input terminal 022 and output end 023.Wherein, which uses dual gate
Design, that is, two column pixels 013 being disposed adjacent share a data line 012.In general, the thin film transistor (TFT) cloth of the array substrate 01
In office, for the two neighbouring thin film transistor (TFT)s 020 being electrically connected with same data line 012, it is directed toward by input terminal 022
The direction of output end 023 is opposite.Illustratively, 019 institute of the first extreme direction 018 and the second extreme direction respectively as shown in figure 1
Show.Control terminal 021 can be grid, and input terminal 022 can be drain electrode, and output end 023 can be source electrode.In actual production process, work as source
Film layer deposits contraposition deviation relative to grid layer where pole and drain electrode, when such as left/right offset, the grid source coupling of adjacent two column pixel 013
Closing capacitor (coupled capacitor between source electrode and grid) can be variant, so as to cause the presence of its feedthrough (feedthrough) voltage
The voltage of difference, pixel electrode generates difference, and vertical line is caused to generate.The design of compensating electric capacity 014 can solve the problems, such as this, but mend
On the one hand the design for repaying capacitor can reduce aperture opening ratio, on the other hand will lead to the increase of grid source coupled capacitor, and feed-trough voltage accordingly increases
Greatly, to generate flashing (flicker) and image retention variation, cause the image quality of display panel and display device poor, so as to cause
Display performance is poor.
In view of the above-mentioned problems, the embodiment of the present invention provides a kind of array substrate, underlay substrate is parallel to by being arranged in
In plane, the direction that the input terminal of first film transistor is directed toward output end is first direction；The input of second thin film transistor (TFT)
The direction that output end is directed toward at end is also first direction, can solve the coupling generated due to grid layer and source-drain electrode layer contraposition offset
On the one hand the inconsistent problem of capacitance variations can avoid compensating electric capacity design as a result, be conducive to improve aperture opening ratio；On the other hand,
While improving vertical line, uneven and image retention risk can be reduced in flashing face, to be conducive to promote image quality and product is shown
Performance.
Array substrate provided in an embodiment of the present invention is illustrated below with reference to Fig. 2-Fig. 6.
It is noted that hereinafter, when not indicating " first " and " second ", structure representated by a structure title includes " the
One ", also include " second ".For example, scan line can represent the first scan line and the second scan line, sub-pixel can represent the first sub- picture
Element and the second sub-pixel, thin film transistor (TFT) can represent first film transistor and the second thin film transistor (TFT).
Fig. 2 is a kind of structural schematic diagram of array substrate provided in an embodiment of the present invention, and Fig. 3 is thin film transistor (TFT) in Fig. 2
Enlarged structure schematic diagram.Referring to figs. 2 and 3, which includes: underlay substrate 100；It is set to underlay substrate 100
Multiple scanline groups 110, multiple data lines 120 and the multiple pixel groups 130 of side, multiple pixel groups 130 are arranged in array,
Each pixel group 130 includes the first sub-pixel 131 and the second sub-pixel 132 set gradually along line direction X；Each scan line
Group 110 includes the first scan line 111 and the second scan line 112, the first sub-pixel 131 and second in same pixel group 130
Sub-pixel 132 is located between the first scan line 131 and the second scan line 132 of the same scanline groups 130, and data line 120 is set
It is placed between the first sub-pixel 131 of same pixel group 130 and the second sub-pixel 132；Pixel group 130 further includes the first film crystalline substance
Body pipe 141 and the second thin film transistor (TFT) 142；The input terminal 1411 and second of the first film transistor 141 of same pixel group 130
The input terminal 1421 of thin film transistor (TFT) 142 is and in the first sub-pixel 131 and the second sub-pixel 132 of the pixel group 130
Between data line 120 be electrically connected, the output end 1412 of first film transistor 141 is electrically connected with the first sub-pixel 131, and second is thin
The output end 1422 of film transistor 142 is electrically connected with the second sub-pixel 132；In the plane for being parallel to underlay substrate 100, first
The direction that the input terminal 1411 of thin film transistor (TFT) 141 is directed toward output end 1412 is first direction 09；Second thin film transistor (TFT) 142
The direction that input terminal 1421 is directed toward output end 1422 is also first direction 09.
Wherein, underlay substrate 100 has support protective effect, can be rigid substrates, such as glass substrate or silicon substrate；?
It can be flexible base board, such as polyimide substrate or stainless steel substrate；Can also be skilled person will appreciate that other types
Or the substrate of material, the embodiment of the present invention are not construed as limiting this.
Wherein, the first scan line 111 and the second scan line 112 are respectively used to thin to first film transistor 141 and second
Film transistor 142 provides switch control signal.Illustratively, switch control signal can be low and high level signal.For example, high level
When, thin film transistor (TFT) is opened；When low level, thin film transistor (TFT) shutdown；Alternatively, when high level, thin film transistor (TFT) shutdown, low level
When, thin film transistor (TFT) is opened.The switch shape of low and high level signal and thin film transistor (TFT) can be set according to the type of thin film transistor (TFT)
The corresponding relationship of state, the embodiment of the present invention are not construed as limiting this.
It should be noted that the first sub-pixel 131 in each pixel group 130 is all the same, and second in each pixel group 130
Sub-pixel 132 is all the same；First film transistor 141 in each pixel group 130 is all the same, and second in each pixel group 130
Thin film transistor (TFT) 142 is all the same.Herein, it can will belong to the first sub-pixel 131, the second sub-pixel of different pixels group 130
132, first film transistor 141 and the second thin film transistor (TFT) 142 are example, to array substrate provided in an embodiment of the present invention
10 illustrate.
Wherein, data line 120 is used for through first film transistor 141 and the second thin film transistor (TFT) 142 respectively to first
Sub-pixel 131 and the second sub-pixel 132 provide data-signal.Illustratively, data-signal can be voltage signal, data-signal
Size corresponds to the bright dark of the display brightness of the sub-pixel in the display panel that the array substrate is subsequently formed and display device, specifically
Corresponding relationship can not repeat this and also be not construed as limiting according to array substrate and display demand setting, the embodiment of the present invention.
Wherein, the pixel group 130 that 5 rows 4 column are illustratively shown in Fig. 2 in other embodiments can also be according to battle array
The actual demand of column substrate 10, the quantity and array arrangement mode, the embodiment of the present invention that pixel group 130 is arranged do not limit this
It is fixed.
On this basis, the first scan line in a scanline groups 110 that setting is electrically connected with same one-row pixels group 130
111 and second scan line 112 be located at the opposite sides of the row pixel group 130, two in the same pixel group 130 can be made
Sub-pixel is electrically connected with two scan lines in the same scanline groups 110 respectively.
Illustratively, the first sub-pixel 131 is electrically connected by first film transistor 141 with the first scan line 111, and second
Sub-pixel 132 is electrically connected by the second thin film transistor (TFT) 142 with the second scan line 112, related to the first scan line 111 as a result,
Connecting line connecting line relevant to the second scan line 112 between without intersecting, do not need cross-line design, array substrate can be made
Layout is simpler, and film layer design is simpler.
Wherein, in the plane for being parallel to underlay substrate 100, the input terminal 1411 of first film transistor 141 is directed toward defeated
The direction of outlet 1412 is first direction 09；The input terminal 1421 of second thin film transistor (TFT) 142 is directed toward the direction of output end 1422
It also is first direction 09.That is, first film transistor 141 and the second thin film transistor (TFT) 142 are directed toward output end by input terminal
Direction is all the same.
Illustratively, shown in Fig. 3 for orientation, which can be to be parallel to line direction X and be directed to
Left direction, or be interpreted as perpendicular to column direction Y and refer both to direction to the left.In other embodiments, first direction 09 can
Any direction in plane to be parallel to underlay substrate 100, can be by plane that line direction X and column direction Y be determined
Any direction, the embodiment of the present invention are not construed as limiting this.
Wherein, the control terminal of first film transistor 141 and output end 1412 are on the direction perpendicular to underlay substrate 100
Overlapping to form first grid source coupled capacitor, the control terminal and output end 1422 of the second thin film transistor (TFT) 142 are perpendicular to substrate base
It is overlapped on the direction of plate 100 and forms second gate source coupled capacitor.First grid source coupled capacitor and second gate source coupled capacitor difference
The data-signal that data line 120 is transmitted to the first sub-pixel 131 and the second sub-pixel 132 is influenced, and then influences pixel electrode and fills
Electric potential.Meanwhile the control terminal of thin film transistor (TFT) and the overlapping area of output end are bigger, the capacitance of grid source coupled capacitor is bigger,
Influence to data-signal is bigger.
The embodiment of the present invention is directed toward by the input terminal of setting first film transistor 141 and the second thin film transistor (TFT) 142
The direction of output end is that same direction even if generating contraposition deviation between film layer, i.e., misplaces in manufacturing process between film layer
When, first grid source coupled capacitor is consistent with the variation tendency of second gate source coupled capacitor, or increases simultaneously, or reduce simultaneously, by
This causes the voltage of pixel electrode identical by the influence of grid potential, if grid potential moment drags down, the voltage of pixel electrode
Because the influence of grid source coupled capacitor can also drag down moment, the variation of first grid source coupled capacitor and second gate source coupled capacitor becomes
Gesture is consistent, so the feed-trough voltage generated is consistent.It misplaces between film layer to the first sub-pixel 131 and the second sub-pixel 132 as a result,
The influence of the data-signal eventually received is consistent, on the one hand can avoid compensating electric capacity design, is conducive to promote opening for sub-pixel
Mouth rate；On the other hand, vertical line can be improved, meanwhile, uneven and image retention risk in flashing face can be reduced, to be conducive to promote picture
Matter and product display performance.
In addition, compare Fig. 3 and Fig. 1, array substrate 10 provided in an embodiment of the present invention can also will on spatial position distance
It is arranged in a staggered manner between the control terminal of closer first film transistor 141 and the control terminal of the second thin film transistor (TFT) 142, it is exemplary
, it will be staggered between the second thin film transistor (TFT) 142 of upper pixel group 130 and the first film transistor 141 of next pixel group 130
Setting, or by the second thin film transistor (TFT) 142 of the first film transistor 141 of upper pixel group 130 and next pixel group 130
Between be arranged in a staggered manner, it should be noted that up and down just for diagram for, in addition upper pixel group refers to phase with next pixel group
In adjacent two row pixels, two pixel groups being electrically connected with same data line.And the control terminal of thin film transistor (TFT) is relative to scan line
Area it is larger, be not thorough and cause so set, can avoid etching that may be present when being oppositely arranged large-area metal block
The risk of short circuit be conducive to improve product yield so that technology difficulty can be made by advantageously reducing.
It should be noted that the merely exemplary data line 120 that shows is the straight line extended along column direction Y in Fig. 2, first
Scan line 111 and the second scan line 112 are the straight line extended along line direction X, but are not constituted to provided in an embodiment of the present invention
The restriction of array substrate 10.In actual products, data line 120, the first scan line 111 and the second scan line 112 line style and
Cabling can be arranged according to the actual demand of array substrate 10, and the embodiment of the present invention is not construed as limiting this.
Secondly, it should be noted that merely exemplary with thin film transistor (TFT) (including first film transistor and the in Fig. 3
Two thin film transistor (TFT)s) channel shape be it is U-shaped array substrate 10 provided in an embodiment of the present invention is illustrated, but not structure
The restriction of pairs of array substrate 10 provided in an embodiment of the present invention.In other embodiments, the channel shape of thin film transistor (TFT)
It can also be L-type or I type.
Again, it should be noted that first and second only for identical sub-pixel, the thin film transistor (TFT) in same group
It distinguishes and names with scan line, in photoelectric properties and indistinction, i.e. " first " and " second " can be exchanged in word order.This
Another form of presentation that sub-pixel, thin film transistor (TFT) and scan line are indicated in scheme of the invention can also be that the first sub-pixel is logical
It crosses first film transistor to be electrically connected with the second scan line, the second sub-pixel passes through the second thin film transistor (TFT) and the first scan line electricity
Connection；Or can be electrically connected with the first scan line for the first sub-pixel by the second thin film transistor (TFT), the second sub-pixel passes through the
One thin film transistor (TFT) is electrically connected with the second scan line, or can be the skilled addressee will appreciate that other form of presentation, sheet
Inventive embodiments are not construed as limiting this.
Illustratively, Fig. 4 is the structural representation of thin film transistor (TFT) in another array substrate provided in an embodiment of the present invention
Figure, the partial structurtes of array substrate 10 when the channel shape for showing thin film transistor (TFT) is I type.Fig. 5 mentions for the embodiment of the present invention
The structural schematic diagram of thin film transistor (TFT) in another array substrate supplied, when the channel shape for showing thin film transistor (TFT) is L-type
The partial structurtes of array substrate 10.In array substrate 10 shown in Fig. 4 and Fig. 5, by the way that first film transistor and second is arranged
The direction that the input terminal of thin film transistor (TFT) is directed toward output end is first direction 09, so that dislocation is to the first sub-pixel between film layer
131 is consistent with the influence of the data-signal eventually received of the second sub-pixel 132, on the one hand can avoid compensating electric capacity design,
Be conducive to be promoted the aperture opening ratio of sub-pixel；On the other hand, vertical line can be improved, meanwhile, it can reduce uneven and image retention in flashing face
Risk, to be conducive to promote image quality and product display performance.
Optionally, with continued reference to Fig. 2, in the plane for being parallel to underlay substrate 100, along line direction X, in same pixel group
In 130, first film transistor 141 is located at the first sub-pixel 131 towards the side of the second sub-pixel 132, the second film crystal
Pipe 142 is located at the side that the second sub-pixel 132 deviates from the first sub-pixel 131.
So set, can make thin film transistor (TFT) be located at same data line 120 electrical connection adjacent subpixels it is same
Side, to can realize that the direction of input terminal direction output end in the thin film transistor (TFT) of all sub-pixels in array substrate 10 is equal
Identical, the pole orientation of alternatively referred to as input terminal and output end is all the same.
Illustratively, each thin film transistor (TFT) is respectively positioned on the right side of the sub-pixel being electrically connected in Fig. 2, in other embodiment party
In formula, thin film transistor (TFT) may be additionally located at the left side for the sub-pixel being electrically connected, and can be set according to the actual demand of array substrate 10
It sets, the embodiment of the present invention is not construed as limiting this.In addition, the first sub-pixel 131 can drain electrode with first film transistor and number
It is located at first according to the first film transistor 141 that line is electrically connected without cross-line is additionally arranged, relative to same pixel group 130
Sub-pixel 131 far from the second sub-pixel 132 side when, the drain electrode of thin film transistor (TFT) is electrically connected the additional setting of needs with data line
For increasing process flow and cost of manufacture caused by cross-line, array substrate 10 provided in an embodiment of the present invention can avoid setting
Cross-line advantageously reduces process flow, reduces cost of manufacture.
Optionally, with continued reference to Fig. 2, the line and the first son of first film transistor 141 and the second thin film transistor (TFT) 142
The diagonal line extending direction of pixel 131 or the second sub-pixel 132 is identical.
So set, first film transistor 141 and the second thin film transistor (TFT) 142 can be made in 131 He of the first sub-pixel
At the corner location of second sub-pixel 132.
Illustratively, by taking orientation shown in Figure 2 as an example, first film transistor 141 can be located at the second sub-pixel 132
The upper left corner, the second thin film transistor (TFT) 142 can be located at the lower right corner of the second sub-pixel 132.In other embodiments, it can also set
It sets, first film transistor 141 is located at the upper right corner of the first sub-pixel 131, and the second thin film transistor (TFT) 142 is located at the first sub-pixel
131 lower left corner；Or use skilled person will appreciate that other modes, the embodiment of the present invention is not construed as limiting this.
The benefit of such setting includes at least in terms of following three: first, for first film transistor 141, and nothing
Need to additionally be arranged lead drained (or source electrode) be electrically connected with data line 120, thus can reduce lead occupancy area, favorably
In reserved bigger area pixel electrode is arranged, thus it is advantageously ensured that higher aperture opening ratio；Second, for the second film crystalline substance
For body pipe 142, source electrode (or drain electrode) can be directly electrically connected with the pixel electrode of the second sub-pixel 132, (such as without bending
The position between data line and the second sub-pixel is arranged in second thin film transistor (TFT), at this point, in order to guarantee thin film transistor (TFT)
Input terminal is consistent with output end direction, needs to bend output end design to guarantee to be electrically connected with pixel electrode), it thus can be true
Lower design difficulty is protected, and lower to etching precision requirement, it is advantageously ensured that production yield, reduces cost；The third aspect, can
By the second thin film transistor (TFT) 142 connected in lastrow pixel group 130 and the first film transistor in this one-row pixels group 130
141 on spatial position between be staggered, be not thorough to can avoid etching that may be present when being oppositely arranged large-area metal block
Caused by short-circuit risk be conducive to improve product yield so that technology difficulty can be made by advantageously reducing.
It should be noted that diagonal line extending direction here can be regarded as connecting boundary inflection point position opposite up and down
The direction set.Illustratively, by taking sub-pixel is polygon as an example, diagonal line extending direction may include upper left inflection point and bottom right inflection point
Line direction or upper right inflection point and lower-left inflection point line direction, the embodiment of the present invention is not construed as limiting this.
Secondly, it should be noted that it is that middle part is raised polygon to the right that sub-pixel shape is illustratively shown in Fig. 2
The primitive shape of domain structure in pairs is such as arranged in shape.In other embodiments, the shape of sub-pixel can also be according to array substrate 10
Actual demand setting, such as only turning recess polygon, or skilled person will appreciate that other shapes, this hair
Bright embodiment is not construed as limiting this.
Optionally, Fig. 6 is the structural schematic diagram of another array substrate provided in an embodiment of the present invention, referring to Fig. 2 and figure
6, in same pixel group 130, the polarity of the first sub-pixel 131 and the second sub-pixel 132 that are electrically connected with same data line 120
It is opposite or identical.
So set, can make for same pixel group 130, data line 120 is that the first sub-pixel 131 provides a positive polarity number
After voltage signal, a negative polarity data voltage signal is provided for the second sub-pixel or data line 120 is the first sub-pixel
After 131 provide a negative polarity data voltage signals, provide a positive polarity data voltage signal for the second sub-pixel, or with it is same
After the same pixel group of data line electrical connection provides positive polarity data voltage signal, negative polarity number is provided to the pixel group of adjacent rows
According to voltage signal, or after the same pixel group that is electrically connected with same data line provides negative polarity data voltage signal, to adjacent
Capable pixel group provides positive polarity data voltage signal, and the reversion of availability data voltage signal polarity, avoids same as a result,
When data line 120 persistently provides the voltage signal of identical polar, due to sub-pixel electric leakage and adjacent two column sub-pixel polarity phase
The poor problem of display image quality with caused by, to be conducive to improve image quality.
It should be noted that the polar setting of sub-pixel is also related to driving method, it is merely exemplary in Fig. 2 to show together
Polarity inversion mode on one data line be "+,-,-,+,+,-... " or "-,+,+,-,-,+... ", in Fig. 6 only
Illustratively show on same data line polarity inversion mode be "+,+,-,-,+,+... " or "-,-,+,
+,-,-,……".It in other embodiments, can also be ability according to the actual demand of array substrate, setting inversion mode
Other modes known to field technique personnel, the embodiment of the present invention are not construed as limiting this.
Optionally, with continued reference to Fig. 3, Fig. 4 or Fig. 5, the first sub-pixel 131 for being electrically connected with same data line 120 and
Second sub-pixel 132 is located at the two sides of data line 120；Input terminal of the segment data line 120 as first film transistor 141
1411 or input terminal 1421 of the segment data line 120 as the second thin film transistor (TFT) 142.
So set, partial function structure of the availability data line 120 as thin film transistor (TFT), thus thin film transistor (TFT) with
Data line can overlap in space layout, lay data line 120, first film transistor 141 and the to advantageously reduce
Space used in two thin film transistor (TFT)s 142 is conducive to reserve biggish space to form sub-pixel, to be conducive to promote opening
Rate.
Optionally, with continued reference to Fig. 3, Fig. 4 or Fig. 5, the input terminal 1421 of the second thin film transistor (TFT) 142 passes through auxiliary connection
Line 150 is electrically connected with data line 120.
Illustratively, thin film transistor (TFT) is respectively positioned on the same side of sub-pixel, 142 range data line of the second thin film transistor (TFT)
120 distance farther out, and the input terminal of the second thin film transistor (TFT) 142 be located at its output end deviate from data line 120 side.Pass through
Assistant connection wire 150 is set, the input terminal 1421 of the second thin film transistor (TFT) 142 can be made to realize with data line 120 and be electrically connected, it is ensured that
Data-signal on data line 120 can normally be provided to the second sub-pixel 132.
Optionally, Fig. 7 is the schematic diagram of the section structure of the A1-A2 along Fig. 3.Referring to Fig. 3 and Fig. 7, assistant connection wire 150 with
1421 same layer of input terminal of second thin film transistor (TFT) 142 is arranged；The input terminal 1421 of second thin film transistor (TFT) 142 is the second film
The source electrode of transistor 142 or drain electrode, it should be noted that thin-film transistor structure includes active layer 160, according to active layer 160
Material it is different, the type of thin film transistor (TFT) can be amorphous silicon film transistor, low-temperature polysilicon film transistor or oxygen
Compound thin film transistor (TFT), it is not limited here.According to active layer with grid layer (film layer i.e. where scan line) relative to lining
The position of substrate is different, and the structure of thin film transistor (TFT) can be top gate structure and bottom grating structure, in figure only by taking bottom grating structure as an example,
It is not limited thereto.
It wherein, can not by the way that the source electrode of assistant connection wire 150 and the second thin film transistor (TFT) 142 or drain electrode same layer to be arranged
The additional quantity for increasing film layer, to be advantageously implemented the lightening design of array substrate, display panel and display device.
Wherein, the control terminal of the second thin film transistor (TFT) 142 can be grid, with the first scan line 111 and the second scan line 112
Same layer setting.
It should be noted that merely exemplary in Fig. 7 show and inventive point phase claimed of the embodiment of the present invention
The film layer of pass, in other embodiments, array substrate 10 may also include gate insulation layer, interlayer dielectric layer and art technology
Other function film layer known to personnel, the embodiment of the present invention are not construed as limiting this.
Optionally, with continued reference to Fig. 3 and Fig. 7, the vertical throwing at least partially in underlay substrate 100 of assistant connection wire 150
Shadow is between the first scan line 111 and the second scan line 112.
So set, the overlapping area of assistant connection wire 150 and the first scan line 111 and the second scan line 112 can be reduced,
It is overlapped and the influence of the performance to the second thin film transistor (TFT) 142 to advantageously reduce assistant connection wire 150 and scan line, thus
It is advantageously ensured that first film transistor 141 is consistent with the performance of the second thin film transistor (TFT) 142, and then it is advantageously ensured that display picture
Matter promotes display performance.
It should be noted that merely exemplary in Fig. 7 show the first scan line 111 and the second scan line 112 is respectively positioned on
Assistant connection wire 150 is not constituted close to the side of underlay substrate 100 to array substrate 10 provided in an embodiment of the present invention
It limits.In other embodiments, also each film layer can be set relative to array substrate according to the actual demand of array substrate 10
100 position, the embodiment of the present invention are not construed as limiting this.
On the basis of the above embodiment, the embodiment of the present invention also provides a kind of display panel, which includes
Any array substrate that above embodiment provides, therefore the array base that also there is the display panel above embodiment to provide
Beneficial effect possessed by plate can refer to understanding above, and this will not be repeated here.
Illustratively, Fig. 8 is a kind of structural schematic diagram of display panel provided in an embodiment of the present invention.Referring to Fig. 8, this is aobvious
Show that panel 20 further includes the color membrane substrates 220 being oppositely arranged with array substrate 10, and is located at array substrate 10 and color membrane substrates
Liquid crystal layer 200 between 220.
Wherein, color membrane substrates 220 include colored color blocking block, black light shield layer and skilled person will appreciate that other
Structure；Liquid crystal layer 200 may include skilled person will appreciate that any type liquid crystal material, the embodiment of the present invention is to this
It is not construed as limiting.
On the basis of the above embodiment, the embodiment of the present invention also provides a kind of display device, which includes
Any display panel that above embodiment provides, display panel include any array base that above embodiment provides
Plate, thus the display device also have above embodiment provide display panel and array substrate possessed by technical effect,
It can refer to understanding above, do not repeat herein.
Illustratively, Fig. 9 is a kind of structural schematic diagram of display device provided in an embodiment of the present invention.Referring to Fig. 9, this is aobvious
Showing device 30 includes display panel 20.
The merely exemplary display device 30 that shows is mobile phone, in other embodiments, the display device 30 in Fig. 9
Can also for tablet computer, intelligent wearable device or skilled person will appreciate that other kinds of dress having a display function
It sets or equipment, the embodiment of the present invention is not construed as limiting this.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (11)
1. a kind of array substrate characterized by comprising
Underlay substrate；
It is set to the multiple scanline groups, multiple data lines and multiple pixel groups of underlay substrate side, the multiple pixel group
It is arranged in array, each pixel group includes the first sub-pixel and second sub-pixel set gradually along line direction；
Each scanline groups include the first scan line and the second scan line, first son in the same pixel group
Pixel and second sub-pixel are located between first scan line and the second scan line of the same scanline groups, institute
Data line is stated to be set between first sub-pixel of pixel group described in same row and second sub-pixel；
The pixel group further includes first film transistor and the second thin film transistor (TFT)；Described the first of the same pixel group is thin
The input terminal of the input terminal of film transistor and second thin film transistor (TFT) be located at the pixel group it is described first son
Data line electrical connection among pixel and second sub-pixel, the output end of the first film transistor and described the
The electrical connection of one sub-pixel, the output end of second thin film transistor (TFT) are electrically connected with second sub-pixel；
In the plane for being parallel to the underlay substrate, the direction that the input terminal of the first film transistor is directed toward output end is
First direction；The direction that the input terminal of second thin film transistor (TFT) is directed toward output end is also first direction.
2. array substrate according to claim 1, which is characterized in that in the plane for being parallel to the underlay substrate, edge
Line direction, in the same pixel group, the first film transistor is located at first sub-pixel towards second son
The side of pixel, second thin film transistor (TFT) are located at the side that second sub-pixel deviates from first sub-pixel.
3. array substrate according to claim 2, which is characterized in that the first film transistor and second film
The line of transistor is identical as the diagonal line extending direction of first sub-pixel or second sub-pixel.
4. array substrate according to claim 1, which is characterized in that described be electrically connected with data line described in same
One sub-pixel and second sub-pixel are located at the two sides of the data line；
Input terminal of the part data line as the first film transistor, or
Input terminal of the part data line as second thin film transistor (TFT).
5. array substrate according to claim 1, which is characterized in that in the same pixel group, with number described in same
It is opposite or identical according to first sub-pixel of line electrical connection and the polarity of second sub-pixel.
6. array substrate according to claim 1, which is characterized in that the input terminal of second thin film transistor (TFT) passes through auxiliary
Connecting line is helped to be electrically connected with the data line.
7. array substrate according to claim 6, which is characterized in that the assistant connection wire and second film crystal
The input terminal same layer of pipe is arranged；
The input terminal of second thin film transistor (TFT) is source electrode or the drain electrode of second thin film transistor (TFT).
8. array substrate according to claim 7, which is characterized in that the assistant connection wire at least partially in the lining
The upright projection of substrate is between first scan line and second scan line.
9. array substrate according to claim 1, which is characterized in that the first film transistor and/or described second
The channel shape of thin film transistor (TFT) is U-shaped, L-type or I type.
10. a kind of display panel, which is characterized in that including the described in any item array substrates of claim 1-9；Further include and institute
The color membrane substrates that array substrate is oppositely arranged are stated, and the liquid crystal layer between the array substrate and the color membrane substrates.
11. a kind of display device, which is characterized in that including display panel described in any one of claim 10.
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| CN201910580876.0A CN110308600A (en) | 2019-06-29 | 2019-06-29 | Array substrate, display panel and display device |
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| CN201910580876.0A CN110308600A (en) | 2019-06-29 | 2019-06-29 | Array substrate, display panel and display device |
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