CN104157628A - 一种新型电力电子模块 - Google Patents
一种新型电力电子模块 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Abstract
本发明的目的在于针对现有DBC板在均流设计中的不足提供一种新型电力电子模块,该电力电子模块为陶瓷-金属复合板结构,该结构包括上铜层、陶瓷层、二极管芯片、功率器件芯片、母排端子,其特征在于所述模块还包括并联的3个或3个以上的功率器件芯片,母排端子放置在所有以上并联的芯片的中心位置。使得各支路回路的分布电感一致,极大程度上实现了拓扑的并联一致性,提高模块的可靠性。消除了并联电路的支路电感不均匀的情况,很好的实现了支路均匀性,利于高频化、高功率化下的并联均流,极大程度上缓解了散热压力,提高模块的可靠性。
Description
技术领域
本发明涉及电力电子技术领域,尤其涉及适合应用于大功率电力半导体模块、功率控制电路、智能功率组件和高频开关电源等,具体是涉及一种电力电子功率模块DBC板设计结构。
背景技术
DBC为陶瓷-金属复合板结构的功率模块,一般在功率模块热源的上表面灌入硅胶,将热源的下表面通过双面覆铜板(DBC)和基板连接到散热器,这种散热结构可以使功率模块工作时产生的热量得到有效的向下消散,从而避免产生过高的结温,防止功率模块高温损坏。基板一般由金属(如铜或铝)或者复合材料(如铝碳化硅)制成,形状主要为长方体,起到传热和支撑的作用。DBC板是由铜箔在高温下直接键合到陶瓷基板形成的,一般采用下铜层-陶瓷层-上铜层的结构,起到绝缘和导热的作用。比起传统的PCB板来说,DBC版由于导电截面大,因此回路感抗明显减小,同时散热性也比传统树脂做成的PCB版更佳。
虽然DBC板的回路感抗很小,但是也不能完全忽略,尤其是在高频、大功率情况下,分布参数的改良显得尤为重要。随着电力电子器件的高频化发展以及全新的SiC器件投入到生产应用中,DBC板中感抗成分占据比例越来越大,同时鉴于未来大功率模块是主流趋势之一,因此不可避免要进行同一模块上器件的并联,传统DBC回路设计存在并联回路不均匀性,导致并联器件的动、静态不均性,从而导致功率集中在某个单一并联回路的芯片上产生发热过多乃至失效,该情况在高频、高功率下尤为严重,因此未来DBC板的并联均流会是一大难题。鉴于此,本发明提出一种全新的DBC板设计理念,有效减小并联回路电感差异,减小回路差异以及缓解电路散热压力。
发明内容
本发明的目的在于针对现有DBC板在均流设计中的不足,提供一种新型电力电子模块,这种拓扑结构与传统结构相比,可以使并联支路的电感差异达到忽略不计,从而极大程度的打破DBC并联上的瓶颈,缓解散热压力,推动大功率乃至超大功率模块的应用。
为解决上述技术问题,本发明采用如下的技术方案是:
一种新型电力电子模块,该电力电子模块为陶瓷-金属复合板结构,该结构包括上铜层、陶瓷层、二极管芯片、功率器件芯片、母排端子,其特征在于所述模块还包括并联的3个或3个以上的功率器件芯片,母排端子放置在所有以上并联的芯片的中心位置。
本发明由于采用了以上结构,具有以下显著技术效果:
使得各支路回路的分布电感一致,极大程度上实现了拓扑的并联一致性,提高模块的可靠性。
消除了并联电路的支路电感不均匀的情况,很好的实现了支路均匀性,利于高频化、高功率化下的并联均流,极大程度上缓解了散热压力,提高模块的可靠性。
附图说明
图1是传统DBC结构的侧视图;
图2是传统DBC结构的等效电路图;
图3是本发明DBC结构的侧视图(4个功率器件芯片);
图4是本发明DBC结构的等效电路图(4个功率器件芯片);
图5是本发明DBC结构的等效电路图(3个功率器件芯片)
其中:附图标记1为DBC上铜层、附图标记2为DBC陶瓷层、附图标记3为二极管芯片、附图标记4为功率器件芯片、附图标记5为母排端子。
具体实施方式
参考附图。
本发明的结构包括上铜层1、陶瓷层2、二极管芯片3、功率器件芯片4、母排端子5,所述模块还包括并联的3个或3个以上的功率器件芯片,母排端子5放置在所有以上并联的芯片的中心位置。
传统意义上,DBC板最上层的一块块铜片称为“岛”,每个岛的都起着流通电流的作用,岛上可以焊接器件或者母排支架端子,岛与岛之间通过铝线连接。传统的DBC排布如附图1所示,等效电路如图2。从图2可以看出,由于该结构导致并联器件的“地”与地之间存在分布电感,这些分布电感以串联方式连接到端口上,造成各支路回路的杂散电感不一致,因此在动态过程中,这些电感上分布的电压会造成并联器件的地电位的不均匀性,对并联器件均流产生不利影响。
本发明在原有岛的数量基本保持不变的基础上,通过改变器件的岛与母排端子的岛的位置(如图3),来达到消除杂散电感不均匀的目的,改动位置后的等效电路如图4所示,从图4可见,每个支路的杂散电感均通过类似并联的方式连接到端口上,因此在该结构中,各支路回路的分布电感一致,极大程度上实现了拓扑的并联一致性。
Claims (1)
1.一种新型电力电子模块,该电力电子模块为陶瓷-金属复合板结构,该结构包括上铜层(1)、陶瓷层(2)、二极管芯片(3)、功率器件芯片(4)、母排端子(5),其特征在于所述模块还包括并联的3个或3个以上的功率器件芯片,母排端子(5)放置在所有以上并联的芯片的中心位置。
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CN105932016A (zh) * | 2016-06-12 | 2016-09-07 | 重庆大学 | 动静态均流的多芯片并联的功率模块 |
CN108141141A (zh) * | 2015-08-14 | 2018-06-08 | 西门子公司 | 用于变流器的相模块 |
CN108233820A (zh) * | 2016-12-16 | 2018-06-29 | 上海电驱动股份有限公司 | 一种bsg电机控制器用集成电气模块 |
CN110785001A (zh) * | 2019-10-30 | 2020-02-11 | 新鸿电子有限公司 | 用于分布式x射线源的多通道高压功率电路板和分布式x射线源 |
WO2023087842A1 (zh) * | 2021-11-16 | 2023-05-25 | 北京卫星制造厂有限公司 | 宇航电源产品的大功率模块集成电路装置及其安装方法 |
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CN108141141A (zh) * | 2015-08-14 | 2018-06-08 | 西门子公司 | 用于变流器的相模块 |
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CN105931998A (zh) * | 2016-06-17 | 2016-09-07 | 扬州国扬电子有限公司 | 一种绝缘基板结构及使用该基板的功率模块 |
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CN108233820A (zh) * | 2016-12-16 | 2018-06-29 | 上海电驱动股份有限公司 | 一种bsg电机控制器用集成电气模块 |
CN110785001A (zh) * | 2019-10-30 | 2020-02-11 | 新鸿电子有限公司 | 用于分布式x射线源的多通道高压功率电路板和分布式x射线源 |
WO2023087842A1 (zh) * | 2021-11-16 | 2023-05-25 | 北京卫星制造厂有限公司 | 宇航电源产品的大功率模块集成电路装置及其安装方法 |
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