CN104135271A - Low-pulse output circuit and equipment applying low-pulse output circuit - Google Patents
Low-pulse output circuit and equipment applying low-pulse output circuit Download PDFInfo
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- CN104135271A CN104135271A CN201410342199.6A CN201410342199A CN104135271A CN 104135271 A CN104135271 A CN 104135271A CN 201410342199 A CN201410342199 A CN 201410342199A CN 104135271 A CN104135271 A CN 104135271A
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Abstract
The invention provides a low-pulse output circuit and equipment applying the low-pulse output circuit. The low-pulse output circuit comprises a first logic circuit, a capacitor C1, a second logic circuit, a time delay circuit and a third logic circuit, wherein the input end of the first logic circuit is used for inputting a level conversion signal; the output end of the first logic circuit is connected with a first power supply, and is connected with the first input end of the second logic circuit through the capacitor C1; the first input end and the second input end of the second logic circuit are connected with a second power supply; the output end of the second logic circuit is connected with the input end of the third logic circuit through the time delay circuit; and the output end of the third logic circuit is connected with a third power supply, and is taken as a pulse output end. By adopting the low-pulse output circuit and the equipment, a step signal can be processed into a low-pulse signal, and the width of a pulse signal can be adjusted according to practical requirements.
Description
Technical field
The present invention relates to pulses switch technical field, relate in particular to a kind of low impulse output circuit and apply the equipment of low impulse output circuit.
Background technology
In current industry electronic system, the most frequently used chip is exactly MCU, and MCU needs the beginning of a lot of triggering signals as code operation as the control hinge of electronic system.But mostly peripheral triggering signal is level conversion from high to low, or level conversion from low to high, and the process chip such as MCU are because the reasons such as signal multiplexing need to be inputted of short duration pulse signal.
Due to the unicity that the processing low and high level of current industry is changed, greatly affect the input durability of MCU, cannot rationally utilize the interrupt interface resource of MCU.As turned at HDMI in MHL signal management, need MCU to control Charge Management process, but signal need to be just rushed in the triggering that turns the MCU of MHL system due to HDMI, if directly connect power supply, the management MCU that turns MHL system as HDMI during in resting state, can not meet the requirement that wakes MCU up; In the applications circuit of AC power supplies, need equally low pulse signal to wake the applications circuit of AC power supplies up, but because AC power supplies is level shifted signal from high to low, when MCU is during in resting state, AC power supplies can not meet the requirement that wakes MCU up.
Therefore, need a kind of low impulse output circuit and apply the equipment of low impulse output circuit, to avoid above-mentioned deficiency.
Summary of the invention
The object of the present invention is to provide a kind of low impulse output circuit and apply the equipment of low impulse output circuit, the step signal that low level can be turned to high level is processed into low pulse signal, thereby provides technical foundation for MCU rationally receives triggering signal easily.
For addressing the above problem, the invention provides a kind of low impulse output circuit, it is characterized in that, comprise: the first logical circuit, capacitor C 1, the second logical circuit, delay circuit and the 3rd logical circuit, the input incoming level switching signal of described the first logical circuit, the output of the first logical circuit connects the first power supply, and the output of the first logical circuit connects the input of the second logical circuit by capacitor C 1, the first input end of the second logical circuit and the second input connect second source, and the output of the second logical circuit connects the input of the 3rd logical circuit by delay circuit, the output of the 3rd logical circuit connects the 3rd power supply, the output of the 3rd logical circuit is as pulse output end.
Further, described delay circuit comprises charging delay circuit and discharge lag circuit, and charging delay circuit comprises resistance R 3 and the capacitor C 2 of series connection, and discharge lag circuit comprises capacitor C in parallel 2 and resistance R 4, and described capacitor C 2 and resistance R 4 connect earth terminal.
Further, described the first power supply connects the output of the first logical circuit by resistance R 1, can either, by the output clamper of the first logical circuit at high level, can play again the effect of current limliting, prevents because of the too high infringement to the first logical circuit of electric current.
Further, described second source connects first input end and second input of the second logical circuit by resistance R 2, can either be by the first input end of the second logical circuit and the second input clamper at high level, can play again the effect of current limliting, prevent because of the too high infringement to the second logical circuit of electric current, it is to be noted that second source is after resistance R 2, the second logical circuit and resistance R 3, the electric current producing should meet can make the 3rd logical circuit conducting, just the output output pulse signal of the 3rd logical circuit.
Further, described the 3rd power supply connects the output of the 3rd logical circuit by resistance R 5, its concrete numerical value need to be adjusted according to output, can either by the 3rd logical circuit and output clamper at high level, can play again the effect of current limliting, prevent because of the too high infringement to the 3rd logical circuit of electric current.
Further, described the 4th power supply connects the output of negative circuit by resistance R 6, can either provide high level to the output of negative circuit, and the effect that can play again current limliting prevents because of the too high infringement to negative circuit of electric current.
Further, described the first power supply, second source, the 3rd power supply and the 4th power supply, meet the start voltage higher than this high impulse output circuit, higher than signal input part voltage.
As a kind of optimal way of the low impulse output circuit of the present invention, described RC delay circuit comprises by resistance R 3 and capacitor C 2 charging delay circuit in series, and the discharge lag circuit, capacitor C 2 and resistance R 4 earth terminals that are formed by capacitor C 2 and resistance R 4 parallel connections.Adopt this circuit structure, can either realize charging and discharging time delay, circuit structure is comparatively simple again simultaneously.
Further, described the first logical circuit adopts first metal-oxide-semiconductor with N raceway groove, and its grid connects level shifted signal as input, source ground end, and drain electrode connects the first power supply and capacitor C 1 as output by pull-up resistor R1; Described the second logical circuit adopts second metal-oxide-semiconductor with P raceway groove, and its grid connects capacitor C 1 and second source as input, and drain electrode connects RC as output and connects delay circuit, and source electrode connects second source as the first output; Described the 3rd logical circuit adopts the 3rd metal-oxide-semiconductor with N raceway groove, and its grid connects delay circuit as input, its source ground end, and its drain electrode connects the 3rd power supply as output and by pull-up resistor R5.
As the one distortion of the low impulse output circuit of the present invention, described the first logical circuit adopts NPN triode, and its base stage connects level shifted signal as input, grounded collector end, and emitter connects the first power supply and capacitor C 1 as output, the second logical circuit adopts PNP triode, and its base stage connects capacitor C 1 and second source as first input end, and emitter connects delay circuit as output, and collector electrode connects second source as the second input, the 3rd logical circuit adopts NPN triode, its grid is as input, its source ground end, its drain electrode is as output and connect the 3rd power supply, the base stage of described NPN triode with there is the first metal-oxide-semiconductor of N raceway groove and the grid connected mode of the 3rd metal-oxide-semiconductor is identical, the collector electrode of NPN triode with there is the first metal-oxide-semiconductor of N raceway groove and the source electrode connected mode of the 3rd metal-oxide-semiconductor is identical, the emitter of NPN triode with there is the first metal-oxide-semiconductor of N raceway groove and the drain electrode connected mode of the 3rd metal-oxide-semiconductor is identical, the base stage of described PNP triode is identical with the grid connected mode of the second metal-oxide-semiconductor with P raceway groove, the collector electrode of PNP triode is identical with the source electrode connected mode with P raceway groove the second metal-oxide-semiconductor, the emitter of PNP triode is identical with the drain electrode connected mode of the second metal-oxide-semiconductor with P raceway groove.
Further, as the one distortion of the low impulse output circuit of the present invention, the first logical circuit, the second logical circuit and the 3rd logical circuit adopt the combinational circuit with door and inverter, with the input of door as signal input part, the output of inverter is as signal output part, level shifted signal is by inputting with the input of door, output by inverter is exported, concrete, in described the first logical circuit with the input incoming level switching signal of door, in the first logical circuit, the output of inverter connects the first power supply, and in the first logical circuit, the output of inverter connects in the second logical circuit and the first input end of door by capacitor C 1, in the second logical circuit, be connected second source with first input end and second input of door, and in the second logical circuit, the output of inverter connects in the 3rd logical circuit and the input of door by delay circuit, in the 3rd logical circuit, the output of inverter connects the 3rd power supply, in the 3rd logical circuit, the output of inverter is as pulse output end, adopt the circuit of this kind of structure also can meet the demands, but Comparatively speaking, adopt metal-oxide-semiconductor circuit structure more simple, cost is lower.
Its specific works principle is: in the time that the grid connection incoming level of the first metal-oxide-semiconductor is changed from low to high, the first metal-oxide-semiconductor conducting, capacitor C 1 transient switching, the grid of the second metal-oxide-semiconductor is of short duration is low level, the second metal-oxide-semiconductor conducting, and second source charges to capacitor C 2 by resistance R 3, the ON time of delay control three metal-oxide-semiconductors, after having charged, the grid of the 3rd metal-oxide-semiconductor becomes high level, thus the 3rd metal-oxide-semiconductor conducting, and the drain electrode output of the 3rd metal-oxide-semiconductor transfers low level to by high level.Capacitor C 1 is due to capacity effect, the second metal-oxide-semiconductor recovers cut-off state, capacitor C 2 is discharged by resistance R 4, therefore the grid level of the 3rd metal-oxide-semiconductor is dragged down, the 3rd metal-oxide-semiconductor cut-off, the drain electrode output of the 3rd metal-oxide-semiconductor reverts to high level by low level, and therefore the drain electrode output of the 3rd metal-oxide-semiconductor is low pulse.Wherein, in discharge process, the deadline that the discharge lag circuit that capacitor C 2 and resistance R 4 form can delay control three metal-oxide-semiconductors, by adjusting the length that the value of capacitor C 2 and resistance R 4 can the control lag time, thereby control the width of output pulse.
The present invention also provides a kind of signal conversion equipment, comprise that HDMI turns MHL system, connect the MCU that described HDMI turns MHL system, connect the low impulse output circuit of described MCU, described low impulse output circuit input is in order to connect HDMI cable, when HDMI cable connects after low impulse output circuit as shown in Figure 2, through circuit conversion, after being converted to low pulse, HDMI level signal from low to high exports, wake the MCU in dormancy up, MCU management is controlled HDMI and is turned MHL system, exports after the HDMI signal of input system is converted into MHL signal.In the time not having HDMI cable to connect, pulse conversion circuit is not exported low pulse signal, and MCU keeps resting state, has saved MCU resource, has improved the utilance of MCU.
The present invention also provides a kind of low impulse output circuit, comprise capacitor C 1, the second logical circuit, delay circuit and the 3rd logical circuit, capacitor C 1 one end connects the first power supply, the other end connects the input of described the second logical circuit, the input of the second logical circuit and the first output connect second source, the second output of the second logical circuit connects the input of the 3rd logical circuit by delay circuit, the output of the 3rd logical circuit connects the 3rd power supply, and the output of the 3rd logical circuit is as pulse output end.
Further, described delay circuit comprises charging delay circuit and discharge lag circuit, and charging delay circuit comprises resistance R 3 and the capacitor C 2 of series connection, and discharge lag circuit comprises capacitor C in parallel 2 and resistance R 4, and described capacitor C 2 and resistance R 4 connect earth terminal.
Further, described second source connects first input end and second input of the second logical circuit by resistance R 2, can either be by the first input end of the second logical circuit and the second input clamper at high level, can play again the effect of current limliting, prevent because of the too high infringement to the second logical circuit of electric current, it is to be noted that second source is after resistance R 2, the second logical circuit and resistance R 3, the electric current producing should meet can make the 3rd logical circuit conducting, just the output output pulse signal of the 3rd logical circuit.
Further, described the 3rd power supply connects the output of the 3rd logical circuit by resistance R 5, its concrete numerical value according to output need to adjust, can by the 3rd logical circuit and output clamper at high level.
Further, described the 4th power supply connects the output of negative circuit by resistance R 6, can either provide high level to the output of negative circuit, and the effect that can play again current limliting prevents because of the too high infringement to negative circuit of electric current.
Further, described the first power supply, second source, the 3rd power supply and the 4th power supply, meet the start voltage higher than this high impulse output circuit, higher than signal input part voltage.
As a kind of optimal way of a kind of low impulse output circuit of the present invention, described delay circuit comprises by resistance R 3 and capacitor C 2 charging delay circuit in series, and the discharge lag circuit, capacitor C 2 and resistance R 4 earth terminals that are formed by capacitor C 2 and resistance R 4 parallel connections.Adopt this circuit structure, can either realize charging and discharging time delay, circuit structure is comparatively simple again simultaneously.
Further, described the second logical circuit adopts second metal-oxide-semiconductor with P raceway groove, its grid connects capacitor C 1 as input and by pull-up resistor R2 second source, drain electrode connects RC delay circuit as the second output, and source electrode connects second source as the first output; Described the 3rd logical circuit adopts has the 3rd metal-oxide-semiconductor of N raceway groove, and its grid connects delay circuit as input, its source ground end, and its drain electrode connects the 3rd power supply and as pulse output end.
Further, as the one distortion of the low impulse output circuit of the present invention, described the second logical circuit adopts PNP triode, and its base stage connects capacitor C 1 and second source as first input end, emitter connects delay circuit as output, and collector electrode connects second source as the second input; The 3rd logical circuit adopts NPN triode, its base stage is as input, grounded collector end, emitter is as output and connect the 3rd power supply, the base stage of described PNP triode is identical with the grid connected mode of the second metal-oxide-semiconductor of P raceway groove, the collector electrode of PNP triode is identical with the drain electrode connected mode of the second metal-oxide-semiconductor of P raceway groove, and the emitter of PNP triode is identical with the second metal-oxide-semiconductor source electrode connected mode of P raceway groove; The 3rd metal-oxide-semiconductor can adopt NPN triode to replace, wherein the base stage of NPN triode is identical with the grid connected mode of the 3rd metal-oxide-semiconductor of N raceway groove, the collector electrode of NPN triode is identical with the drain electrode connected mode of the 3rd metal-oxide-semiconductor of N raceway groove, and the emitter of NPN triode is identical with the 3rd metal-oxide-semiconductor source electrode connected mode of N raceway groove.
Further, as the another kind distortion of a kind of low impulse output circuit of the present invention, described the second logical circuit, the 3rd logical circuit adopts the combinational circuit with door and inverter, in the second logical circuit with the first input end of door by capacitor C 1 rear access level conversion input signal and be connected the first power supply, in the second logical circuit, be connected second source with the first input end of door, in the second logical circuit, be connected second source with the second input of door, in the second logical circuit, the output of inverter connects in the 3rd logical circuit and the input of door by delay circuit, in the 3rd logical circuit, the output of inverter connects the 3rd power supply, while is as the output of low pulse signal, adopt the circuit of this structure also can meet the demands, but Comparatively speaking, adopt metal-oxide-semiconductor circuit structure more simple, cost is lower.
Its specific works principle is: in the time that input incoming level is changed from high to low, capacitor C 1 transient switching, the grid of the second metal-oxide-semiconductor is of short duration is low level, the second metal-oxide-semiconductor conducting, second source is by the second metal-oxide-semiconductor and resistance R 3 and capacitor C 2, making the 3rd metal-oxide-semiconductor grid is high level, the 3rd metal-oxide-semiconductor conducting, the output of the 3rd metal-oxide-semiconductor is converted to low level by high level, simultaneously because capacitor C 2 stores electric charge, in charging process, capacitor C 2 forms RC series circuit with resistance R 3, the opening time of delay control three metal-oxide-semiconductors, capacitor C 1 is due to capacity effect, the second metal-oxide-semiconductor recovers cut-off state, capacitor C 2 is in parallel with resistance R 4 and discharge by resistance R 4, therefore the grid level of the 3rd metal-oxide-semiconductor is dragged down, the 3rd metal-oxide-semiconductor cut-off, the drain electrode output of the 3rd metal-oxide-semiconductor reverts to high level by low level, therefore the 3rd metal-oxide-semiconductor is output as low pulse.Wherein, in discharge process, the deadline that the discharge lag circuit that capacitor C 2 and resistance R 4 form can delay control three metal-oxide-semiconductors, by adjusting the length that the value of capacitor C 2 and resistance R 4 can the control lag time, thereby control the width of output pulse.
The present invention also provides a kind of AC electronic equipment, comprise: AC interface, the functional circuit of MCU and control thereof, and low impulse output circuit, AC interface is for external AC power supplies, described low impulse output circuit AC power supplies when AC interface is extracted for described MCU provides low pulse signal, MCU controls the mode of described functional circuit according to this low pulse signal conversion, the input of described low impulse output circuit connects AC power supplies, output connects described MCU, in the time that AC power supplies is transferred to, produce level shifted signal from high to low, from the input input of low impulse output circuit, through circuit conversion, produce low pulse signal, low pulse signal wakes the MCU in resting state up, thereby control the work of peripheral function circuit, MCU can ensure in resting state at ordinary times, save MCU resource, improve the utilance of MCU.
The present invention is by utilizing the time-delay characteristics of capacity effect and delay circuit, in conjunction with the switch feature of logical circuit, high level can be turned to the step signal that low level step signal and low level turn high level and be processed into low pulse signal, and can adjust according to the actual requirements the width of setting pulse signal by the electric capacity of delay circuit and the numerical value of resistance are set.
Brief description of the drawings
Fig. 1 is the circuit theory diagrams of the embodiment of the present invention one;
Fig. 2 is the physical circuit figure of the embodiment of the present invention one;
Fig. 3 is that the present invention adopts and door and the inverter schematic diagram as logical circuit;
Fig. 4 is the circuit theory diagrams of the embodiment of the present invention two;
Fig. 5 is the physical circuit figure of the embodiment of the present invention two;
Fig. 6 is the schematic diagram of the embodiment of the present invention three;
Fig. 7 is the schematic diagram of the embodiment of the present invention four.
Reference numeral: S1: the first power supply, S2: second source, S3: the 3rd power supply, IN: level signal input, OUT: pulse output end, C1: capacitor C 1,100: the first logical circuit, 200: the second logical circuits, 300: delay circuit, 400: the three logical circuits.
Embodiment
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Embodiment mono-
Please refer to the circuit theory diagrams of the embodiment of the present invention one shown in Fig. 1, comprise: the first logical circuit, capacitor C 1, the second logical circuit, RC delay circuit and the 3rd logical circuit, the input of described the first logical circuit is as level signal input IN incoming level switching signal, the output of the first logical circuit connects the first power supply, and the output of the first logical circuit connects the first input end of the second logical circuit by capacitor C 1, the input of the second logical circuit and the second input connect second source, and the output of the second logical circuit connects the input of the 3rd logical circuit by delay circuit, the output of the 3rd logical circuit connects the 3rd power supply, the output of the 3rd logical circuit is as pulse output end OUT, described the first power supply, second source and the 3rd power supply provide high level.
In the time that level signal input IN inputs level shifted signal from low to high, the first logical circuit conducting, capacitor C 1 transient switching, the of short duration conducting of the second logical circuit, the high level of second source input makes the 3rd logical circuit conducting after by the second logical circuit and RC delay circuit, the output output of the 3rd logical circuit transfers low level to by high level, due to the capacity effect of capacitor C 1, the second logical circuit cut-off, RC delay circuit discharges, the 3rd logical circuit cut-off, the output output of the 3rd logical circuit reverts to high level by low level, therefore the present embodiment is exported low pulse.
Please refer to the physical circuit figure of the embodiment of the present invention one shown in Fig. 2, comprise: the first logical circuit has the first metal-oxide-semiconductor of N raceway groove, the second logical circuit has the second metal-oxide-semiconductor of P raceway groove and the 3rd logical circuit and has the 3rd metal-oxide-semiconductor of N raceway groove, the source electrode of described the first metal-oxide-semiconductor connects earth terminal, drain electrode connects the first high level, the drain electrode of described the first metal-oxide-semiconductor connects the grid of the second metal-oxide-semiconductor by capacitor C 1, the drain and gate of the second metal-oxide-semiconductor connects the second high level, between the second metal-oxide-semiconductor source electrode and the 3rd metal-oxide-semiconductor grid, be connected with RC delay circuit, the source ground end of the 3rd metal-oxide-semiconductor, drain electrode connects third high level, described the 3rd metal-oxide-semiconductor drain electrode connects.
Described the first power supply connects the output of the first logical circuit by pull-up resistor R1, can either, by the output clamper of the first logical circuit at high level, can play again the effect of current limliting, prevents because of the too high infringement to the first logical circuit of electric current.
Described second source connects first input end and second input of the second logical circuit by pull-up resistor R2, can either be by the first input end of the second logical circuit and the second input clamper at high level, can play again the effect of current limliting, prevent because of the too high infringement to the second logical circuit of electric current, it is to be noted that second source is after resistance R 2, the second logical circuit and resistance R 3, the electric current producing should meet can make the 3rd logical circuit conducting, just the output output pulse signal of the 3rd logical circuit.
Described the 3rd power supply connects the output of the 3rd logical circuit by pull-up resistor R5, its concrete numerical value need to be adjusted according to output, can either by the 3rd logical circuit and output clamper at high level, can play again the effect of current limliting, prevent because of the too high infringement to the 3rd logical circuit of electric current.
Described delay circuit comprises capacitor C 2 and resistance R 3 charging delay circuit in series, in order to the conducting of delay control three metal-oxide-semiconductors; And capacitor C 2 and the resistance R 4 discharge lag circuit forming in parallel, described capacitor C 2 and resistance R 4 earth terminals, in order to the cut-off of delay control three metal-oxide-semiconductors, R4 is also as the pull down resistor of Q3, in order to the low level of the 3rd metal-oxide-semiconductor input to be provided simultaneously.
Its specific works principle is: in the time that the grid connection incoming level of the first metal-oxide-semiconductor is changed from low to high, the first metal-oxide-semiconductor conducting, capacitor C 1 transient switching, the grid of the second metal-oxide-semiconductor is of short duration is low level, the second metal-oxide-semiconductor conducting, and the second high level charges to capacitor C 2 by electric capacity R3, the ON time of delay control three metal-oxide-semiconductors, after having charged, the grid of the 3rd metal-oxide-semiconductor becomes high level, thus the 3rd metal-oxide-semiconductor conducting, and the drain electrode output of the 3rd metal-oxide-semiconductor transfers low level to by high level.Capacitor C 1 is due to capacity effect, the second metal-oxide-semiconductor recovers cut-off state, capacitor C 2 is discharged by resistance R 4, therefore the grid level of the 3rd metal-oxide-semiconductor is dragged down, the 3rd metal-oxide-semiconductor cut-off, the drain electrode output of the 3rd metal-oxide-semiconductor reverts to high level by low level, and therefore the 3rd metal-oxide-semiconductor output is exported low pulse.Wherein, in discharge process, the deadline that the discharge lag circuit that capacitor C 2 and resistance R 4 form can delay control three metal-oxide-semiconductors, by adjusting the length that the value of capacitor C 2 and resistance R 4 can the control lag time, thereby control the width of output pulse.
The time-delay characteristics of passing through to utilize capacity effect and RC delay circuit of this enforcement, in conjunction with the logical circuit feature of metal-oxide-semiconductor, the step signal that low level can be turned to high level is processed into low pulse signal, and the width of setting pulse signal according to the actual requirements.
As a distortion of the present embodiment, described the first logical circuit adopts NPN triode, and its base stage connects level shifted signal as input, grounded collector end, and emitter connects the first power supply and capacitor C 1 as output, the second logical circuit adopts PNP triode, and its base stage connects capacitor C 1 and second source as first input end, and emitter connects delay circuit as output, and collector electrode connects second source as the second input, the 3rd logical circuit adopts NPN triode, its grid is as input, its source ground end, its drain electrode is as output and connect the 3rd power supply, described in the first metal-oxide-semiconductor the 3rd metal-oxide-semiconductor, the base stage of NPN triode is identical with the grid connected mode of N-channel MOS pipe, the collector electrode of NPN triode is identical with the drain electrode connected mode of N-channel MOS pipe, the emitter of NPN triode is identical with N-channel MOS pipe source electrode connected mode, second metal-oxide-semiconductor with P raceway groove can adopt PNP triode to replace, wherein the base stage of PNP triode is identical with the grid connected mode of P channel MOS tube, the collector electrode of PNP triode is identical with the drain electrode connected mode of P channel MOS tube, the emitter of PNP triode is identical with P channel MOS tube source electrode connected mode, but consider that the resistance consumption of NPN triode is greater than the metal-oxide-semiconductor of N raceway groove, the resistance consumption of PNP triode is greater than the metal-oxide-semiconductor of P raceway groove, therefore preferably adopt the metal-oxide-semiconductor providing in the present embodiment as logical circuit.
As shown in Figure 3, as the another one distortion of the present embodiment, described the first logical circuit, the second logical circuit, the 3rd logical circuit adopts the combinational circuit with door and inverter, the first logical circuit, capacitor C 1, the second logical circuit, delay circuit and the 3rd logical circuit, in described the first logical circuit with the input incoming level switching signal of door, in the first logical circuit, the output of inverter connects the first power supply, and in the first logical circuit, the output of inverter connects in the second logical circuit and the input of door by capacitor C 1, in the second logical circuit, be connected second source with first input end and second input of door, and in the second logical circuit, the output of inverter connects in the 3rd logical circuit and the input of door by delay circuit, in the 3rd logical circuit, the output of inverter connects the 3rd power supply, in the 3rd logical circuit, the output of inverter is as pulse output end, adopt the circuit of this kind of structure also can meet the demands, but Comparatively speaking, adopt metal-oxide-semiconductor circuit structure more simple, cost is lower.
Embodiment bis-
Please refer to the circuit theory diagrams of the embodiment of the present invention two as shown in Figure 4, comprise capacitor C 1, the second logical circuit, delay circuit and the 3rd logical circuit, capacitor C 1 one end connects the first power supply, the other end connects the input of described the second logical circuit, the input of the second logical circuit and the first output connect second source, the second output of the second logical circuit connects the input of the 3rd logical circuit by RC delay circuit, the output of the 3rd logical circuit connects the 3rd power supply, and the output of the 3rd logical circuit is as pulse output end OUT.
In the time of level shifted signal from low to high of input, capacitor C 1 transient switching, the of short duration conducting of the second logical circuit, the high level of second source input makes the 3rd logical circuit conducting after by the second logical circuit and RC delay circuit, the output output of the 3rd logical circuit transfers low level to by high level, due to the capacity effect of capacitor C 1, the second logical circuit cut-off, delay circuit discharges, the 3rd logical circuit cut-off, the output output of the 3rd logical circuit reverts to high level by low level, and therefore the present embodiment is exported low pulse.
Please refer to the physical circuit figure of the embodiment of the present invention two as shown in Figure 5, wherein, the second logical circuit has the second metal-oxide-semiconductor of P raceway groove, the 3rd logical circuit has the 3rd metal-oxide-semiconductor of N raceway groove, the grid of described the second metal-oxide-semiconductor is inputted the first high level by capacitor C 1, the drain and gate of the second metal-oxide-semiconductor connects the second high level, between the source electrode of the second metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor grid, be connected with RC delay circuit, the source ground end of the 3rd metal-oxide-semiconductor, drain electrode connects third high level, and the drain electrode of the 3rd metal-oxide-semiconductor is as pulse output end OUT.
Described second source connects first input end and second input of the second logical circuit by pull-up resistor R2, can either be by the first input end of the second logical circuit and the second input clamper at high level, can play again the effect of current limliting, prevent because of the too high infringement to the second logical circuit of electric current.
Described the 3rd power supply connects the output of the 3rd logical circuit by pull-up resistor R5, its concrete numerical value need to be adjusted according to output, can either by the 3rd logical circuit and output clamper at high level, can play again the effect of current limliting, prevent because of the too high infringement to the 3rd logical circuit of electric current.
Described delay circuit comprises capacitor C 2 and resistance R 3 charging delay circuit in series, in order to the conducting of delay control three metal-oxide-semiconductors; And capacitor C 2 and the resistance R 4 discharge lag circuit forming in parallel, described capacitor C 2 and resistance R 4 earth terminals, in order to the cut-off of delay control three metal-oxide-semiconductors.
Its specific works principle is: in the time that capacitor C 1 connects incoming level and changes from low to high, capacitor C 1 transient switching, the grid of the second metal-oxide-semiconductor is of short duration is low level, the second metal-oxide-semiconductor conducting, the second high level charges to capacitor C 2 by electric capacity R3, the ON time of delay control three metal-oxide-semiconductors, and after having charged, the grid of the 3rd metal-oxide-semiconductor becomes high level, thereby the 3rd metal-oxide-semiconductor conducting, the drain electrode output of the 3rd metal-oxide-semiconductor transfers low level to by high level.Capacitor C 1 is due to capacity effect, the second metal-oxide-semiconductor recovers cut-off state, capacitor C 2 is discharged by resistance R 4, therefore the grid level of the 3rd metal-oxide-semiconductor is dragged down, the 3rd metal-oxide-semiconductor cut-off, the drain electrode output of the 3rd metal-oxide-semiconductor reverts to high level by low level, and therefore the 3rd metal-oxide-semiconductor drain electrode output is exported low pulse.Wherein, in discharge process, the deadline that the discharge lag circuit that capacitor C 2 and resistance R 4 form can delay control three metal-oxide-semiconductors, by adjusting the length that the value of capacitor C 2 and resistance R 4 can the control lag time, thereby control the width of output pulse.
The time-delay characteristics of passing through to utilize capacity effect and delay circuit of this enforcement, in conjunction with the feature of logical circuit, the step signal that low level can be turned to high level is processed into low pulse signal, and the width of setting pulse signal according to the actual requirements.
As a distortion of the present embodiment, described the second logical circuit adopts PNP triode, and its base stage connects capacitor C 1 and second source as first input end, and emitter connects delay circuit as output, and collector electrode connects second source as the second input; The 3rd logical circuit adopts NPN triode, its base stage is as input, grounded collector end, emitter is as output and connect the 3rd power supply the second metal-oxide-semiconductor the 3rd metal-oxide-semiconductor, the base stage of described PNP triode is identical with the grid connected mode of the second metal-oxide-semiconductor with P raceway groove, the collector electrode of PNP triode is identical with the source electrode connected mode of the second metal-oxide-semiconductor with P raceway groove, and the emitter of PNP triode is identical with the drain electrode connected mode of the second metal-oxide-semiconductor with P raceway groove; The base stage of described NPN triode is identical with the grid connected mode of the 3rd metal-oxide-semiconductor with N raceway groove, the collector electrode of NPN triode is identical with the source electrode connected mode of the 3rd metal-oxide-semiconductor with N raceway groove, and the emitter of NPN triode is identical with the drain electrode connected mode of the 3rd metal-oxide-semiconductor with N raceway groove.But consider that the resistance consumption of NPN triode is greater than the metal-oxide-semiconductor of N raceway groove, the resistance consumption of PNP triode is greater than the metal-oxide-semiconductor of P raceway groove, therefore preferably adopts the metal-oxide-semiconductor providing in the present embodiment as logical circuit.
As the another one distortion of the present embodiment, described the second logical circuit, the 3rd logical circuit adopts the combinational circuit with door and inverter, in the second logical circuit with the first input end of door by capacitor C 1 rear access level conversion input signal and be connected the first power supply, in the second logical circuit, be connected second source with the first input end of door, in the second logical circuit, be connected second source with the second input of door, in the second logical circuit, the output of inverter connects in the 3rd logical circuit and the input of door by delay circuit, in the 3rd logical circuit, the output of inverter connects the 3rd power supply, while is as the output of low pulse signal, adopt the circuit of this structure also can meet the demands, but Comparatively speaking, adopt metal-oxide-semiconductor circuit structure more simple, cost is lower.
Embodiment tri-
Please refer to the schematic diagram of the embodiment of the present invention three as shown in Figure 6, the signal conversion equipment that the present embodiment provides comprises that the HDMI for receiving HDMI signal and being converted into MHL signal output turns MHL system, is responsible for control and management HDMI and turns the MCU of MHL system and be responsible for MCU the low impulse output circuit of low pulse signal is provided, the input that described MCU connects connects the output of described low impulse output circuit, the control output end that described MCU connects connects described HDMI and turns MHL system, and the input of described low impulse output circuit is in order to connect HDMI cable.In the present embodiment, described low impulse output circuit adopts the circuit design shown in Fig. 2, and the course of work of the signal conversion equipment that the present embodiment provides is as follows:
When HDMI cable connects after low impulse output circuit as shown in Figure 2, after being converted to low pulse signal by described low impulse output circuit, the HDMI level signal from low to high of HDMI cable input exports, can wake the MCU in dormancy up, MCU and then management are controlled HDMI and are turned MHL system works, export after making its HDMI signal by input be converted into MHL signal;
The beneficial effect of the present embodiment: in the time not having HDMI cable to connect, pulse conversion circuit is not exported low pulse signal, and MCU keeps resting state, has saved MCU resource, has improved the utilance of MCU.
Embodiment tetra-
Please refer to the schematic diagram of the embodiment of the present invention four AC electronic equipments as shown in Figure 7, comprise the MCU of AC power supplies peripheral applications circuit and control AC power supplies peripheral applications circuit, described MCU is connected with low impulse output circuit as shown in Figure 4, in the time that AC power supplies is transferred to, AC power supplies can produce level shifted signal from high to low, through circuit conversion, after being converted to low pulse, level signal from high to low exports, wake the MCU in resting state up, the peripheral applications circuit of AC power supplies is controlled in MCU management, complete corresponding function, as equipment such as notebooks, transfer to after AC power supplies, MCU can control necessary circuitry and carry out work, inessential circuit enters resting state, reduce equipment power dissipation, extend the service time of electric weight.
The beneficial effect of the present embodiment: in the time not having AC power supplies to transfer to, pulse conversion circuit is not exported low pulse signal, MCU can keep resting state, save MCU resource, improved the utilance of MCU, simultaneously when transfering to after AC power supplies, MCU can control necessary circuitry and carry out work, inessential circuit enters resting state, has reduced equipment power dissipation, has extended the service time of electric weight.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (10)
1. a low impulse output circuit, it is characterized in that, comprise: the first logical circuit, capacitor C 1, the second logical circuit, delay circuit and the 3rd logical circuit, the input incoming level switching signal of described the first logical circuit, the output of the first logical circuit connects the first power supply, and the output of the first logical circuit connects the input of the second logical circuit by capacitor C 1, the first input end of the second logical circuit and the second input connect second source, and the output of the second logical circuit connects the input of the 3rd logical circuit by delay circuit, the output of the 3rd logical circuit connects the 3rd power supply, the output of the 3rd logical circuit is as pulse output end.
2. low impulse output circuit according to claim 1, it is characterized in that: described the first logical circuit adopts the metal-oxide-semiconductor with N raceway groove, its grid connects level shifted signal as input, source ground end, and drain electrode connects the first power supply and capacitor C 1 as output; The second logical circuit adopts the metal-oxide-semiconductor with P raceway groove, and its grid connects capacitor C 1 and second source as first input end, and drain electrode connects delay circuit as output, and source electrode connects second source as the second input; The 3rd logical circuit adopts has the metal-oxide-semiconductor of N raceway groove, and its grid is as input, its source ground end, and its drain electrode is as output and connect the 3rd power supply; Or described the first logical circuit adopts NPN triode, its base stage connects level shifted signal as input, grounded collector end, and emitter connects the first power supply and capacitor C 1 as output; The second logical circuit adopts PNP triode, and its base stage connects capacitor C 1 and second source as first input end, and emitter connects delay circuit as output, and collector electrode connects second source as the second input; The 3rd logical circuit adopts NPN triode, and its grid is as input, its source ground end, and its drain electrode is as output and connect the 3rd power supply.
3. low impulse output circuit according to claim 1, it is characterized in that: described the first logical circuit, the second logical circuit, the 3rd logical circuit adopt the combinational circuit with door and inverter, as signal input part, the output of inverter is as signal output part with the input of door.
4. according to the low impulse output circuit described in any one in claims 1 to 3, it is characterized in that: between the output of logical and the first logical circuit of described the first power supply, be connected with resistance R 1, contact resistance R3 between the first input end of described second source and the second logical circuit, contact resistance R5 between described the 3rd power supply and the output of the 3rd logical circuit, for clamper high level and restricted circulation electric current.
5. a low impulse output circuit, it is characterized in that, comprise: capacitor C 1, the second logical circuit, delay circuit and the 3rd logical circuit, capacitor C 1 one end connects the first power supply, the other end connects the first input end of described the second logical circuit, the input of the second logical circuit and the second input connect second source, the output of the second logical circuit connects the input of the 3rd logical circuit by delay circuit, the output of the 3rd logical circuit connects the 3rd power supply, and the output of the 3rd logical circuit is as pulse output end.
6. low impulse output circuit according to claim 5, it is characterized in that: described the second logical circuit adopts the metal-oxide-semiconductor with P raceway groove, its grid connects capacitor C 1 and second source as first input end, drain electrode connects delay circuit as output, and source electrode connects second source as the second input; The 3rd logical circuit adopts has the metal-oxide-semiconductor of N raceway groove, and its grid is as input, its source ground end, and its drain electrode is as output and connect the 3rd power supply; Or described the second logical circuit adopts PNP triode, its base stage connects capacitor C 1 and second source as first input end, and emitter connects delay circuit as output, and collector electrode connects second source as the second input; The 3rd logical circuit adopts NPN triode, and its base stage is as input, grounded collector end, and emitter is as output and connect the 3rd power supply.
7. low impulse output circuit according to claim 5, it is characterized in that: described the second logical circuit, the 3rd logical circuit adopt the combinational circuit with door and inverter, as signal input part, the output of inverter is as signal output part with the input of door.
8. according to the low impulse output circuit described in any one in claim 5 to 7, it is characterized in that: between the output of logical and the first logical circuit of described the first power supply, be connected with resistance R 1, contact resistance R3 between the output of described second source and the second logical circuit, contact resistance R5 between described the 3rd power supply and the output of the 3rd logical circuit, for clamper high level and restricted circulation electric current.
9. a signal conversion equipment, it is characterized in that, comprise: turn MHL system, control HDMI and turn the MCU of MHL system works and the low impulse output circuit as described in claim 1～4 any one for the HDMI that receives HDMI signal and be converted into MHL signal output, described low impulse output circuit provides low pulse signal for described MCU.
10. an AC electronic equipment, it is characterized in that, comprise: the functional circuit of AC interface, MCU and control thereof and the low impulse output circuit as described in any one in claim 5～8, AC interface is for external AC power supplies, described low impulse output circuit AC power supplies when AC interface is extracted for described MCU provides low pulse signal, MCU controls the mode of described functional circuit according to this low pulse signal conversion.
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| CN201410342199.6A CN104135271A (en) | 2014-07-17 | 2014-07-17 | Low-pulse output circuit and equipment applying low-pulse output circuit |
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| CN201410342199.6A CN104135271A (en) | 2014-07-17 | 2014-07-17 | Low-pulse output circuit and equipment applying low-pulse output circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107340846A (en) * | 2017-08-31 | 2017-11-10 | 广东虹勤通讯技术有限公司 | The logic circuit and notebook computer of a kind of power down preventing |
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Application publication date: 20141105 |