CN107231145A - Reset unit and chip - Google Patents
Reset unit and chip Download PDFInfo
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- CN107231145A CN107231145A CN201610170342.7A CN201610170342A CN107231145A CN 107231145 A CN107231145 A CN 107231145A CN 201610170342 A CN201610170342 A CN 201610170342A CN 107231145 A CN107231145 A CN 107231145A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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Abstract
The invention discloses a kind of reset unit and chip.Wherein, the reset unit includes：Reset signal charging circuit, is connected to power supply, for carrying out charging and output voltage signal after power supply electrifying；And Schmidt's buffer circuit, reset signal charging circuit is connected to, for exporting reset signal according to the threshold voltage of voltage signal and Schmidt's buffer circuit.The present invention solves reset unit in correlation technique compatible can not realize the technical problem of long resetting time in the case of circuit structure is simple.
Description
Technical field
The present invention relates to circuit field, in particular to a kind of reset unit and chip.
Background technology
As Moore's Law is deep into the work(included on sub-micrometer scale, the integrated level more and more higher of chip, one single chip
Energy module is more and more, and on-chip system SOC (System On Chip, referred to as SOC) has become integrated circuit
The trend of design.The functional units such as substantial amounts of status register and control register are there is in SOC, in power supply
When being added on chip, the state of these registers is uncertain, and these uncertain states are likely to cause system
Maloperation.In order to eliminate possible maloperation, chip can typically introduce electrification reset unit, automatic in startup power supply
Produce the initial value that reset signal carrys out refresh register.
Traditional electrification reset unit (as shown in Figure 1) can not be mutated this principle using the voltage of electric capacity, in power supply
RC paths are charged during startup, when capacitance voltage is charged to the threshold voltage of phase inverter, phase inverter reversely, passes through
The reset signal of one fixed width is produced after pulse-generating circuit.There is Railway Project in this reset unit structure：(1) it is multiple
Position signal width not enough, can not meet extensive requirement (millisecond magnitude) of the SOC systems to resetting time now.Although
Reset signal width can be widened by increasing RC value, but this also results in the big resistance area occupied of bulky capacitor simultaneously
It is excessive；(2) if the power supply electrifying time for RC time constant than if larger, the reset signal of generation
Amplitude can be smaller than supply voltage so that cause reset it is not abundant enough；(3) this structure is easily subject to power supply noise
Interference, if there is power jitter when supply voltage rises near threshold voltage, may cause multiple mistake to reset
And produce oscillator signal.
The problem of existing for conventional reset cellular construction, existing many more complicated structures are suggested, but these
Circuit introduces more auxiliary unit, and some auxiliary units even need single power supply to supply, and is solving above-mentioned ask
The complexity of reset circuit is added while topic, chip area is increased.
Compatible asking for long resetting time can not be realized in the case of circuit structure is simple for reset unit in correlation technique
Topic, not yet proposes effective solution at present.
The content of the invention
, can not at least to solve reset unit in correlation technique the embodiments of the invention provide a kind of reset unit and chip
Compatibility realizes the technical problem of long resetting time in the case of circuit structure is simple.
One side according to embodiments of the present invention there is provided a kind of reset unit, including：Reset signal charging circuit,
Power supply is connected to, for carrying out charging and output voltage signal after power supply electrifying；And Schmidt's buffer circuit, even
Reset signal charging circuit is connected to, for resetting letter according to the output of the threshold voltage of voltage signal and Schmidt's buffer circuit
Number.
Further, reset signal charging circuit includes：The first transistor, wherein, the grid of the first transistor and leakage
Pole is connected to power supply；First electric capacity, wherein, the positive electrode of the first electric capacity is connected to the source electrode of the first transistor, first
The negative electrode ground connection of electric capacity；And second electric capacity, wherein, the positive electrode of the second electric capacity is connected to power supply, the second electric capacity
Negative electrode ground connection.
Further, the first transistor is nmos pass transistor.
Further, Schmidt's buffer circuit includes：Schmitt inverter, is connected to reset signal charging circuit,
When the voltage signal of reset signal charging circuit output exceedes the threshold voltage of schmitt inverter, reverse voltage is exported；
And first phase inverter, the output end of schmitt inverter and reset unit is connected to, for defeated to schmitt inverter
The reverse voltage gone out carries out anti-phase, output reset signal.
Further, schmitt inverter includes：Second transistor, wherein, the source electrode of second transistor is connected to electricity
Source, the grid of second transistor is connected to reset signal charging circuit；Third transistor, wherein, third transistor
Source electrode is connected to the drain electrode of second transistor, and the grid of third transistor is connected to reset signal charging circuit；4th is brilliant
Body pipe, wherein, the drain electrode of the 4th transistor is connected to the drain electrode of third transistor, and the grid of the 4th transistor is connected to
Reset signal charging circuit；5th transistor, wherein, the source ground of the 5th transistor, the grid of the 5th transistor
Reset signal charging circuit is connected to, the drain electrode of the 5th transistor is connected to the source electrode of the 4th transistor；6th transistor,
Wherein, the source electrode of the 6th transistor is connected to the drain electrode of second transistor, and the grid of the 6th transistor is connected to the 4th crystalline substance
The drain electrode of body pipe, the grounded drain of the 6th transistor；And the 7th transistor, wherein, the source electrode of the 7th transistor connects
The drain electrode of the 5th transistor is connected to, the grid of the 7th transistor is connected to the drain electrode of the 4th transistor, the 7th transistor
Drain electrode is connected to power supply.
Further, the forward threshold voltage of schmitt inverter is higher than negative sense threshold voltage.
Further, the first phase inverter includes：8th transistor, wherein, the grid of the 8th transistor is connected to Shi Mi
The output end of special phase inverter, the drain electrode of the 8th transistor is connected to power supply, and the source electrode of the 8th transistor is connected to reset list
The output end of member；And the 9th transistor, wherein, the grid of the 9th transistor is connected to the output of schmitt inverter
End, the source ground of the 9th transistor, the drain electrode of the 8th transistor is connected to the output end of reset unit.
Further, reset unit also includes：Reset signal discharge circuit, wherein, reset signal discharge circuit it is defeated
Entering end is used to receive external control signal, and the first output end of reset signal discharge circuit is connected to reset signal charging electricity
Road, the second output end of reset signal discharge circuit is connected to the output end of reset unit, for being believed according to outside control
Number the output end of reset signal charging circuit and reset unit is discharged.
Further, reset signal discharge circuit includes：Second phase inverter, wherein, the input of the second phase inverter is used
In reception external control signal；Tenth transistor, wherein, the grid of the tenth transistor is connected to the defeated of the second phase inverter
Go out end, the drain electrode of the tenth transistor is connected to reset signal charging circuit, the source ground of the tenth transistor；And the
11 transistors, wherein, the grid of the 11st transistor is connected to the output end of the second phase inverter, the 11st transistor
Drain electrode be connected to the output end of reset unit, the source ground of the 11st transistor.
Another aspect according to embodiments of the present invention, additionally provides a kind of chip, and the chip includes any of the above-described kind of reset
Unit.
In embodiments of the present invention, using including the reset unit of following structure：Reset signal charging circuit, is connected to
Power supply, for carrying out charging and output voltage signal after power supply electrifying；And Schmidt's buffer circuit, it is connected to multiple
Position signal charging circuit, for exporting reset signal according to the threshold voltage of voltage signal and Schmidt's buffer circuit, leads to
The voltage threshold that Schmidt's buffer circuit is set is crossed, extension resetting time has been reached and has suppressed the mesh of the influence of power jitter
, it is achieved thereby that realizing the technique effect of longer resetting time under relatively simple circuit structure, and then solve
Reset unit compatible can not realize the technical problem of long resetting time in the case of circuit structure is simple in correlation technique.
Brief description of the drawings
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, this hair
Bright schematic description and description is used to explain the present invention, does not constitute inappropriate limitation of the present invention.In accompanying drawing
In：
Fig. 1 is the schematic diagram of the reset unit according to prior art；
Fig. 2 is the schematic diagram of reset unit according to embodiments of the present invention；
Fig. 3 is a kind of schematic diagram of alternatively reset unit according to embodiments of the present invention；
Fig. 4 is the schematic diagram of according to embodiments of the present invention another alternatively reset unit；
Fig. 5 is the schematic diagram of according to embodiments of the present invention another alternatively reset unit；
Fig. 6 is the schematic diagram of according to embodiments of the present invention another alternatively reset unit；
Fig. 7 is the functional simulation figure according to the reset unit of present example；
Fig. 8 is the functional simulation figure under being 1ms in the power supply electrifying time according to the reset unit of present example；And
Fig. 9 is the functional simulation figure of the secondary electrification reset of the reset unit according to present example.
Embodiment
In order that those skilled in the art more fully understand the present invention program, below in conjunction with the embodiment of the present invention
Accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment
The only embodiment of a present invention part, rather than whole embodiments.Based on the embodiment in the present invention, ability
The every other embodiment that domain those of ordinary skill is obtained under the premise of creative work is not made, should all belong to
The scope of protection of the invention.
It should be noted that term " first " in description and claims of this specification and above-mentioned accompanying drawing, "
Two " etc. be for distinguishing similar object, without for describing specific order or precedence.It should be appreciated that this
The data that sample is used can be exchanged in the appropriate case, so as to embodiments of the invention described herein can with except
Here the order beyond those for illustrating or describing is implemented.In addition, term " comprising " and " having " and they
Any deformation, it is intended that covering is non-exclusive to be included, for example, containing process, the side of series of steps or unit
Method, system, product or equipment are not necessarily limited to those steps clearly listed or unit, but may include unclear
It is that ground is listed or for the intrinsic other steps of these processes, method, product or equipment or unit.
There is provided a kind of embodiment of reset unit according to embodiments of the present invention.Fig. 2 is according to embodiments of the present invention
The schematic diagram of reset unit.As shown in Fig. 2 the reset unit includes：Reset signal charging circuit 10 and Schmidt are slow
Rush circuit 20.
Reset signal charging circuit 10, is connected to power supply, for carrying out charging and output voltage signal after power supply electrifying.
In embodiments of the present invention, can be stable via output after low pressure difference linear voltage regulator LDO by high-voltage power supply
Circuit inside LVPS supply reset unit.The reset signal charging circuit 10 of the embodiment of the present invention is on power supply
Carry out charging and output voltage signal after electricity, alternatively, reset signal charging circuit 10 can select RC charging circuits,
As shown in Figure 1.Preferably, in order to extend power-on reset time, the reset signal charging circuit 10 of the embodiment of the present invention
Including：The first transistor, wherein, the grid of the first transistor and drain electrode are connected to power supply；First electric capacity, wherein,
The positive electrode of first electric capacity is connected to the source electrode of the first transistor, the negative electrode ground connection of the first electric capacity；And second electric capacity,
Wherein, the positive electrode of the second electric capacity is connected to power supply, the negative electrode ground connection of the second electric capacity.
The embodiment of the present invention is illustrated below in conjunction with Fig. 3.As shown in figure 3, reset signal charging circuit 10 includes
The first transistor N7, the first electric capacity Crst and the second electric capacity Ccore, wherein, the first transistor N7 grid and leakage
Pole all meets LVPS VDDL, and source electrode connects the first electric capacity Crst positive electrode, and the first electric capacity Crst positive electrodes connect
One transistor N7 source electrode, negative electrode ground connection, the second electric capacity Ccore positive electrodes meet LVPS VDDL, negative electricity
Pole is grounded.Because the first transistor N7 employs diode connected mode, only when the second electric capacity Ccore chargings exceed
The first transistor N7 threshold voltage the first transistor N7 can just be opened, therefore power supply electrifying initial stage, only can be to second
Electric capacity Ccore charges, and when LVPS VDDL exceedes the first transistor N7 threshold voltage, passes through first crystal
Pipe N7 charges to the first electric capacity Crst, and the second electric capacity Ccore voltages can be in a slight decrease in this charging process, and this is
Because the second electric capacity Ccore positive electrode charges to the first electric capacity Crst, LVPS VDDL is sufficiently high during this,
And reset signal is effectively, therefore reset signal during this can be by system reset.In addition, the first transistor N7 clamper
Effect can cause even if the power supply electrifying time it is longer when can also produce normal reset signal.
Alternatively, the first transistor of the embodiment of the present invention is nmos pass transistor.
It should be noted that above-mentioned the first transistor N7 function can also be realized by diode.
Schmidt's buffer circuit 20, is connected to reset signal charging circuit 10, for slow according to voltage signal and Schmidt
Rush the threshold voltage output reset signal of circuit 10.
In embodiments of the present invention, the voltage signal exported in reset signal charging circuit 10 is higher than Schmidt's buffer circuit
During 20 threshold voltage, Schmidt's buffer circuit 20 is turned on, so as to change the level of reset signal.
Alternatively, Schmidt's buffer circuit 20 includes：Schmitt inverter 201, is connected to reset signal charging circuit
10, it is defeated when the voltage signal that reset signal charging circuit 10 is exported exceedes the threshold voltage of schmitt inverter 201
Go out reverse voltage；And first phase inverter 202, the output end of schmitt inverter 201 and reset unit is connected to,
Reverse voltage for being exported to schmitt inverter carries out anti-phase, output reset signal.
Preferably, the forward threshold voltage of schmitt inverter is higher than negative sense threshold voltage.Applying in the embodiment of the present invention
The forward threshold voltage of close special buffer circuit 20 is higher than negative sense threshold voltage, therefore the situation of resetting time is being significantly increased
Under, it can effectively suppress influence of the power jitter to reset.
The embodiment of the present invention is illustrated below in conjunction with Fig. 4.As shown in figure 4, Schmidt's buffer circuit 20 includes applying
The close phase inverter 202 of special phase inverter 201 and first, wherein, the first end of schmitt inverter 201 is connected to the first crystalline substance
Body pipe N7 source electrode, the second end is connected to the first phase inverter 202, three-terminal link to LVPS VDDL, first
The first end of phase inverter 202 is connected to schmitt inverter 201, and the second end is connected to LVPS VDDL, the 3rd end
For exporting reset signal RESET.Preferably, schmitt inverter 201 can be set to make it have higher forward direction
Threshold voltage and relatively low negative sense threshold voltage, when node T voltage exceedes the positive threshold of schmitt inverter 201
Schmitt inverter 201 exports anti-phase during voltage, therefore higher forward threshold voltage can postpone Schmidt's buffering electricity
Road 20 exports the anti-phase time, is favorably improved resetting time, and relatively low negative sense threshold voltage then can be to a certain degree
The power jitter occurred in upper suppression power up.
Alternatively, schmitt inverter includes：Second transistor, wherein, the source electrode of second transistor is connected to power supply,
The grid of second transistor is connected to reset signal charging circuit；Third transistor, wherein, the source electrode of third transistor
The drain electrode of second transistor is connected to, the grid of third transistor is connected to reset signal charging circuit；4th transistor,
Wherein, the drain electrode of the 4th transistor is connected to the drain electrode of third transistor, and the grid of the 4th transistor is connected to reset letter
Number charging circuit；5th transistor, wherein, the source ground of the 5th transistor, the grid of the 5th transistor is connected to
Reset signal charging circuit, the drain electrode of the 5th transistor is connected to the source electrode of the 4th transistor；6th transistor, wherein,
The source electrode of 6th transistor is connected to the drain electrode of second transistor, and the grid of the 6th transistor is connected to the 4th transistor
Drain electrode, the grounded drain of the 6th transistor；And the 7th transistor, wherein, the source electrode of the 7th transistor is connected to
The drain electrode of five transistors, the grid of the 7th transistor is connected to the drain electrode of the 4th transistor, and the drain electrode of the 7th transistor connects
It is connected to power supply.
The embodiment of the present invention is illustrated below in conjunction with Fig. 5.As shown in figure 5, schmitt inverter includes the second crystalline substance
Body pipe P1, third transistor P2, the 4th transistor N1, the 5th transistor N2, the 6th transistor P3 and the 7th crystal
Pipe N3.Second transistor P1 source electrodes meet LVPS VDDL, and grid connects the first transistor N7 source electrode, and drain electrode connects
Third transistor P2 source electrode.Third transistor P2 source electrode connects second transistor P1 drain electrode, and it is brilliant that grid connects first
Body pipe N7 source electrode, drain electrode connects the 4th transistor N1 drain electrode.4th transistor N1 source electrodes meet the 5th transistor N2
Drain electrode, grid connects the first transistor N7 source electrode, and drain electrode connects third transistor P2 drain electrode.5th transistor N2
Source ground, grid connects the first transistor N7 source electrode, and drain electrode connects the 4th transistor N1 source electrode.7th crystal
Pipe N3 source electrode connects the 5th transistor N2 drain electrode, and grid connects the 4th transistor N1 drain electrode, and drain electrode connects low-voltage electricity
Source VDDL.6th transistor P3 source electrode connects second transistor P1 drain electrode, and grid connects the 4th transistor N1 leakage
Pole, grounded drain.
Alternatively, the first phase inverter includes：8th transistor, wherein, the grid of the 8th transistor is connected to Schmidt
The output end of phase inverter, the drain electrode of the 8th transistor is connected to power supply, and the source electrode of the 8th transistor is connected to reset unit
Output end；And the 9th transistor, wherein, the grid of the 9th transistor is connected to the output end of schmitt inverter,
The source ground of 9th transistor, the drain electrode of the 8th transistor is connected to the output end of reset unit.
As shown in figure 5, the first phase inverter includes the 8th transistor P4 and the 9th transistor N4.9th transistor N4's
Source ground, grid connects the 4th transistor N1 drain electrode, and drain electrode connects the output end of reset unit to export reset signal
RESET.8th crystal P4 source electrode meets VDDL, and grid connects the 4th transistor N1 drain electrode, and drain electrode connects RESET letters
Number.
In embodiments of the present invention, using including the reset unit of following structure：Reset signal charging circuit, is connected to
Power supply, for carrying out charging and output voltage signal after power supply electrifying；And Schmidt's buffer circuit, it is connected to multiple
Position signal charging circuit, for exporting reset signal according to the threshold voltage of voltage signal and Schmidt's buffer circuit, leads to
The voltage threshold that Schmidt's buffer circuit is set is crossed, extension resetting time has been reached and has suppressed the mesh of the influence of power jitter
, it is achieved thereby that realizing the technique effect of longer resetting time under relatively simple circuit structure, and then solve
Reset unit compatible can not realize the technical problem of long resetting time in the case of circuit structure is simple in correlation technique.
Alternatively, reset unit also includes：Reset signal discharge circuit, wherein, the input of reset signal discharge circuit
Hold for receiving external control signal, the first output end of reset signal discharge circuit is connected to reset signal charging circuit,
Second output end of reset signal discharge circuit is connected to the output end of reset unit, for according to external control signal pair
The output end of reset signal charging circuit and reset unit is discharged.
Alternatively, reset signal discharge circuit includes：Second phase inverter, wherein, the input of the second phase inverter is used for
Receive external control signal；Tenth transistor, wherein, the grid of the tenth transistor is connected to the output of the second phase inverter
End, the drain electrode of the tenth transistor is connected to reset signal charging circuit, the source ground of the tenth transistor；And the tenth
One transistor, wherein, the grid of the 11st transistor is connected to the output end of the second phase inverter, the 11st transistor
Drain electrode is connected to the output end of reset unit, the source ground of the 11st transistor.
The embodiment of the present invention is illustrated below in conjunction with Fig. 6.As shown in fig. 6, reset signal discharge circuit includes the
Two phase inverter INV1, the tenth transistor N5 and the 11st transistor N6.Second phase inverter INV1 input connects enable letter
Number ENABLE, exports the tenth transistor N5 and the 11st transistor N6 grid end, power supply termination high-voltage power supply VDDH.
Tenth transistor N5 source ground connection, grid end connects the second phase inverter INV1 output end, and drain terminal meets the first transistor N7
Source.11st transistor N6 source ground connection, grid end connects the second phase inverter INV1 output end, and drain terminal connects multiple
Position signal RESET output end.
Preferably, the low pressure difference linear voltage regulator LDO power down of the embodiment of the present invention is controlled by enable signal ENABLE, because
Also the electric discharge of reset signal is controlled during this power down by enable signal ENABLE.When enable signal ENABLE jump to it is low
During level, the first electric capacity Crst and reset signal RESET are dragged down by the tenth transistor N5 and the 11st transistor N6
To low level, in case secondary electrification reset fails.
The embodiment of the present invention is described in detail below in conjunction with Fig. 6.
The reset unit of the embodiment of the present invention is put including reset signal charging circuit, Schmidt's buffer circuit and reset signal
Circuit.
Reset signal charging circuit includes the first transistor N7, the first electric capacity Crst and the second electric capacity Ccore, wherein,
The first transistor N7 grid and drain electrode all meet LVPS VDDL, and source electrode connects the first electric capacity Crst positive electrode,
First electric capacity Crst positive electrodes connect the first transistor N7 source electrode, negative electrode ground connection, the second electric capacity Ccore positive electrodes
Meet LVPS VDDL, negative electrode ground connection.
Schmidt's buffer circuit includes schmitt inverter and the first phase inverter, wherein, schmitt inverter includes second
Transistor P1, third transistor P2, the 4th transistor N1, the 5th transistor N2, the 6th transistor P3 and the 7th are brilliant
Body pipe N3.Second transistor P1 source electrodes meet LVPS VDDL, and grid connects the first transistor N7 source electrode, drain electrode
Connect third transistor P2 source electrode.Third transistor P2 source electrode connects second transistor P1 drain electrode, and grid connects first
Transistor N7 source electrode, drain electrode connects the 4th transistor N1 drain electrode.4th transistor N1 source electrodes connect the 5th transistor
N2 drain electrode, grid connects the first transistor N7 source electrode, and drain electrode connects third transistor P2 drain electrode.5th transistor
N2 source ground, grid connects the first transistor N7 source electrode, and drain electrode connects the 4th transistor N1 source electrode.7th is brilliant
Body pipe N3 source electrode connects the 5th transistor N2 drain electrode, and grid connects the 4th transistor N1 drain electrode, and drain electrode connects low-voltage
Power vd DL.6th transistor P3 source electrode connects second transistor P1 drain electrode, and grid connects the 4th transistor N1's
Drain electrode, grounded drain.First phase inverter includes the 8th transistor P4 and the 9th transistor N4.9th transistor N4's
Source ground, grid connects the 4th transistor N1 drain electrode, and drain electrode connects the output end of reset unit to export reset signal
RESET.8th crystal P4 source electrode meets VDDL, and grid connects the 4th transistor N1 drain electrode, and drain electrode connects RESET letters
Number.
Reset signal discharge circuit includes the second phase inverter INV1, the tenth transistor N5 and the 11st transistor N6.The
Two phase inverter INV1 input termination enables signal ENABLE, output the tenth transistor N5 of termination and the 11st transistor
N6 grid, power supply termination high-voltage power supply VDDH.Tenth transistor N5 source ground, it is anti-phase that grid connects second
Device INV1 output end, drain electrode connects the first transistor N7 source electrode.11st transistor N6 source ground, grid
The second phase inverter INV1 output end is connect, drain electrode connects reset signal RESET output end.
In embodiments of the present invention, the first transistor N7 employs diode connected mode, only as the second electric capacity Ccore
Charging can just be opened more than the first transistor N7 threshold voltage the first transistor N7, therefore power supply electrifying initial stage, only
Second electric capacity Ccore can be charged, when LVPS VDDL exceedes the first transistor N7 threshold voltage, passed through
The first transistor N7 charges to the first electric capacity Crst, and the second electric capacity Ccore voltages can slightly drop in this charging process
It is low (be less than 50mV), low during this because the second electric capacity Ccore positive electrode charges to the first electric capacity Crst
Voltage source VDDL is sufficiently high, and reset signal is effectively, therefore the reset signal during this can such as scheme system reset
Shown in 7.
The first transistor N7 clamping action can cause even if the power supply electrifying time it is longer when can also produce it is normal multiple
Position signal, as shown in figure 8, the power supply electrifying time is 1ms.Can be by adjusting capacitance size so that first crystal
Pipe N7 has that one section of period the second electric capacity Ccore voltage is slightly reduced after opening and the first electric capacity Crst voltages slowly rise.
Suitable forward threshold voltage is obtained additionally by the transistor parameter of adjustment schmitt inverter, when node T voltage
When being raised and lowered into certain voltage respectively with LVPS VDDL voltage, schmitt inverter can be triggered and redirected,
So that the output of Schmidt's buffer circuit is anti-phase.
Table 1 shows influence of the different capacitance sizes to final resetting time, it is known that just can be with using very small electric capacity
Obtain relatively long resetting time.Different magnitude of capacitance can be selected according to requirement of the system to resetting time.
Table 2 shows the reset unit that the embodiment of the present invention proposes and traditional reset unit (reset unit shown in Fig. 1)
The comparison of resetting time, it is known that the reset unit of the embodiment of the present invention greatly improves resetting time.
Table 1
| Capacitance size | 1pF | 10pF | 100pF | 1nF | 10nF |
| Resetting time | 55us | 530us | 5.3ms | 52ms | 530ms |
Table 2
| Existing reset unit (R=100K) | The reset unit of the embodiment of the present invention | |
| Resetting time | 85us | 52ms |
In embodiments of the present invention, the forward threshold voltage of Schmidt's buffer circuit is higher than negative sense threshold voltage, works as node
Schmitt inverter output is anti-phase therefore higher just when T voltage exceedes the forward threshold voltage of schmitt inverter
It can postpone Schmidt's buffer circuit to threshold voltage and export the anti-phase time, be favorably improved resetting time, and it is relatively low
Negative sense threshold voltage can then suppress the power jitter occurred in power up to a certain extent.It is multiple additionally by adjustment
Capacitance in the signal charging circuit of position, can allow LVPS VDDL to be soon stabilized to more than 1.15V.
In embodiments of the present invention, low pressure difference linear voltage regulator LDO power down is controlled by enable signal ENABLE, therefore is fallen
Also the electric discharge of reset signal is controlled when electric by enable signal ENABLE.Low level is jumped to when enabling signal ENABLE
When, the first electric capacity Crst and reset signal RESET are pulled down to by the tenth transistor N5 and the 11st transistor N6 low
Level, in case secondary electrification reset fails, as shown in Figure 9.
Seen from the above description, the embodiment of the invention discloses a kind of simple and reliable reset unit, it has longer
It is resetting time, longer or in the case that upper power supply has certain shake even in power-on time, still it can keep
Normal errorless operation, it is adaptable to system level chip (i.e. SOC).The function of whole reset unit is in SoC systems
When electric, low effective reset signal longer for a period of time is produced, SoC systems is started working from reset state, from
And reach electric automatically reset function.The reset circuit simple possible of the embodiment of the present invention, using only 13 crystal
Resetting time is greatly improved in the case of pipe and 2 electric capacity, and by setting schmitt inverter, in certain journey
Contribute to the inhibitory action to power jitter on degree, the nmos pass transistor for employing diode connected mode carries out charging pincers
Position, even if the power supply electrifying time is relatively long, also can guarantee that the amplitude of reset signal reaches normal size, by resetting
Signal discharge circuit has ensured discharge channel during power down well, efficiently avoid secondary electrification reset failure.
According to further embodiment of this invention there is provided a kind of chip, the chip includes above-mentioned reset unit.
The embodiments of the present invention are for illustration only, and the quality of embodiment is not represented.
In the above embodiment of the present invention, the description to each embodiment all emphasizes particularly on different fields, and does not have in some embodiment
The part of detailed description, may refer to the associated description of other embodiment.
, can be by other in several embodiments provided herein, it should be understood that disclosed technology contents
Mode realize.Wherein, device embodiment described above is only schematical, such as division of described unit,
It can be a kind of division of logic function, can have other dividing mode when actually realizing, such as multiple units or component
Another system can be combined or be desirably integrated into, or some features can be ignored, or do not perform.It is another, institute
Display or the coupling each other discussed or direct-coupling or communication connection can be by some interfaces, unit or mould
The INDIRECT COUPLING of block or communication connection, can be electrical or other forms.
The unit illustrated as separating component can be or may not be it is physically separate, it is aobvious as unit
The part shown can be or may not be physical location, you can with positioned at a place, or can also be distributed to
On multiple units.Some or all of unit therein can be selected to realize this embodiment scheme according to the actual needs
Purpose.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improve and moistened
Decorations also should be regarded as protection scope of the present invention.
Claims (10)
1. a kind of reset unit, it is characterised in that including：
Reset signal charging circuit, is connected to power supply, for electricity to be charged and exported after the power supply electrifying
Press signal；And
Schmidt's buffer circuit, is connected to the reset signal charging circuit, for according to the voltage signal and
The threshold voltage output reset signal of Schmidt's buffer circuit.
2. reset unit according to claim 1, it is characterised in that the reset signal charging circuit includes：
The first transistor, wherein, the grid of the first transistor and drain electrode are connected to the power supply；
First electric capacity, wherein, the positive electrode of first electric capacity is connected to the source electrode of the first transistor, institute
State the negative electrode ground connection of the first electric capacity；And
Second electric capacity, wherein, the positive electrode of second electric capacity is connected to the power supply, second electric capacity
Negative electrode is grounded.
3. reset unit according to claim 2, it is characterised in that the first transistor is nmos pass transistor.
4. reset unit according to claim 1 or 2, it is characterised in that Schmidt's buffer circuit includes：
Schmitt inverter, is connected to the reset signal charging circuit, defeated in the reset signal charging circuit
When the voltage signal gone out exceedes the threshold voltage of the schmitt inverter, reverse voltage is exported；And
First phase inverter, is connected to the output end of the schmitt inverter and the reset unit, for institute
The reverse voltage for stating schmitt inverter output carries out anti-phase, the output reset signal.
5. reset unit according to claim 4, it is characterised in that the schmitt inverter includes：
Second transistor, wherein, the source electrode of the second transistor is connected to the power supply, second crystal
The grid of pipe is connected to the reset signal charging circuit；
Third transistor, wherein, the source electrode of the third transistor is connected to the drain electrode of the second transistor,
The grid of the third transistor is connected to the reset signal charging circuit；
4th transistor, wherein, the drain electrode of the 4th transistor is connected to the drain electrode of the third transistor,
The grid of 4th transistor is connected to the reset signal charging circuit；
5th transistor, wherein, the source ground of the 5th transistor, the grid of the 5th transistor connects
The reset signal charging circuit is connected to, the drain electrode of the 5th transistor is connected to the source of the 4th transistor
Pole；
6th transistor, wherein, the source electrode of the 6th transistor is connected to the drain electrode of the second transistor,
The grid of 6th transistor is connected to the drain electrode of the 4th transistor, and the drain electrode of the 6th transistor connects
Ground；And
7th transistor, wherein, the source electrode of the 7th transistor is connected to the drain electrode of the 5th transistor,
The grid of 7th transistor is connected to the drain electrode of the 4th transistor, and the drain electrode of the 7th transistor connects
It is connected to the power supply.
6. reset unit according to claim 5, it is characterised in that the positive threshold electricity of the schmitt inverter
Pressure is higher than negative sense threshold voltage.
7. reset unit according to claim 4, it is characterised in that first phase inverter includes：
8th transistor, wherein, the grid of the 8th transistor is connected to the output of the schmitt inverter
End, the drain electrode of the 8th transistor is connected to the power supply, and the source electrode of the 8th transistor is connected to described
The output end of reset unit；And
9th transistor, wherein, the grid of the 9th transistor is connected to the output of the schmitt inverter
End, the source ground of the 9th transistor, the drain electrode of the 8th transistor is connected to the reset unit
Output end.
8. reset unit according to claim 1 or 2, it is characterised in that the reset unit also includes：Reset
Signal discharge circuit, wherein, the input of the reset signal discharge circuit is used to receive external control signal,
First output end of the reset signal discharge circuit is connected to the reset signal charging circuit, the reset letter
Second output end of number discharge circuit is connected to the output end of the reset unit, for outside being controlled according to described
Signal discharges the output end of the reset signal charging circuit and the reset unit.
9. reset unit according to claim 8, it is characterised in that the reset signal discharge circuit includes：
Second phase inverter, wherein, the input of second phase inverter is used to receive the external control signal；
Tenth transistor, wherein, the grid of the tenth transistor is connected to the output end of second phase inverter,
The drain electrode of tenth transistor is connected to the reset signal charging circuit, and the source electrode of the tenth transistor connects
Ground；And
11st transistor, wherein, the grid of the 11st transistor is connected to the defeated of second phase inverter
Go out end, the drain electrode of the 11st transistor is connected to the output end of the reset unit, the 11st crystal
The source ground of pipe.
10. a kind of chip, it is characterised in that including the reset unit any one of claim 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610170342.7A CN107231145B (en) | 2016-03-23 | 2016-03-23 | Reset unit and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610170342.7A CN107231145B (en) | 2016-03-23 | 2016-03-23 | Reset unit and chip |
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| Publication Number | Publication Date |
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| CN107231145A true CN107231145A (en) | 2017-10-03 |
| CN107231145B CN107231145B (en) | 2020-10-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610170342.7A Active CN107231145B (en) | 2016-03-23 | 2016-03-23 | Reset unit and chip |
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|---|---|
| CN (1) | CN107231145B (en) |
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| CN112204884A (en) * | 2018-05-31 | 2021-01-08 | 华为技术有限公司 | Power-on reset circuit and isolated half-bridge driver |
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| CN112204884A (en) * | 2018-05-31 | 2021-01-08 | 华为技术有限公司 | Power-on reset circuit and isolated half-bridge driver |
| CN112204884B (en) * | 2018-05-31 | 2024-04-26 | 华为技术有限公司 | Power-on reset circuit and isolated half-bridge driver |
| CN112260663A (en) * | 2020-11-11 | 2021-01-22 | 北京中科芯蕊科技有限公司 | Sub-threshold pulse broadening circuit |
| CN112260663B (en) * | 2020-11-11 | 2023-06-30 | 北京中科芯蕊科技有限公司 | Subthreshold pulse stretching circuit |
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|---|---|
| CN107231145B (en) | 2020-10-27 |
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