CN107231145B - Reset unit and chip - Google Patents
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- CN107231145B CN107231145B CN201610170342.7A CN201610170342A CN107231145B CN 107231145 B CN107231145 B CN 107231145B CN 201610170342 A CN201610170342 A CN 201610170342A CN 107231145 B CN107231145 B CN 107231145B
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Abstract
The invention discloses a reset unit and a chip. Wherein, this reset unit includes: the reset signal charging circuit is connected to the power supply and is used for charging and outputting a voltage signal after the power supply is electrified; and the Schmitt buffer circuit is connected to the reset signal charging circuit and used for outputting the reset signal according to the voltage signal and the threshold voltage of the Schmitt buffer circuit. The invention solves the technical problem that the reset unit in the related technology can not be compatible with the circuit structure to realize long reset time.
Description
Technical Field
The invention relates to the field of circuits, in particular to a reset unit and a chip.
Background
As moore's law deepens into submicron order, the integration level of chips is higher and higher, more and more functional modules are included On a single Chip, and System On Chip (SOC) has become a trend of integrated circuit design. There are a large number of functional units such as a status register and a control register in the SOC chip, and when power is applied to the chip, the status of these registers is uncertain, and these uncertain states are likely to cause malfunction of the system. To eliminate possible malfunction, the chip typically incorporates a power-on reset unit that automatically generates a reset signal to refresh the initial value of the register when power is turned on.
The conventional power-on reset unit (as shown in fig. 1) charges an RC path when a power supply is started by using the principle that the voltage of a capacitor cannot change suddenly, and when the voltage of the capacitor is charged to the threshold voltage of an inverter, the inverter reverses, and a reset signal with a certain width is generated after passing through a pulse generation circuit. This reset cell structure has several problems: (1) the width of the reset signal is not enough, and the requirement (millisecond magnitude) of the reset time of the existing large-scale SOC system cannot be met. Although the reset signal width can be widened by increasing the value of RC, this also causes the occupation area of the large capacitor and the large resistor to be too large; (2) if the power-on time of the power supply is larger than the time constant of the RC, the amplitude of the generated reset signal is smaller than the power supply voltage, so that the reset is insufficient; (3) this structure is easily subject to power supply noise, and if there is power supply jitter when the power supply voltage rises to near the threshold voltage, it may cause multiple false resets and generate an oscillation signal.
Many more complex structures have been proposed to solve the problems of the conventional reset unit structure, but these circuits introduce more auxiliary units, and some auxiliary units even need separate power supply, so that the complexity of the reset circuit is increased while the above problems are solved, and the chip area is increased.
Aiming at the problem that the reset unit in the related art cannot be compatible with the long reset time under the condition of simple circuit structure, no effective solution is provided at present.
Disclosure of Invention
The embodiment of the invention provides a reset unit and a chip, which at least solve the technical problem that the reset unit in the related technology cannot be compatible with the technology of realizing long reset time under the condition of simple circuit structure.
According to an aspect of an embodiment of the present invention, there is provided a reset unit including: the reset signal charging circuit is connected to the power supply and is used for charging and outputting a voltage signal after the power supply is electrified; and the Schmitt buffer circuit is connected to the reset signal charging circuit and used for outputting the reset signal according to the voltage signal and the threshold voltage of the Schmitt buffer circuit.
Further, the reset signal charging circuit includes: a first transistor, wherein a gate and a drain of the first transistor are connected to a power supply; a first capacitor, wherein the positive electrode of the first capacitor is connected to the source of the first transistor, and the negative electrode of the first capacitor is grounded; and a second capacitor, wherein the positive electrode of the second capacitor is connected to the power supply, and the negative electrode of the second capacitor is grounded.
Further, the first transistor is an NMOS transistor.
Further, the schmitt buffer circuit includes: the Schmitt inverter is connected to the reset signal charging circuit and outputs an inverted voltage when a voltage signal output by the reset signal charging circuit exceeds a threshold voltage of the Schmitt inverter; and the first inverter is connected to the output ends of the Schmitt inverter and the reset unit and is used for inverting the inverted voltage output by the Schmitt inverter and outputting a reset signal.
Further, the schmitt inverter includes: a second transistor, wherein a source of the second transistor is connected to a power supply, and a gate of the second transistor is connected to the reset signal charging circuit; a third transistor, wherein a source of the third transistor is connected to a drain of the second transistor, and a gate of the third transistor is connected to the reset signal charging circuit; a fourth transistor, wherein a drain of the fourth transistor is connected to a drain of the third transistor, and a gate of the fourth transistor is connected to the reset signal charging circuit; a fifth transistor, wherein a source of the fifth transistor is grounded, a gate of the fifth transistor is connected to the reset signal charging circuit, and a drain of the fifth transistor is connected to a source of the fourth transistor; a sixth transistor, wherein a source of the sixth transistor is connected to the drain of the second transistor, a gate of the sixth transistor is connected to the drain of the fourth transistor, and a drain of the sixth transistor is grounded; and a seventh transistor, wherein a source of the seventh transistor is connected to a drain of the fifth transistor, a gate of the seventh transistor is connected to a drain of the fourth transistor, and a drain of the seventh transistor is connected to the power supply.
Further, the schmitt inverter has a positive threshold voltage higher than a negative threshold voltage.
Further, the first inverter includes: a gate of the eighth transistor is connected to the output terminal of the schmitt inverter, a drain of the eighth transistor is connected to the power supply, and a source of the eighth transistor is connected to the output terminal of the reset unit; and a ninth transistor, wherein a gate of the ninth transistor is connected to an output terminal of the schmitt inverter, a source of the ninth transistor is grounded, and a drain of the eighth transistor is connected to an output terminal of the reset unit.
Further, the reset unit further includes: the reset signal discharge circuit, wherein, reset signal discharge circuit's input is used for receiving external control signal, and reset signal discharge circuit's first output is connected to reset signal charging circuit, and reset signal discharge circuit's second output is connected to the output of reset unit for discharge the output of reset signal charging circuit and reset unit according to external control signal.
Further, the reset signal discharge circuit includes: the input end of the second inverter is used for receiving an external control signal; a tenth transistor, wherein a gate of the tenth transistor is connected to the output terminal of the second inverter, a drain of the tenth transistor is connected to the reset signal charging circuit, and a source of the tenth transistor is grounded; and an eleventh transistor, wherein a gate of the eleventh transistor is connected to the output terminal of the second inverter, a drain of the eleventh transistor is connected to the output terminal of the reset unit, and a source of the eleventh transistor is grounded.
According to another aspect of the embodiments of the present invention, there is also provided a chip including any one of the reset units described above.
In the embodiment of the present invention, a reset unit including the following structure is adopted: the reset signal charging circuit is connected to the power supply and is used for charging and outputting a voltage signal after the power supply is electrified; and the Schmitt buffer circuit is connected to the reset signal charging circuit and used for outputting a reset signal according to the voltage signal and the threshold voltage of the Schmitt buffer circuit, and the purposes of prolonging the reset time and inhibiting the influence of power supply jitter are achieved by setting the voltage threshold of the Schmitt buffer circuit, so that the technical effect of realizing longer reset time under a simpler circuit structure is realized, and the technical problem that the reset unit cannot be compatible to realize long reset time under the condition of simple circuit structure in the related technology is solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a schematic diagram of a reset unit according to the prior art;
FIG. 2 is a schematic diagram of a reset unit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an alternative reset unit in accordance with an embodiment of the present invention;
FIG. 4 is a schematic diagram of yet another alternative reset unit in accordance with an embodiment of the present invention;
FIG. 5 is a schematic diagram of yet another alternative reset unit in accordance with an embodiment of the present invention;
FIG. 6 is a schematic diagram of yet another alternative reset unit in accordance with an embodiment of the present invention;
FIG. 7 is a functional simulation diagram of a reset unit according to an example of the present invention;
FIG. 8 is a functional simulation diagram of a reset unit according to an example of the present invention at a power-on time of 1 ms; and
fig. 9 is a functional simulation diagram of a secondary power-on reset of a reset unit according to an example of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
According to an embodiment of the present invention, an embodiment of a reset unit is provided. Fig. 2 is a schematic diagram of a reset unit according to an embodiment of the present invention. As shown in fig. 2, the reset unit includes: a reset signal charging circuit 10 and a schmitt buffer circuit 20.
And the reset signal charging circuit 10 is connected to the power supply and is used for charging and outputting a voltage signal after the power supply is powered on.
In the embodiment of the invention, a high-voltage power supply can output a stable low-voltage power supply to the circuit inside the reset unit after passing through the low dropout regulator LDO. The reset signal charging circuit 10 according to the embodiment of the present invention charges and outputs a voltage signal after the power supply is powered on, and optionally, the reset signal charging circuit 10 may be an RC charging circuit, as shown in fig. 1. Preferably, in order to extend the power-on reset time, the reset signal charging circuit 10 of the embodiment of the present invention includes: a first transistor, wherein a gate and a drain of the first transistor are connected to a power supply; a first capacitor, wherein the positive electrode of the first capacitor is connected to the source of the first transistor, and the negative electrode of the first capacitor is grounded; and a second capacitor, wherein the positive electrode of the second capacitor is connected to the power supply, and the negative electrode of the second capacitor is grounded.
An embodiment of the present invention will be described below with reference to fig. 3. As shown in fig. 3, the reset signal charging circuit 10 includes a first transistor N7, a first capacitor Crst, and a second capacitor Ccore, wherein the gate and the drain of the first transistor N7 are both connected to a low voltage power supply VDDL, the source is connected to the positive electrode of the first capacitor Crst, the positive electrode of the first capacitor Crst is connected to the source of the first transistor N7, the negative electrode is grounded, the positive electrode of the second capacitor Ccore is connected to the low voltage power supply VDDL, and the negative electrode is grounded. Since the first transistor N7 is diode-connected, the first transistor N7 is turned on only when the second capacitor Ccore is charged above the threshold voltage of the first transistor N7, so that only the second capacitor Ccore is charged during the power-up period, and when the low voltage power supply VDDL exceeds the threshold voltage of the first transistor N7, the first capacitor Crst is charged through the first transistor N7, and the voltage of the second capacitor Ccore is slightly decreased during this charging process, because the positive electrode of the second capacitor Ccore charges the first capacitor Crst, during which the low voltage power supply VDDL is high enough and the reset signal is active, so that the system is reset by the reset signal during this period. In addition, the clamping action of the first transistor N7 may enable a normal reset signal to be generated even when the power supply is powered on for a long time.
Optionally, the first transistor in the embodiment of the present invention is an NMOS transistor.
Note that the function of the first transistor N7 may be realized by a diode.
And the Schmitt buffer circuit 20 is connected to the reset signal charging circuit 10 and is used for outputting a reset signal according to the voltage signal and the threshold voltage of the Schmitt buffer circuit 10.
In the embodiment of the present invention, when the voltage signal output from the reset signal charging circuit 10 is higher than the threshold voltage of the schmitt buffer circuit 20, the schmitt buffer circuit 20 is turned on, so that the level of the reset signal can be changed.
Optionally, the schmitt buffer circuit 20 includes: a schmitt inverter 201 connected to the reset signal charging circuit 10, and outputting an inverted voltage when a voltage signal output from the reset signal charging circuit 10 exceeds a threshold voltage of the schmitt inverter 201; and a first inverter 202 connected to the output ends of the schmitt inverter 201 and the reset unit, for inverting the inverted voltage output from the schmitt inverter and outputting a reset signal.
Preferably, the schmitt inverter has a positive threshold voltage higher than a negative threshold voltage. The schmitt buffer circuit 20 in the embodiment of the present invention has a higher positive threshold voltage than a negative threshold voltage, so that the influence of power jitter on the reset can be effectively suppressed under the condition of greatly increasing the reset time.
An embodiment of the present invention will be described below with reference to fig. 4. As shown in fig. 4, the schmitt buffer circuit 20 includes a schmitt inverter 201 and a first inverter 202, wherein a first terminal of the schmitt inverter 201 is connected to the source of the first transistor N7, a second terminal is connected to the first inverter 202, a third terminal is connected to the low voltage power supply VDDL, a first terminal of the first inverter 202 is connected to the schmitt inverter 201, a second terminal is connected to the low voltage power supply VDDL, and the third terminal is used for outputting the RESET signal RESET. Preferably, the schmitt inverter 201 may be configured to have a higher positive threshold voltage and a lower negative threshold voltage, and when the voltage of the node T exceeds the positive threshold voltage of the schmitt inverter 201, the schmitt inverter 201 outputs an inverted phase, so that the higher positive threshold voltage may delay the output inverted phase of the schmitt buffer circuit 20, which helps to improve the reset time, and the lower negative threshold voltage may suppress the power jitter occurring during the power-on process to some extent.
Optionally, the schmitt inverter includes: a second transistor, wherein a source of the second transistor is connected to a power supply, and a gate of the second transistor is connected to the reset signal charging circuit; a third transistor, wherein a source of the third transistor is connected to a drain of the second transistor, and a gate of the third transistor is connected to the reset signal charging circuit; a fourth transistor, wherein a drain of the fourth transistor is connected to a drain of the third transistor, and a gate of the fourth transistor is connected to the reset signal charging circuit; a fifth transistor, wherein a source of the fifth transistor is grounded, a gate of the fifth transistor is connected to the reset signal charging circuit, and a drain of the fifth transistor is connected to a source of the fourth transistor; a sixth transistor, wherein a source of the sixth transistor is connected to the drain of the second transistor, a gate of the sixth transistor is connected to the drain of the fourth transistor, and a drain of the sixth transistor is grounded; and a seventh transistor, wherein a source of the seventh transistor is connected to a drain of the fifth transistor, a gate of the seventh transistor is connected to a drain of the fourth transistor, and a drain of the seventh transistor is connected to the power supply.
An embodiment of the present invention will be described below with reference to fig. 5. As shown in fig. 5, the schmitt inverter includes a second transistor P1, a third transistor P2, a fourth transistor N1, a fifth transistor N2, a sixth transistor P3, and a seventh transistor N3. The source of the second transistor P1 is connected to the low voltage power supply VDDL, the gate is connected to the source of the first transistor N7, and the drain is connected to the source of the third transistor P2. The source of the third transistor P2 is connected to the drain of the second transistor P1, the gate is connected to the source of the first transistor N7, and the drain is connected to the drain of the fourth transistor N1. The source of the fourth transistor N1 is connected to the drain of the fifth transistor N2, the gate is connected to the source of the first transistor N7, and the drain is connected to the drain of the third transistor P2. The source of the fifth transistor N2 is grounded, the gate is connected to the source of the first transistor N7, and the drain is connected to the source of the fourth transistor N1. The source of the seventh transistor N3 is connected to the drain of the fifth transistor N2, the gate is connected to the drain of the fourth transistor N1, and the drain is connected to the low voltage power supply VDDL. The source of the sixth transistor P3 is connected to the drain of the second transistor P1, the gate is connected to the drain of the fourth transistor N1, and the drain is grounded.
Optionally, the first inverter comprises: a gate of the eighth transistor is connected to the output terminal of the schmitt inverter, a drain of the eighth transistor is connected to the power supply, and a source of the eighth transistor is connected to the output terminal of the reset unit; and a ninth transistor, wherein a gate of the ninth transistor is connected to an output terminal of the schmitt inverter, a source of the ninth transistor is grounded, and a drain of the eighth transistor is connected to an output terminal of the reset unit.
As shown in fig. 5, the first inverter includes an eighth transistor P4 and a ninth transistor N4. The source of the ninth transistor N4 is grounded, the gate is connected to the drain of the fourth transistor N1, and the drain is connected to the output terminal of the RESET unit to output the RESET signal RESET. The eighth transistor P4 has a source connected to VDDL, a gate connected to the drain of the fourth transistor N1, and a drain connected to the RESET signal.
In the embodiment of the present invention, a reset unit including the following structure is adopted: the reset signal charging circuit is connected to the power supply and is used for charging and outputting a voltage signal after the power supply is electrified; and the Schmitt buffer circuit is connected to the reset signal charging circuit and used for outputting a reset signal according to the voltage signal and the threshold voltage of the Schmitt buffer circuit, and the purposes of prolonging the reset time and inhibiting the influence of power supply jitter are achieved by setting the voltage threshold of the Schmitt buffer circuit, so that the technical effect of realizing longer reset time under a simpler circuit structure is realized, and the technical problem that the reset unit cannot be compatible to realize long reset time under the condition of simple circuit structure in the related technology is solved.
Optionally, the reset unit further comprises: the reset signal discharge circuit, wherein, reset signal discharge circuit's input is used for receiving external control signal, and reset signal discharge circuit's first output is connected to reset signal charging circuit, and reset signal discharge circuit's second output is connected to the output of reset unit for discharge the output of reset signal charging circuit and reset unit according to external control signal.
Alternatively, the reset signal discharge circuit includes: the input end of the second inverter is used for receiving an external control signal; a tenth transistor, wherein a gate of the tenth transistor is connected to the output terminal of the second inverter, a drain of the tenth transistor is connected to the reset signal charging circuit, and a source of the tenth transistor is grounded; and an eleventh transistor, wherein a gate of the eleventh transistor is connected to the output terminal of the second inverter, a drain of the eleventh transistor is connected to the output terminal of the reset unit, and a source of the eleventh transistor is grounded.
An embodiment of the present invention will be described below with reference to fig. 6. As shown in fig. 6, the reset signal discharge circuit includes a second inverter INV1, a tenth transistor N5, and an eleventh transistor N6. The second inverter INV1 has an input terminal connected to the ENABLE signal ENABLE, outputs gate terminals of the tenth transistor N5 and the eleventh transistor N6, and has a power supply terminal connected to the high voltage power supply VDDH. The source terminal of the tenth transistor N5 is grounded, the gate terminal is connected to the output terminal of the second inverter INV1, and the drain terminal is connected to the source terminal of the first transistor N7. The source end of the eleventh transistor N6 is grounded, the gate end is connected to the output end of the second inverter INV1, and the drain end is connected to the output end of the RESET signal RESET.
Preferably, the power-down of the low dropout regulator LDO according to the embodiment of the present invention is controlled by the ENABLE signal ENABLE, and therefore, the discharging of the reset signal is also controlled by the ENABLE signal ENABLE when the power-down is performed. When the ENABLE signal ENABLE transitions to a low level, the first capacitor Crst and the RESET signal RESET are pulled low by the tenth transistor N5 and the eleventh transistor N6 to a low level to prevent a secondary power-on-RESET failure.
The following describes an embodiment of the present invention in detail with reference to fig. 6.
The reset unit of the embodiment of the invention comprises a reset signal charging circuit, a Schmitt buffer circuit and a reset signal discharging circuit.
The reset signal charging circuit comprises a first transistor N7, a first capacitor Crst and a second capacitor Ccore, wherein the grid and the drain of the first transistor N7 are both connected with a low voltage power supply VDDL, the source is connected with the positive electrode of the first capacitor Crst, the positive electrode of the first capacitor Crst is connected with the source of the first transistor N7, the negative electrode is grounded, the positive electrode of the second capacitor Ccore is connected with the low voltage power supply VDDL, and the negative electrode is grounded.
The schmitt buffer circuit includes a schmitt inverter and a first inverter, wherein the schmitt inverter includes a second transistor P1, a third transistor P2, a fourth transistor N1, a fifth transistor N2, a sixth transistor P3, and a seventh transistor N3. The source of the second transistor P1 is connected to the low voltage power supply VDDL, the gate is connected to the source of the first transistor N7, and the drain is connected to the source of the third transistor P2. The source of the third transistor P2 is connected to the drain of the second transistor P1, the gate is connected to the source of the first transistor N7, and the drain is connected to the drain of the fourth transistor N1. The source of the fourth transistor N1 is connected to the drain of the fifth transistor N2, the gate is connected to the source of the first transistor N7, and the drain is connected to the drain of the third transistor P2. The source of the fifth transistor N2 is grounded, the gate is connected to the source of the first transistor N7, and the drain is connected to the source of the fourth transistor N1. The source of the seventh transistor N3 is connected to the drain of the fifth transistor N2, the gate is connected to the drain of the fourth transistor N1, and the drain is connected to the low voltage power supply VDDL. The source of the sixth transistor P3 is connected to the drain of the second transistor P1, the gate is connected to the drain of the fourth transistor N1, and the drain is grounded. The first inverter includes an eighth transistor P4 and a ninth transistor N4. The source of the ninth transistor N4 is grounded, the gate is connected to the drain of the fourth transistor N1, and the drain is connected to the output terminal of the RESET unit to output the RESET signal RESET. The eighth transistor P4 has a source connected to VDDL, a gate connected to the drain of the fourth transistor N1, and a drain connected to the RESET signal.
The reset signal discharge circuit includes a second inverter INV1, a tenth transistor N5, and an eleventh transistor N6. The second inverter INV1 has an input terminal receiving the ENABLE signal ENABLE, an output terminal receiving the gates of the tenth transistor N5 and the eleventh transistor N6, and a power supply terminal receiving the high voltage power supply VDDH. The source of the tenth transistor N5 is grounded, the gate thereof is connected to the output terminal of the second inverter INV1, and the drain thereof is connected to the source of the first transistor N7. The eleventh transistor N6 has a source grounded, a gate connected to the output terminal of the second inverter INV1, and a drain connected to the output terminal of the RESET signal RESET.
In the embodiment of the present invention, the first transistor N7 is diode connected, the first transistor N7 is turned on only when the second capacitor Ccore is charged to exceed the threshold voltage of the first transistor N7, so that only the second capacitor Ccore is charged during the power-up period, and when the low voltage power VDDL exceeds the threshold voltage of the first transistor N7, the first capacitor Crst is charged through the first transistor N7, during which the voltage of the second capacitor Ccore is slightly decreased (less than 50mV), because the positive electrode of the second capacitor Ccore charges the first capacitor Crst, during which the low voltage power VDDL is high enough and the reset signal is active, so that the reset signal during this period resets the system, as shown in fig. 7.
The clamping action of the first transistor N7 may enable the generation of a normal reset signal even when the power-on time is long, as shown in fig. 8, which is 1 ms. The capacitor size may be adjusted such that the voltage of the second capacitor Ccore slightly decreases and the voltage of the first capacitor Crst slowly increases for a period after the first transistor N7 is turned on. In addition, a proper forward threshold voltage is obtained by adjusting the transistor parameters of the Schmitt inverter, and when the voltage of the node T and the voltage of the low-voltage power supply VDDL respectively rise and fall to a certain voltage, the Schmitt inverter is triggered to jump, so that the output of the Schmitt buffer circuit is inverted.
Table 1 shows the effect of different capacitance sizes on the final reset time, knowing that relatively long reset times can be obtained with very small capacitances. Capacitance values of different magnitudes can be selected according to the requirement of the system on the reset time. Table 2 shows a comparison between the reset time of the reset unit according to the embodiment of the present invention and the reset time of the conventional reset unit (the reset unit shown in fig. 1), which indicates that the reset unit according to the embodiment of the present invention greatly increases the reset time.
TABLE 1
| Size of capacitor | 1pF | 10pF | 100pF | 1nF | 10nF |
| Reset time | 55us | 530us | 5.3ms | 52ms | 530ms |
TABLE 2
| Existing reset unit (R100K) | Reset unit of the embodiment of the invention | |
| Reset time | 85us | 52ms |
In the embodiment of the invention, the positive threshold voltage of the Schmitt buffer circuit is higher than the negative threshold voltage, and the output of the Schmitt inverter is inverted when the voltage of the node T exceeds the positive threshold voltage of the Schmitt inverter, so that the time of inverting the output of the Schmitt buffer circuit can be delayed by the higher positive threshold voltage, the reset time can be improved, and the power supply jitter in the power-on process can be inhibited to a certain extent by the lower negative threshold voltage. In addition, the low voltage power supply VDDL can be stabilized to 1.15V or more quickly by adjusting the capacitance in the reset signal charging circuit.
In the embodiment of the invention, the power-down of the LDO is controlled by the ENABLE signal ENABLE, so that the discharging of the reset signal is controlled by the ENABLE signal ENABLE when the power-down is performed. When the ENABLE signal ENABLE transitions to a low level, the first capacitor Crst and the RESET signal RESET are pulled low by the tenth transistor N5 and the eleventh transistor N6 to avoid a secondary power-on-RESET failure, as shown in fig. 9.
As can be seen from the above description, the embodiments of the present invention disclose a simple and reliable reset unit, which has a long reset time, can maintain normal and error-free operation even if the power-on time is long or there is a certain jitter in the power-on power source, and is suitable for a system on a chip (i.e., SOC). The whole reset unit has the function that when the SoC system is electrified, a low and effective reset signal with a long period of time is generated, so that the SoC system starts to work from a reset state, and the function of automatic reset after electrification is achieved. The reset circuit of the embodiment of the invention is simple and feasible, the reset time is greatly prolonged under the condition of only using 13 transistors and 2 capacitors, the Schmitt phase inverter is arranged, the suppression effect on power supply jitter is facilitated to a certain extent, the NMOS transistor adopting a diode connection mode is used for charging and clamping, even if the power-on time of a power supply is relatively long, the amplitude of a reset signal can be ensured to reach the normal size, a discharge channel in power failure is well ensured through the reset signal discharge circuit, and the failure of secondary power-on reset is effectively avoided.
According to still another embodiment of the present invention, there is provided a chip including the reset unit described above.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (9)
1. A reset unit, comprising:
the reset signal charging circuit is connected to a power supply and is used for charging and outputting a voltage signal after the power supply is electrified; and
the Schmitt buffer circuit is connected to the reset signal charging circuit and used for outputting a reset signal according to the voltage signal and the threshold voltage of the Schmitt buffer circuit;
the reset signal charging circuit includes: a first transistor, wherein a gate and a drain of the first transistor are connected to the power supply; a first capacitor, wherein a positive electrode of the first capacitor is connected to a source of the first transistor, and a negative electrode of the first capacitor is grounded; and a second capacitor, wherein a positive electrode of the second capacitor is connected to the power supply, and a negative electrode of the second capacitor is grounded.
2. The reset unit according to claim 1, wherein the first transistor is an NMOS transistor.
3. The reset unit of claim 1, wherein the schmitt buffer circuit comprises:
the Schmitt inverter is connected to the reset signal charging circuit and outputs an inverted voltage when a voltage signal output by the reset signal charging circuit exceeds a threshold voltage of the Schmitt inverter; and
and the first inverter is connected to the output ends of the Schmitt inverter and the reset unit and is used for inverting the inverted voltage output by the Schmitt inverter and outputting the reset signal.
4. The reset unit of claim 3, wherein the Schmitt inverter comprises:
a second transistor, wherein a source of the second transistor is connected to the power supply, and a gate of the second transistor is connected to the reset signal charging circuit;
a third transistor, wherein a source of the third transistor is connected to a drain of the second transistor, and a gate of the third transistor is connected to the reset signal charging circuit;
a fourth transistor, wherein a drain of the fourth transistor is connected to a drain of the third transistor, and a gate of the fourth transistor is connected to the reset signal charging circuit;
a fifth transistor, wherein a source of the fifth transistor is grounded, a gate of the fifth transistor is connected to the reset signal charging circuit, and a drain of the fifth transistor is connected to a source of the fourth transistor;
a sixth transistor, wherein a source of the sixth transistor is connected to the drain of the second transistor, a gate of the sixth transistor is connected to the drain of the fourth transistor, and a drain of the sixth transistor is grounded; and
a seventh transistor, wherein a source of the seventh transistor is connected to a drain of the fifth transistor, a gate of the seventh transistor is connected to a drain of the fourth transistor, and a drain of the seventh transistor is connected to the power supply.
5. The reset unit of claim 4, wherein the Schmitt inverter has a positive threshold voltage higher than a negative threshold voltage.
6. The reset unit according to claim 3, wherein the first inverter comprises:
an eighth transistor, wherein a gate of the eighth transistor is connected to an output terminal of the schmitt inverter, a drain of the eighth transistor is connected to the power supply, and a source of the eighth transistor is connected to an output terminal of the reset unit; and
a ninth transistor, wherein a gate of the ninth transistor is connected to an output terminal of the schmitt inverter, a source of the ninth transistor is grounded, and a drain of the eighth transistor is connected to an output terminal of the reset unit.
7. The reset unit of claim 1, further comprising: the reset signal discharge circuit comprises an input end of the reset signal discharge circuit, a first output end of the reset signal discharge circuit is connected to the reset signal charging circuit, and a second output end of the reset signal discharge circuit is connected to the output end of the reset unit and used for discharging the reset signal charging circuit and the output end of the reset unit according to the external control signal.
8. The reset unit according to claim 7, wherein the reset signal discharging circuit comprises:
a second inverter, wherein an input terminal of the second inverter is used for receiving the external control signal;
a tenth transistor, wherein a gate of the tenth transistor is connected to the output terminal of the second inverter, a drain of the tenth transistor is connected to the reset signal charging circuit, and a source of the tenth transistor is grounded; and
an eleventh transistor, wherein a gate of the eleventh transistor is connected to the output terminal of the second inverter, a drain of the eleventh transistor is connected to the output terminal of the reset unit, and a source of the eleventh transistor is grounded.
9. A chip comprising a reset unit according to any one of claims 1 to 8.
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| CN201610170342.7A CN107231145B (en) | 2016-03-23 | 2016-03-23 | Reset unit and chip |
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| CN201610170342.7A CN107231145B (en) | 2016-03-23 | 2016-03-23 | Reset unit and chip |
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| CN107231145B true CN107231145B (en) | 2020-10-27 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107707233B (en) * | 2017-11-03 | 2020-09-01 | 中国电子科技集团公司第五十四研究所 | Reset circuit for preventing instantaneous power failure from causing secondary reset |
| CN109861678B (en) * | 2017-11-30 | 2022-12-13 | 兆易创新科技集团股份有限公司 | Power-on reset circuit and chip |
| CN112204884B (en) * | 2018-05-31 | 2024-04-26 | 华为技术有限公司 | Power-on reset circuit and isolated half-bridge driver |
| CN112260663B (en) * | 2020-11-11 | 2023-06-30 | 北京中科芯蕊科技有限公司 | Subthreshold pulse stretching circuit |
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| JP2010147835A (en) * | 2008-12-19 | 2010-07-01 | Mitsumi Electric Co Ltd | Power-on resetting circuit |
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| CN101882926A (en) * | 2010-06-24 | 2010-11-10 | 北京巨数数字技术开发有限公司 | Power on reset circuit for constant-current driving chip |
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