CN104134658A - Standard cell metal structure directly over polysilicon structure - Google Patents
Standard cell metal structure directly over polysilicon structure Download PDFInfo
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- CN104134658A CN104134658A CN201410182965.7A CN201410182965A CN104134658A CN 104134658 A CN104134658 A CN 104134658A CN 201410182965 A CN201410182965 A CN 201410182965A CN 104134658 A CN104134658 A CN 104134658A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
Abstract
A semiconductor structure includes a first active area structure, an isolation structure surrounding the first active area structure, a first polysilicon structure, a first metal structure, and a second metal structure. The first polysilicon structure is over the first active area structure. The first metal structure is directly over a first portion of the first active area structure. The second metal structure is directly over and in contact with a portion of the first polysilicon structure and in contact with the first metal structure. The invention also discloses a standard cell metal structure directly over a polysilicon structure.
Description
Require priority
The application requires the U.S. Provisional Patent Application the 61/818th of submitting on May 2nd, 2013, the priority of No. 694, and its full content is hereby expressly incorporated by reference.
Related application
The application relates to and acts on behalf of case number for T5057-883U (TSMC2013-0379, title is " Standard Cell Having Cell Height being Non-integral Multiple of Nominal Minimum Pitch ") and T5057-884U (TSMC2013-0380, title is " Standard Cells for Predetermined Function Having Different Types of Layout ") co-pending patent application, the full content of the two is hereby expressly incorporated by reference.
Technical field
The present invention relates to technical field of semiconductors, more specifically, relate to the standard cell metal structure that is located immediately at polysilicon structure top.
Background technology
In the design of integrated circuit, use the standard cell with predetermined function.The pre-designed layout of standard cell is kept in cell library.In the time of a kind of integrated circuit of design, from cell library, retrieve the pre-designed layout of standard cell and place it in the one or more desired locations on integrated circuit layout.Then connect up, standard cell is interconnected with metal wire (metal track).After this, integrated circuit layout is used for by carrying out manufacturing integration circuit with predetermined semiconductor fabrication process.
Summary of the invention
In order to solve existing problem in prior art, according to an aspect of the present invention, provide a kind of layout designs that can be used for manufacturer's standard unit, comprising:
The first active area layout patterns, is associated with the first active area that forms described standard cell, and isolated area is at least positioned at the outside of described the first active area layout patterns;
The first polysilicon layout patterns, is associated with the first polysilicon structure that forms described standard cell, and described the first polysilicon layout patterns is configured to described the first active area layout patterns overlapping;
The first metal layout patterns, is associated with the first metal structure that forms described standard cell, and described the first metal layout pattern arrangement is overlapping with described the first active area layout patterns; And
The second metal layout patterns, is associated with the second metal structure that forms described standard cell, and described the second metal layout pattern arrangement is and described the first polysilicon layout patterns and described the first metal layout pattern overlapping.
In optional embodiment, described the second metal layout patterns is also configured to described the first active area layout patterns and described isolated area overlapping.
In optional embodiment, described the second metal layout patterns flatly extends to outside described the first active area layout patterns along the channel width dimension of described the first active area layout patterns.
In optional embodiment, described the second metal layout patterns flatly extends to outside described the first active area layout patterns along the orientation of described the first active area layout patterns.
In optional embodiment, described layout designs also comprises: the second active area layout patterns, be associated with the second active area that forms described standard cell, described isolated area is also positioned at the outside of described the second active area layout patterns, described the first active area layout patterns defines P transistor npn npn district, and described the second active area layout patterns defines N-type transistor area, and described the first polysilicon layout patterns is positioned at described the second layout patterns top, active area.
In optional embodiment, described layout designs also comprises: the 3rd metal layout patterns, be associated with the 3rd metal structure that forms described standard cell, described the 3rd metal layout pattern arrangement is and described the first polysilicon layout patterns and described the second metal layout pattern overlapping.
In optional embodiment, described layout designs also comprises: the second polysilicon layout patterns, be associated with the second polysilicon structure that forms described standard cell, and described the second polysilicon layout patterns is configured to described the first active area layout patterns overlapping; And, the 3rd metal layout patterns, be associated with the 3rd metal structure that forms described standard cell, described the 3rd metal layout pattern arrangement is overlapping with described the second polysilicon layout patterns, and according to predetermined interval rule, described the second metal layout patterns and described the 3rd metal layout patterns are opened by horizontal subdivision.
According to a further aspect in the invention, also provide a kind of semiconductor structure, having comprised:
The first active area structure;
Isolation structure, around described the first active area structure;
The first polysilicon structure, is positioned at described the first active area structure top;
The first metal structure, is located immediately at above the Part I of described the first active area structure; And
The second metal structure, is located immediately at the part top of described the first polysilicon structure and contacts with the described Part I of described the first polysilicon structure and contact with described the first metal structure.
In optional embodiment, described the second metal structure is also located immediately at the Part II top of described the first active area structure and the part top of described isolation structure.
In optional embodiment, described the second metal structure flatly extends to outside described the first active area structure along the channel width dimension of described the first active area structure.
In optional embodiment, described the second metal structure flatly extends to outside described the first active area structure along the orientation of described the first active area structure.
In optional embodiment, described the first active area structure comprises fin structure.
In optional embodiment, described semiconductor structure also comprises: the second active area structure, by described isolation structure around, described the first active area structure forms a part for P transistor npn npn, and described the second active area structure forms the transistorized part of N-type, and described polysilicon structure is positioned at described the second top, active area.
In optional embodiment, described semiconductor structure also comprises: the 3rd metal structure, is located immediately at described the first polysilicon structure top and contacts with described the first polysilicon structure and contact with described the second metal structure.
In optional embodiment, described semiconductor structure also comprises: the second polysilicon structure, is positioned at described the first active area structure top; And the 3rd metal structure, is located immediately at described the second polysilicon structure top and contacts with described the second polysilicon structure, and described the second metal structure and described the 3rd metal structure are opened by horizontal subdivision according to predetermined interval rule.
According to another aspect of the invention, also provide a kind of IC design system, having comprised:
Nonvolatile storage medium, the layout designs coding of standard cell for described nonvolatile storage medium, described layout designs comprises:
The first active area layout patterns, is associated with the first active area that forms described standard cell, and isolated area is at least positioned at the outside of described the first active area layout patterns;
The first polysilicon layout patterns, is associated with the first polysilicon structure that forms described standard cell, and described the first polysilicon layout patterns is configured to described the first active area layout patterns overlapping;
The first metal layout patterns, is associated with the first metal structure that forms described standard cell, and described the first metal layout pattern arrangement is overlapping with described the first active area layout patterns; And
The second metal layout patterns, is associated with the second metal structure that forms described standard cell, and described the second metal layout pattern arrangement is and described the first polysilicon layout patterns and described the first metal layout pattern overlapping; And
Hardware processor, communicates to connect and is configured to carry out one group of instruction that the described layout designs based on primary circuit design and described standard cell produces integrated circuit layout with described nonvolatile storage medium.
In optional embodiment, described the second metal layout patterns is also configured to described the first active area layout patterns and described isolated area overlapping.
In optional embodiment, the layout designs of the described standard cell of encoding in described nonvolatile storage medium also comprises: the second active area layout patterns, be associated with the second active area that forms described standard cell, described in being also positioned at, described isolated area has the outside of the second source region layout patterns, described the first active area layout patterns is positioned at P transistor npn npn district, and described the second active area layout patterns is positioned at N-type transistor area, and described the first polysilicon layout patterns is positioned at described the second layout patterns top, active area.
In optional embodiment, the layout designs of the described standard cell of encoding in described nonvolatile storage medium also comprises: the 3rd metal layout patterns, be associated with the 3rd metal structure that forms described standard cell, described the 3rd metal layout pattern arrangement is and described the first polysilicon layout patterns and described the second metal layout pattern overlapping.
In optional embodiment, the layout designs of the described standard cell of encoding in described nonvolatile storage medium also comprises: the second polysilicon layout patterns, be associated with the second polysilicon structure that forms described standard cell, described the second polysilicon layout patterns is configured to described the first active area layout patterns overlapping; And, the 3rd metal layout patterns, be associated with the 3rd metal structure that forms described standard cell, described the 3rd metal layout pattern arrangement is overlapping with described the second polysilicon layout patterns, and described the second metal layout patterns and described the 3rd metal layout patterns are opened by horizontal subdivision according to predetermined interval rule.
In accordance with a further aspect of the present invention, also provide a kind of generation to can be used for the method for the layout designs of manufacturer's standard unit, having comprised:
Produce the active area layout patterns being associated with the active area that forms described standard cell, isolated area is at least positioned at the outside of described active area layout patterns;
Produce the polysilicon layout patterns being associated with the polysilicon structure that forms described standard cell, described polysilicon layout patterns is configured to described active area layout patterns overlapping;
Produce the first metal layout patterns being associated with the first metal structure that forms described standard cell, described the first metal layout pattern arrangement is overlapping with described active area layout patterns; And
Produce the second metal layout patterns being associated with the second metal structure that forms described standard cell, described the second metal layout pattern arrangement is and described polysilicon layout patterns and described the first metal layout pattern overlapping.
In optional embodiment, produce described the second metal layout patterns and carry out with described the second metal layout patterns and described active area layout patterns and the overlapping mode of described isolated area.
In optional embodiment, described method also comprises: carry out Design Rule Checking, to determine whether to exist the design violation being associated with described the second metal layout patterns; And, solve described design in violation of rules and regulations by described the second metal layout patterns being moved to or further moved to described isolated area.
Brief description of the drawings
By the example in accompanying drawing, but be not limited to these examples, show one or more embodiment, wherein, the element in describing in the whole text with same reference numerals represents identical element.
Fig. 1 shows according to the schematic layout pattern of the standard cell of one or more embodiment.
Fig. 2 A shows the sectional view obtaining along datum line A according to the semiconductor structure of manufacturing according to the layout shown in Fig. 1 of one or more embodiment.
Fig. 2 B shows the sectional view obtaining along datum line B according to the semiconductor structure of manufacturing according to the layout shown in Fig. 1 of one or more embodiment.
Fig. 3 shows another schematic layout pattern according to the standard cell of one or more embodiment.
Fig. 4 shows another schematic layout pattern according to the standard cell of one or more embodiment.
Fig. 5 shows according to the functional block diagram of the IC design system of one or more embodiment.
Fig. 6 shows according to the method flow diagram of the generation layout designs of one or more embodiment.
Embodiment
Should be appreciated that, the following disclosure provides one or more different embodiment or example, for realizing different characteristic of the present invention.Below by the particular instance of describing assembly and layout to simplify the present invention.Certainly, these are only examples and are not intended to limit the present invention.According to the standard practices in industry, all parts not drawn on scale in accompanying drawing and the only object for illustrating.
In addition, this can use such as " below ", " above ", " level ", " vertical ", " ... above ", " ... below ", the spatial relationship term such as " upwards ", " downward ", " top ", " bottom ", " left side ", " the right " and derivative thereof (as, " flatly ", " down ", " up " etc.), so that describe parts in the present invention and the relation of another parts.Spatial relationship term is intended to comprise the different azimuth of the device that comprises these parts.
Fig. 1 is according to the schematic layout pattern of the standard cell 100 of one or more embodiment.The all layout patterns that are not standard cell 100 all illustrate in Fig. 1.And, skilled person in the art will appreciate that and use layout patterns to prepare one group of mask, this group mask is in turn intended for the standard cell in manufacturing integration circuit.
The layout of standard cell 100 comprises the first active area layout patterns 102, the second active area layout patterns 104, polysilicon layout patterns 112,114,116 and 118, the metal layout patterns 121,122,123,126,127 and 128 of the first kind, and the metal layout patterns 132 and 134 of Second Type.Active area layout patterns 102 is relevant to the active area structure that forms standard cell 100 with 104.Isolated area 142 is at least positioned at the outside of active area layout patterns 102 and 104.In certain embodiments because active area 102 and 104 and isolated area 142 mutually repelling geometrically, so sometimes, active area is also referred to as oxide layer definition (OD) district.In certain embodiments, active area layout patterns 102 limits P transistor npn npn district, and active layout patterns 104 limits N-type transistor area.
The corresponding polysilicon structure of polysilicon layout patterns 112,114,116 and 118 and formation standard cell 100 is relevant.Metal layout patterns 121,122,123,126,127 is relevant with the metal structure that forms the corresponding first kind with 128.In some applications, the metal structure of the first kind is also referred to as zero layer of (" M0OD " or " MD ") structure of metal of top, oxide layer definition.Metal layout patterns 121,122,123,126,127 and 128 and active area layout patterns 102 and 104 are overlapping.In some applications, the M0OD metal structure (based on metal layout patterns 121,122,123,126,127 and 128) finally obtaining can be used as the one or more transistorized source/drain electrodes of standard cell 100.Metal layout patterns 132 and 134 is associated with the metal structure that forms corresponding Second Type.In some applications, the metal structure of Second Type is also referred to as zero layer of (" M0PO " or " MP ") structure of metal of polysilicon top.
As shown in Figure 1, polysilicon layout patterns 112,114,116 and 118 is configured to active area layout patterns 102 and 104 overlapping.In certain embodiments, polysilicon layout patterns 112 and 114 is associated with the gate electrode that forms standard cell 100, and polysilicon layout patterns 116 and 118 is associated with the edge formation polysilicon structure of the active area structure along corresponding to active area layout patterns 102 and 104.In some applications, the polysilicon structure finally obtaining based on polysilicon layout patterns 116 and 118 is also referred to as polysilicon (PODE) structure on oxide layer definition edge.In certain embodiments, PODE structure does not form one or more transistorized any functional parts of standard cell 100.
Can be used for the polysilicon structure being produced by polysilicon layout patterns 112 to be electrically connected to corresponding to the M0PO structure of metal layout patterns 132 via plug of M0PO structure (based on metal layout patterns 132) top.Metal layout patterns 134 is configured to polysilicon layout patterns 114 and metal layout patterns 122 and 123 overlapping.Therefore, can be used for corresponding to the M0PO structure of metal layout patterns 134 polysilicon structure that is electrically connected M0OD structure (based on metal layout patterns 122 and 123) and is produced by polysilicon layout patterns 114.In certain embodiments, metal layout patterns 134 only with metal pattern 122 and 123 in one overlapping.In certain embodiments, one or more overlapping in metal layout patterns 134 and metal pattern 121,122 and 123 and polysilicon layout patterns 112,114,116 and 118.
In the embodiment show in figure 1, metal layout patterns 134 is overlapping with active area layout patterns 102 and isolated area 142.And as shown in Figure 1, metal layout patterns 134 extend horizontally away active area layout patterns 102 along the channel width dimension W of active area layout patterns 102.In certain embodiments, metal layout patterns 134 extend horizontally away active area layout patterns 102 along the orientation L of active area layout patterns 102.
In certain embodiments, layout patterns 132 and 134 is for the manufacture of the M0PO structure of standard cell 100.The distance B between the layout patterns 132 and 134 of manufacturing M0PO structure with the one group of predetermined design rule control being associated for the manufacture of the pre-customized fabrication technique of standard cell, and/or the gross area of layout patterns or pattern area density.In certain embodiments, this group predetermined design rule not and by the layout patterns for M0PO structure 134 be set to be crossed with source region layout patterns 102 or 104 and isolated area 142 between the opposing rule in border.
In view of the schematic layout pattern shown in Fig. 1, the standard cell 100 of the layout patterns manufacture based on Fig. 1 obtaining can have active area structure (based on layout patterns 102 and 104), around the isolation structure of active area structure, the polysilicon structure of active area structure top is (based on layout patterns 112, 114, 116 and 118), be located immediately at the M0OD metal structure (based on layout patterns 122 or 123) of the top of a part for active area structure (based on layout patterns 102), and be located immediately at a part of top of polysilicon structure (based on layout patterns 114) and the M0PO metal structure that contacts and contact with M0OD metal structure with the described part of described polysilicon structure.In certain embodiments, M0PO metal structure is higher than M0OD metal structure, and therefore, M0OD metal structure also contacts with the sidewall of corresponding M0PO metal structure.For example, M0PO metal structure based on layout patterns 134 is contacting corresponding to the position of datum line 134a with the sidewall of the M0OD metal structure based on layout patterns 122, and M0PO metal structure based on layout patterns 134 is contacting corresponding to the position of datum line 134b with the sidewall of the M0OD metal structure based on layout patterns 123.
Fig. 2 A and Fig. 2 B further show the physical structure of the standard cell finally obtaining.
Fig. 2 A shows the sectional view that the semiconductor structure 150 manufactured according to the layout 100 according to shown in Fig. 1 of one or more embodiment obtains along datum line A.Semiconductor structure 150 comprises the active area structure 162 of substrate 160, substrate top, around the isolation structure 164 of active area structure be located immediately at active area structure and the M0OD metal structure 166 of isolation structure top.
In certain embodiments, substrate 160 comprises elemental semiconductor, compound semiconductor, alloy semiconductor or its combination.The example of elemental semiconductor includes but not limited to silicon and germanium.The example of compound semiconductor includes but not limited to carborundum, GaAs, gallium phosphide, indium phosphide, indium arsenide and indium antimonide.The example of alloy semiconductor includes but not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and GaInAsP.In certain embodiments, also use other semi-conducting materials that comprise III family, IV family and V group element.In one or more embodiments, substrate 160 comprise semiconductor-on-insulator (SOI), doped epitaxial layer, gradient semiconductor layer and/or have a semiconductor layer (as, Si) cover another dissimilar semiconductor layer Stacket semiconductor structure of (as, Ge).In certain embodiments, substrate 160 comprises P type doped substrate.The example of the P type alloy in P doped substrate includes but not limited to boron, gallium and indium.
As shown in Fig. 1 and Fig. 2 A, comprise the many fin structures such as three fins in Fig. 2 A corresponding to the active area structure 162 of layout patterns 102.In the embodiment shown in Fig. 2 A, active area structure 162 comprises fin 162a, 162b and 162c, and isolated area 162d and 162e.In certain embodiments, fin 162a, 162b and 162c are by making with the roughly the same material of substrate 160.In certain embodiments, in order to form P transistor npn npn, fin 162a, 162b and 162c are N-type doping.In certain embodiments, in order to form N-type transistor, fin 162a, 162b and 162c are the doping of P type.In certain embodiments, the one or more additional masking that have different layout patterns are also used with one or more masks of manufacturing active area structure 162 together with having layout patterns 102.
M0OD metal structure 166 is corresponding with layout patterns 122.In certain embodiments, use two-step method to manufacture M0OD metal structure 166: first to form the M0OD metal structure 166a of bottom, then form the M0OD metal structure 166b on top.In certain embodiments, use one-step method to manufacture M0OD metal structure 166.Be formed on the top of M0OD metal structure 166 such as one or more additional metal structures of metal one deck via plug 172 and metal one layer conductor 174.In certain embodiments, the material of M0OD metal structure 166 comprises tungsten, complex copper or composite tungsten.
Fig. 2 B shows the sectional view that the semiconductor structure 150 manufactured according to the layout 100 according to shown in Fig. 1 of one or more embodiment obtains along datum line B.As shown in Figure 2 A and 2B, polysilicon structure 182 is located immediately at the top of active area structure 162.Polysilicon structure 182 is corresponding with layout patterns 114.M0PO metal structure 184 is located immediately at polysilicon structure 182 tops and contacts with polysilicon structure 182.M0PO metal structure 184 is located immediately at the top of active area structure 162 and isolation structure 164.In certain embodiments, M0PO metal structure 184 and active area structure 162 are separated by one or more layers dielectric layer and/or grid structure (not shown).M0PO metal structure 184 is corresponding with layout patterns 134.In certain embodiments, the material of M0PO metal structure 184 comprises tungsten, complex copper or composite tungsten.
Because the spatial relationship of other spatial relationships between the different parts of standard cell 100 and corresponding layout patterns is similar and from wherein can clearly obtaining, so can dispense describing in further detail about such spatial relationship.
In certain embodiments, use the different elements (such as M0PD structure or polysilicon structure) in M0PO metal structure connection standard unit, this contributes to minimize the area in 0 layer, metal or other cross tie part layers that standard cell itself occupies.Therefore, more cross tie part interconnection resource can be used for by the Wiring technique arranging and wiring tool is implemented.
Fig. 3 shows according to another schematic layout pattern of the standard cell 300 of one or more embodiment.The layout of standard cell 300 comprises the first active area layout patterns 302, the second active area layout patterns 304, polysilicon layout patterns 312,314,316,318a and 318b, the metal layout patterns 321,322,326 and 327 of the first kind and the metal layout patterns 332,334,336 and 338 of Second Type.Active area layout patterns 302 and 304 is associated with the active area structure that forms standard cell 300.Isolated area 342 is at least positioned at the outside of active area layout patterns 302 and 304.Polysilicon layout patterns 312,314,316,318a and 318b are associated with the polysilicon structure of the corresponding standard cell 300 of formation.Metal layout patterns 321,322,326 and 327 is associated with the corresponding M0OD metal structure of formation.Metal layout patterns 332,334,336 and 338 is associated with the corresponding M0PO metal structure of formation.
In the embodiment shown in fig. 3, metal layout patterns 336 and 338 is used to form M0PO metal structure, M0PO metal structure electrical connection polysilicon structure (based on layout patterns 316) and M0OD metal structure (based on layout patterns 322 and 327).In order to meet predetermined design rule, after the position of layout patterns 334 and size are determined, layout patterns 336 extend horizontally away the first active area layout patterns 302 along channel width dimension W and the orientation L of the first active area layout patterns.And layout patterns 338 extend horizontally away the second active area layout patterns 304 along channel width dimension W and the orientation L of the second active area layout patterns.
Fig. 4 shows according to another schematic layout pattern of the standard cell 400 of one or more embodiment.The layout of standard cell 400 comprises the first active area layout patterns 402, the second active area layout patterns 404, polysilicon layout patterns 412,414,416,418a and 418b, the metal layout patterns 421,422,426 and 427 of the first kind, and the metal layout patterns 432,434,436 and 438 of Second Type.Active area layout patterns 402 and 404 is associated with the active area structure that forms standard cell 400.Isolated area 442 is at least positioned at the outside of active area layout patterns 402 and 404.Polysilicon layout patterns 412,414,416,418a and 418b are associated with the polysilicon structure of the corresponding standard cell 400 of formation.Metal layout patterns 421,422,426 and 427 is associated with the corresponding M0OD metal structure of formation.Metal layout patterns 432,434,436 and 438 is associated with the corresponding M0PO metal structure of formation.
In the embodiment show in figure 4, similar with the embodiment shown in Fig. 3, metal layout patterns 436 and 438 is used to form M0PO metal structure, M0PO metal structure electrical connection polysilicon structure (based on layout patterns 416) and M0OD metal structure (based on layout patterns 422 and 427).In the embodiment show in figure 4, the size of active area pattern 402 and 404 is enough large, makes layout patterns 436 and 438 can not extend horizontally away active area layout patterns along channel width dimension W.But in order to meet predetermined design rule, after the position of pattern layout 434 and size are determined, layout patterns 436 and 438 still extend horizontally away corresponding active area layout patterns along orientation L.
Fig. 5 shows according to the functional block diagram of the IC design system 500 of one or more embodiment.IC design system 500 comprises first computer system 510, second computer system 520, the network storage equipment 530 and connects the network 540 of first computer system 510, second computer system 520 and the network storage equipment 530.In certain embodiments, can dispense one or more in second computer system 520, memory device 530 and network 540.
First computer system 510 comprises hardware processor 512, this hardware processor 512 and integrated layout 514a, circuit design 514b to produce, computer program code 514c are (, one group of executable instruction) and the non-transient computer-readable recording medium 514 with the standard cell lib 514d coding (, storage) in conjunction with Fig. 1, Fig. 3 and the described layout patterns of Fig. 4 communicate to connect.Processor 512 is electrically connected and communicates to connect with computer-readable recording medium 514.Processor 512 is configured to carry out one group of instruction 514c of coding in computer-readable recording medium 514, thereby makes computer 510 can be used as arranging and wiring tool, to produce the layout designs based on standard cell lib 514d.
In certain embodiments, standard cell lib 514d is stored in non-transient storage medium instead of in storage medium 514.In certain embodiments, standard cell lib 514d is stored in the non-transient storage medium in the network storage equipment 530 or second computer system 520.In this case, processor 512 is by network-accessible standard cell lib 514d.
In certain embodiments, processor 512 is central processing unit (CPU), multiprocessor, distributed processing system(DPS), application-specific integrated circuit (ASIC) (ASIC) and/or suitable processing unit.
In certain embodiments, computer-readable recording medium 514 is electronics, magnetic, optics, electromagnetism, ultrared and/or semiconductor system (or device or equipment).For example, computer-readable recording medium 514 comprises semiconductor or solid-state memory, tape, removable computer diskette, random access memory (RAM), read-only memory (ROM), hard disc and/or CD.In some embodiment of use CD, computer-readable recording medium 514 comprises disk read/write (CD-R/W) and/or the Digital video disc (DVD) of compact compact disc-ROM (CD-ROM), compactness.
In at least some embodiment, computer system 510 comprises I/O interface 516 and display unit 517.I/O interface 516 is connected to controller 512 and allows circuit designer to operate first computer system 510.In at least some embodiment, display unit 517 shows and carries out the state of setting and wiring tool 514a and graphic user interface (GUI) is preferably provided with real-time mode.In at least some embodiment, I/O interface 516 and display unit 517 allow operator to operate computer system 510 in mutual mode.
Fig. 6 shows method 600 flow charts according to the generation layout designs of one or more embodiment.Should be appreciated that, the operation that can add before, during and/or after the method 600 shown in Fig. 6, and at this, some other techniques are only described simply.In certain embodiments, carry out method 600 by operational hardware computer (all computer systems 510 as shown in Figure 5).
In operating procedure 610, produce the layout patterns of standard cell, all layout patterns as shown in Figure 1.The layout patterns producing comprises the one or more layout patterns that are used to form M0PO structure.In certain embodiments, form at least one in one or more layout patterns of M0PO structure and the corresponding active area layout patterns of standard cell and corresponding isolated area overlapping and there is no need with two all overlapping.In certain embodiments, the one or more layout patterns for M0PO structure of generation and corresponding active area layout patterns and corresponding isolated area are overlapping.
For example, operating procedure 610 comprises the active area layout patterns that generation is associated with the active area that forms standard cell, and isolated area is at least positioned at the outside (operating procedure 612) of active area layout patterns.Operating procedure 610 also comprises the polysilicon layout patterns that generation is associated with the polysilicon structure that forms standard cell, and polysilicon layout patterns is configured to and active area layout patterns overlapping (operating procedure 614).Operating procedure 610 also comprises the first metal layout patterns (operating procedure 616) that generation is associated with the first metal structure (such as a M0PO structure) that forms standard cell.The first metal layout pattern arrangement is overlapping with active area layout patterns.Operating procedure 610 also comprises the second metal layout patterns (operating procedure 618) that generation is associated with the second metal structure (such as the 2nd M0PO structure) that forms standard cell.The second metal layout pattern arrangement is and polysilicon layout patterns and the first metal layout pattern overlapping.
In operating procedure 620, carry out Design Rule Checking (DRC), to determine whether to exist the design relevant to the layout patterns that forms metal structure (such as M0PO structure) problem in violation of rules and regulations.In addition, in operating procedure 630, if determine existence design problem in violation of rules and regulations in operating procedure 620, by moving to or further move to for one or more layout patterns of metal structure corresponding isolated area to solve design violation problem.
According to an embodiment, the layout designs that can be used for manufacturer's standard unit comprises the first active area layout patterns, the first polysilicon layout patterns, the first metal layout patterns and the second metal layout patterns.The first active area layout patterns is associated with the first active area that forms standard cell, and isolated area is at least positioned at the outside of the first active area layout patterns.The first polysilicon layout patterns is associated with the first polysilicon structure that forms standard cell, and the first polysilicon layout patterns is configured to the first active area layout patterns overlapping.The first metal layout patterns is associated with the first metal structure that forms standard cell, and the first metal layout pattern arrangement is overlapping with the first active area layout patterns.The second metal layout patterns is associated with the second metal structure that forms standard cell, and the second metal layout pattern arrangement is and the first polysilicon layout patterns and the first metal layout pattern overlapping.
According to another embodiment, semiconductor structure comprises the first active area structure, isolation structure, the first polysilicon structure, the first metal structure and the second metal structure around the first active area structure.The first polysilicon structure is positioned at the top of the first active area structure.The first metal structure is located immediately at the Part I top of the first active area structure.The second metal structure is located immediately at the part top of the first polysilicon structure and contacts with a described part and first metal structure of described the first polysilicon structure.
According to another embodiment, IC design system comprises nonvolatile storage medium and the hardware processor with the communication connection of nonvolatile storage medium.With the layout designs coding nonvolatile storage medium of standard cell.Layout designs comprises the first active area layout patterns being associated with the first active area that forms standard cell, the first polysilicon layout patterns being associated with the first polysilicon structure that forms standard cell, the first metal layout patterns being associated with the first metal structure that forms standard cell and the second metal layout patterns being associated with the second metal structure that forms standard cell.Isolated area is at least positioned at the outside of the first active area layout patterns.The first polysilicon layout patterns is configured to the first active area layout patterns overlapping.The first metal layout pattern arrangement is overlapping with the first active area layout patterns.The second metal layout pattern arrangement is and the first polysilicon layout patterns and the first metal layout pattern overlapping.Hardware processor is configured to carry out one group of instruction of the integrated circuit layout that produces the layout designs based on primary circuit design and standard cell.
According to another embodiment, the method that produces the layout designs that can be used for manufacturer's standard unit comprises the active area layout patterns that generation is associated with the active area that forms standard cell.Isolated area is at least positioned at the outside of active area layout patterns.Produce the polysilicon layout patterns being associated with the polysilicon structure that forms standard cell.Polysilicon layout patterns is configured to active area layout patterns overlapping.Produce the first metal layout patterns being associated with the first metal structure that forms standard cell.The first metal layout pattern arrangement is overlapping with active area layout patterns.Produce the second metal layout patterns being associated with the second metal structure that forms standard cell.The second metal layout pattern arrangement is and polysilicon layout patterns and the first metal layout pattern overlapping.
Summarize the feature of some embodiment above, made those of ordinary skill in the art's various aspects that the present invention may be better understood.It will be understood by those skilled in the art that can design or change as basis with the present invention easily other for reach with here the identical object of the embodiment that introduces and/or realize technique and the structure of same advantage.Those of ordinary skill in the art also should be appreciated that such equivalent constructions does not deviate from the spirit and scope of the present invention, and in the situation that not deviating from the spirit and scope of the present invention, can carry out multiple variation, replacement and change.
Claims (10)
1. a layout designs that can be used for manufacturer's standard unit, comprising:
The first active area layout patterns, is associated with the first active area that forms described standard cell, and isolated area is at least positioned at the outside of described the first active area layout patterns;
The first polysilicon layout patterns, is associated with the first polysilicon structure that forms described standard cell, and described the first polysilicon layout patterns is configured to described the first active area layout patterns overlapping;
The first metal layout patterns, is associated with the first metal structure that forms described standard cell, and described the first metal layout pattern arrangement is overlapping with described the first active area layout patterns; And
The second metal layout patterns, is associated with the second metal structure that forms described standard cell, and described the second metal layout pattern arrangement is and described the first polysilicon layout patterns and described the first metal layout pattern overlapping.
2. layout designs according to claim 1, wherein, described the second metal layout patterns is also configured to described the first active area layout patterns and described isolated area overlapping.
3. layout designs according to claim 2, wherein, described the second metal layout patterns flatly extends to outside described the first active area layout patterns along the channel width dimension of described the first active area layout patterns.
4. layout designs according to claim 2, wherein, described the second metal layout patterns flatly extends to outside described the first active area layout patterns along the orientation of described the first active area layout patterns.
5. a semiconductor structure, comprising:
The first active area structure;
Isolation structure, around described the first active area structure;
The first polysilicon structure, is positioned at described the first active area structure top;
The first metal structure, is located immediately at above the Part I of described the first active area structure; And
The second metal structure, is located immediately at the part top of described the first polysilicon structure and contacts with the described Part I of described the first polysilicon structure and contact with described the first metal structure.
6. semiconductor structure according to claim 5, wherein, described the second metal structure is also located immediately at the Part II top of described the first active area structure and the part top of described isolation structure.
7. an IC design system, comprising:
Nonvolatile storage medium, the layout designs coding of standard cell for described nonvolatile storage medium, described layout designs comprises:
The first active area layout patterns, is associated with the first active area that forms described standard cell, and isolated area is at least positioned at the outside of described the first active area layout patterns;
The first polysilicon layout patterns, is associated with the first polysilicon structure that forms described standard cell, and described the first polysilicon layout patterns is configured to described the first active area layout patterns overlapping;
The first metal layout patterns, is associated with the first metal structure that forms described standard cell, and described the first metal layout pattern arrangement is overlapping with described the first active area layout patterns; And
The second metal layout patterns, is associated with the second metal structure that forms described standard cell, and described the second metal layout pattern arrangement is and described the first polysilicon layout patterns and described the first metal layout pattern overlapping; And
Hardware processor, communicates to connect and is configured to carry out one group of instruction that the described layout designs based on primary circuit design and described standard cell produces integrated circuit layout with described nonvolatile storage medium.
8. generation can be used for a method for the layout designs of manufacturer's standard unit, comprising:
Produce the active area layout patterns being associated with the active area that forms described standard cell, isolated area is at least positioned at the outside of described active area layout patterns;
Produce the polysilicon layout patterns being associated with the polysilicon structure that forms described standard cell, described polysilicon layout patterns is configured to described active area layout patterns overlapping;
Produce the first metal layout patterns being associated with the first metal structure that forms described standard cell, described the first metal layout pattern arrangement is overlapping with described active area layout patterns; And
Produce the second metal layout patterns being associated with the second metal structure that forms described standard cell, described the second metal layout pattern arrangement is and described polysilicon layout patterns and described the first metal layout pattern overlapping.
9. method according to claim 8, wherein, produces described the second metal layout patterns and carries out with described the second metal layout patterns and described active area layout patterns and the overlapping mode of described isolated area.
10. method according to claim 8, also comprises:
Carry out Design Rule Checking, to determine whether to exist the design violation being associated with described the second metal layout patterns; And
Solve described design in violation of rules and regulations by described the second metal layout patterns being moved to or further moved to described isolated area.
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| US14/015,924 | 2013-08-30 | ||
| US14/015,924 US9158877B2 (en) | 2013-05-02 | 2013-08-30 | Standard cell metal structure directly over polysilicon structure |
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| DE102013110607B4 (en) | 2020-02-27 |
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