KR20230068952A - Integrated circuit and method for manufacturing the same - Google Patents

Abstract

An integrated circuit and a method of manufacturing the same are disclosed. The method of manufacturing an integrated circuit comprising a plurality of stacked metal layers comprises the steps of: arranging a plurality of standard cells each comprising cell patterns formed on the plurality of metal layers; and forming an additional pattern on a specific metal layer among the plurality of metal layers, wherein the specific metal layer is formed with patterns extended in a first direction and with a plurality of tracks defined and spaced apart from each other in a second direction. The step of forming an additional pattern comprises: a step of forming an additional pattern between adjacent patterns when the gap between adjacent patterns formed on the same track among the plurality of tracks exceeds a reference value.

Description

Integrated circuit and method for manufacturing the same {INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THE SAME}

The technical idea of the present disclosure relates to an integrated circuit and a method for manufacturing the same, and more particularly, to an integrated circuit including a plurality of stacked metal layers and a method for manufacturing the same.

An integrated circuit can be designed based on standard cells. Specifically, the layout of the integrated circuit may be created by arranging standard cells according to data defining the integrated circuit and routing the arranged standard cells. As a semiconductor manufacturing process is miniaturized, the size of patterns in a standard cell may decrease, and the size of the standard cell may also decrease. As the length of a gate of an integrated circuit and the pitch between gate lines continuously decrease, the density of lines for interconnecting semiconductor devices has also increased.

A technical problem to be solved by the present invention is to provide an integrated circuit with increased routing freedom and a method for manufacturing the integrated circuit.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

According to the technical idea of the present disclosure, a method of manufacturing an integrated circuit including a plurality of stacked metal layers includes disposing a plurality of standard cells each including cell patterns formed on the plurality of metal layers, and a plurality of metal layers. Forming an additional pattern on a specific metal layer among the layers, wherein the specific metal layer has patterns extending in a first direction and a plurality of tracks spaced apart from each other in a second direction are defined, and the additional pattern is formed. The performing of the plurality of tracks may include forming an additional pattern between adjacent patterns when a distance between adjacent patterns formed on the same track among the plurality of tracks exceeds a reference value.

According to the technical idea of the present disclosure, an integrated circuit including a plurality of stacked metal layers includes first logic cells and second logic cells each including cell patterns formed on the plurality of metal layers, and among the plurality of metal layers. A dummy pattern is formed over the first logic cell and the second logic cell in the specific metal layer and is electrically separated from other patterns, and in the specific metal layer, patterns extending in a first direction are respectively formed and mutually A plurality of first tracks spaced apart in a second direction may be defined, and patterns may be formed on all tracks of the plurality of first tracks.

According to the technical idea of the present disclosure, an integrated circuit including a plurality of stacked metal layers includes first standard cells and second standard cells each including cell patterns formed on the plurality of metal layers, and among the plurality of metal layers. The specific metal layer is formed over the first standard cell and the second standard cell, and includes an extension pattern extending from the cell pattern of the first standard cell, and the specific metal layer has patterns extending in the first direction, respectively, and mutually. A plurality of first tracks spaced apart in a second direction may be defined, and adjacent patterns formed on the same track among the plurality of first tracks may be spaced apart from each other by at least one predetermined value.

In a method of manufacturing an integrated circuit according to an exemplary embodiment of the present disclosure, when a distance between adjacent patterns formed on the same track among a plurality of tracks formed on a specific metal layer exceeds a reference value in a routing step, an additional pattern is generated. can form Even if the cell pattern of the standard cell itself is not a full-track structure, an integrated circuit with a full-track structure can be manufactured by forming an additional pattern in a routing step. Accordingly, in the method of manufacturing an integrated circuit, the degree of freedom of routing may be increased, and it may be facilitated to form uniform patterns of metal layers.

Effects that can be obtained in the exemplary embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned above can be obtained from the description of the exemplary embodiments of the present disclosure below. It can be clearly derived and understood by those skilled in the art to which they belong. That is, unintended effects according to the exemplary embodiments of the present disclosure may also be derived by those skilled in the art from the exemplary embodiments of the present disclosure.

The drawings accompanying this specification may not be to scale for convenience of illustration, and components may be exaggerated or reduced.
1 is a layout diagram illustrating an integrated circuit according to an exemplary embodiment of the present disclosure.
2A and 2C are cross-sectional views taken along line A-A' of FIG. 1, and FIGS. 2B and 2D are cross-sectional views taken along line B-B' of FIG.
3 and 4 are diagrams for describing an integrated circuit according to an exemplary embodiment of the present disclosure.
5 is a diagram for explaining an integrated circuit according to an exemplary embodiment of the present disclosure.
6 is a flowchart illustrating a method of fabricating an integrated circuit according to an exemplary embodiment of the present disclosure.
7 is a flowchart illustrating a method of fabricating an integrated circuit according to an exemplary embodiment of the present disclosure.
8 is a flowchart illustrating a method of fabricating an integrated circuit according to an exemplary embodiment of the present disclosure.
9 and 10 are diagrams for explaining a method of manufacturing an integrated circuit according to an exemplary embodiment of the present disclosure.
11 is a diagram for explaining a method of manufacturing an integrated circuit according to an exemplary embodiment of the present disclosure.
12 is a block diagram illustrating a computing system for design of an integrated circuit according to an exemplary embodiment of the present disclosure.

Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a layout diagram illustrating an integrated circuit 10 according to an exemplary embodiment of the present disclosure. Specifically, FIG. 1 is a layout diagram for explaining patterns of the first metal layer M1 of the integrated circuit 10 .

FIG. 1 is a plan view showing a part of an integrated circuit 10 constituting one chip or one functional block on a plane consisting of an X axis and a Y axis. In this specification, the X-axis direction and the Y-axis direction may be referred to as a first horizontal direction and a second horizontal direction, respectively, and the Z-axis direction may be referred to as a vertical direction. The plane made up of the X and Y axes can be referred to as the horizontal plane, and components arranged in the +Z-axis direction relative to other components can be referred to as being above other components, and relative to other components - Components disposed in the Z-direction may be referred to as being below other components.

Integrated circuit 10 may include a plurality of standard cells. A standard cell is a layout unit included in an integrated circuit, and may be designed to perform a predefined function, and may also be referred to as a cell. The integrated circuit 10 may include a number of various standard cells, and the standard cells may be arranged and arranged according to a plurality of rows.

Multiple standard cells are used repeatedly in integrated circuit design. Standard cells may be pre-designed according to a manufacturing technology and stored in a standard cell library, and integrated circuits may be designed by arranging and interconnecting standard cells stored in the standard cell library according to design rules.

Standard cells may include logic cells. For example, logic cells include electronic components such as central processing units (CPUs), graphics processing units (GPUs), and systems on a chip (SOCs), such as inverters, AND gates, NAND gates, OR gates, XOR gates, and NOR gates. You can implement circuits that make up various basic circuits that are often used in digital circuit design for devices. Or, for example, logic cells may implement other circuits often used in circuit blocks, such as flip-flops and latches.

Standard cells may include filler cells. A pillar cell may be placed adjacent to a functional cell to provide routing of signals provided to or output from the functional cell. Also, the filler cell may be a cell used to fill a space remaining after functional cells are disposed.

The integrated circuit 10 may include metal layers on which wires for interconnecting standard cells are formed. Some of the metal layers may be used as a configuration for interconnecting elements inside the standard cell.

The plurality of metal layers may be sequentially stacked in a vertical direction, and for example, a second metal layer (eg, M2 in FIGS. 3 and 4) may be formed on the first metal layer M1, A third metal layer (eg, M3 in FIG. 5 ) may be formed on the second metal layer M2 . In an exemplary embodiment, the first metal layer M1 may include patterns extending in the X-axis direction, the second metal layer M2 may include patterns extending in the Y-axis direction, and the third metal layer M2 may include patterns extending in the Y-axis direction. The metal layer M3 may include patterns extending in the X-axis direction (uni-direction). Also, other metal layers may be further formed on the third metal layer M3.

The patterns formed on each of the metal layers may be made of metal, conductive metal nitride, metal silicide, or a combination thereof. In the drawings of this specification, only some layers may be shown for convenience of illustration, and vias may be displayed even though they are located under the pattern of the metal layer to indicate the connection between the pattern of the metal layer and the lower pattern. there is.

The integrated circuit 10 may include a first power line PL1 and a second power line PL2 supplying a voltage to each of the standard cells. The first power line PL1 and the second power line PL2 may be disposed at the boundary of each of the plurality of rows. The first power line PL1 may provide a first supply voltage (eg, power supply voltage) to each standard cell, and the second power line PL2 may provide a second supply voltage (eg, a power supply voltage) to each standard cell. , ground voltage). The first power line PL1 and the second power line PL2 may be formed as conductive patterns extending in the X-axis direction and may be alternately disposed in the Y-axis direction. Although FIG. 1 shows that each of the first power line PL1 and the second power line PL2 is formed as a pattern of the first metal layer M1, the integrated circuit 10 according to the present disclosure is not limited thereto. , Each of the first power line PL1 and the second power line PL2 may be formed as a pattern of an upper metal layer of the first metal layer M1 or may be formed inside a separation trench formed in the substrate. .

Referring to FIG. 1 , the integrated circuit 10 may include a first standard cell C1 and a second standard cell C2 disposed adjacent to each other in the X-axis direction. The first standard cell C1 and the second standard cell C2 may be single height cells aligned and arranged in one row, and the first standard cell C1 and the second standard cell C2 ) may have a first cell height CH1 in the Y-axis direction. However, it is not limited thereto, and the integrated circuit 10 may include a first standard cell C1 and a second standard cell C2, which are multiple height cells consecutively arranged in two or more adjacent rows. may be

Each of the first standard cell C1 and the second standard cell C2 may be defined by a cell boundary. A diffusion break may be formed at the cell boundary. In this case, the first standard cell C1 and the second standard cell C2 may be logic cells.

A plurality of tracks on which patterns of the first metal layer M1 are disposed may be defined in the integrated circuit 10 . The first metal layer M1 may be the lowest metal layer among the plurality of metal layers. A plurality of tracks may extend in the X-axis direction and may be spaced apart from each other in the Y-axis direction. For example, first to fifth tracks TR11 to TR15 may be formed on the first standard cell C1 and the second standard cell C2. Conductive patterns extending in the X-axis direction may be formed in the first to fifth tracks TR11 to TR15. However, unlike shown in FIG. 1, the number of tracks of the first metal layer M1 formed to pass inside the cell boundaries of the first standard cell C1 and the second standard cell C2 can be variously modified. do.

The first standard cell C1 and the second standard cell C2 may include patterns of the first metal layer M1. For example, the first standard cell C1 may include cell patterns formed on the first track TR11, the second track TR12, the third track TR13, and the fifth track TR15. Also, for example, the second standard cell C2 may include cell patterns formed on the first track TR11, the second track TR12, the third track TR13, and the fifth track TR15. .

A cell pattern may not be formed in at least one of the first to fifth tracks TR11 to TR15 in each of the first standard cell C1 and the second standard cell C2. That is, in at least one of the first to fifth tracks TR11 to TR15, a cell pattern may not be formed within the cell boundary of each of the first standard cell C1 and the second standard cell C2. For example, the cell pattern of the first standard cell C1 may not be formed in the fourth track TR14, and the cell pattern of the second standard cell C2 may not be formed in the fourth track TR14. there is. The first standard cell C1 and the second standard cell C2 may not have a full-track structure.

The integrated circuit 10 may include a dummy pattern and/or an extension pattern formed on the first metal layer M1. The dummy pattern and the extension pattern are disposed on the first standard cell C1 and the second standard cell C2 but may not be included in the cell pattern. The dummy pattern and the extension pattern may be patterns generated in a P&R (placement and routing) step (eg, S20 of FIG. 6 ).

Patterns of the first metal layer M1 of the integrated circuit 10 may be arranged to have a designated interval from each other. A spacing between patterns disposed adjacent to each other on the same track of the first metal layer M1 may be defined as a tip-to-tip (hereinafter referred to as “T2T”) space, and a tip-to-tip Patterns of the first metal layer M1 may be arranged so that the tip space has a first designated value T1. For example, within the integrated circuit 10 constituting one chip or one functional block, the number of first designation values T1 may be set to 10 or less. In an exemplary embodiment, the number of first designated values T1 set in the integrated circuit 10 may be one or two.

In the manufacturing method of the integrated circuit 10 according to the present disclosure, a tip-to-tip of the first metal layer M1 is formed by forming a dummy pattern and an extension pattern in an empty space of the first metal layer M1 in a P&R step. space requirements can be met. That is, the integrated circuit 10 may have a full-track structure in which patterns satisfying a tip-to-tip space requirement are formed on all tracks of the first metal layer M1 .

The dummy pattern of the first metal layer M1 may be electrically separated from patterns of other layers. That is, the dummy pattern may be electrically separated from patterns of other metal layers formed on the first metal layer M1 and may be electrically separated from elements formed under the first metal layer M1. .

In an exemplary embodiment, the dummy pattern may be formed over the first standard cell C1 and the second standard cell C2. The dummy pattern of the first metal layer M1 may be formed over two or more standard cells disposed adjacent to each other in the X-axis direction. For example, the dummy patterns may be disposed on the second track TR12 and the third track TR13 and may be disposed on cell boundaries between the first standard cell C1 and the second standard cell C2. there is.

The extension pattern of the first metal layer M1 may be formed to extend from the cell pattern of the first standard cell C1. In an exemplary embodiment, the extension pattern of the first metal layer M1 may be a pattern extending from an output pin or an input pin of the first standard cell C1. A via may be formed on the extension pattern and may be electrically connected to an upper layer of the first metal layer M1, for example, the second metal layer M2. Also, the extension pattern may be electrically connected to an element formed under the first metal layer M1.

In an exemplary embodiment, the extension pattern may be formed over the first standard cell C1 and the second standard cell C2. The extension pattern of the first metal layer M1 may be formed over two or more standard cells disposed adjacent to each other in the X-axis direction. For example, the extension pattern may be disposed on the fifth track TR15.

An integrated circuit 10 according to an exemplary embodiment of the present disclosure includes first standard cells C1 and second standard cells C2 in which empty tracks on which no cell pattern is formed are disposed in a first metal layer M1. and may include a dummy pattern or an extension pattern that is an additional pattern additionally formed in the P&R step. Accordingly, in manufacturing the integrated circuit 10, the degree of freedom of routing may be increased, and it may be easy to form certain patterns on the first metal layer M1 having a full-track structure.

2A and 2C are cross-sectional views taken along line A-A' of FIG. 1, and FIGS. 2B and 2D are cross-sectional views taken along line B-B' of FIG. In the description of FIGS. 2C and 2D , redundant descriptions of the same reference numerals as those in FIGS. 2A and 2B will be omitted.

1, 2a, and 2b, each of the first standard cell C1 and the second standard cell C2 of the integrated circuit 10 may be defined by a cell boundary, and each cell boundary includes A diffusion brake 120 may be formed. The diffusion brake 120 may electrically separate active regions of different standard cells from each other. Although a single diffusion break is shown in FIGS. 2A and 2B, a double diffusion break may be formed at the cell boundary.

The diffusion brake 120 may include a silicon-containing insulating layer such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbonitride layer, or a combination thereof. For example, the diffusion brake 120 may include fluoride silicate glass (FSG), undoped silicate glass (USG), boro-phospho-silicate glass (BPSG), phospho-silicate glass (PSG), flowable oxide (FOX), PE -TEOS (plasma enhanced tetra-ethyl-ortho-silicate), or TOSZ (tonen silazene) may be included.

Each of the first standard cell C1 and the second standard cell C2 of the integrated circuit 10 may include a fin-type active region F protruding from the substrate 902 and extending in the X-axis direction. The substrate 902 is a semiconductor such as silicon (Si) or germanium (Ge), or III-IV such as GaAs, AlGaAs, InAs, InGaAs, InSb, GaSb, InGaSb, InP, GaP, InGaP, InN, GaN, InGaN, and the like. group compounds may be included. In an exemplary embodiment, the substrate may be a Silicon-On-Insulator (SOI) substrate or a Germanium-On-Insulator (GOI) substrate.

The number of fin-type active regions F formed in each of the first standard cell C1 and the second standard cell C2 may be variously modified. However, each of the first standard cell C1 and the second standard cell C2 according to the present disclosure is not limited to those shown in FIGS. 2A and 2B, and as shown in FIGS. 2C and 2D, the fin-type active region (F ), a nanosheet may be formed on the nanosheet, and for example, a Multi Bridge Channel (MBC) FET having a gate line surrounding the nanosheet may be formed. Alternatively, for example, a gate-all-around (GAA) FET in which nanowires are surrounded by gate lines may be formed on the fin-type active region F, and a plurality of stacked nanowires are surrounded by gate lines. A vertical GAA FET may be formed. Also, for example, a negative capacitance (NC) FET may be formed in an active region of each of the first standard cell C1 and the second standard cell C2. In addition to the examples of the transistors described above, various transistors (complementary FET (CFET), negative FET (NCFET), carbon nanotube (CNT) FET, bipolar junction transistor, and other three-dimensional transistors) may be formed.

A gate line 960 may be formed to extend in the Y-axis direction on the fin-type active region F. The gate line 960 may be made of metal, metal nitride, metal carbide, or a combination thereof. The metal may be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The metal nitride may be selected from TiN and TaN. The metal carbide may be TiAlC. A gate insulating layer 952 may be interposed to surround the gate line 960 . The gate insulating layer 952 may include an interface layer and a high dielectric layer. The interface layer may be formed of a silicon oxide layer, a silicon oxynitride layer, a silicate layer, or a combination thereof.

A plurality of source/drain regions 930 may be formed on the fin-type active region F. The plurality of source/drain regions 930 may be formed of an epitaxially grown semiconductor layer. For example, the plurality of source/drain regions 930 may include a semiconductor layer epitaxially grown from the fin-type active region F. The plurality of source/drain regions 930 may be formed of an epitaxially grown Si layer, an epitaxially grown SiC layer, an embedded SiGe structure including a plurality of epitaxially grown SiGe layers, or the like. A metal silicide layer may be formed on an upper surface of each of the plurality of source/drain regions 930 .

The plurality of contact plugs 984 may be connected to the plurality of source/drain regions 930 . The plurality of contact plugs 984 may be disposed in the plurality of contact holes penetrating the interlayer insulating layer 974 and the inter-gate insulating layer 944 . Each of the plurality of contact plugs 984 may be made of metal, conductive metal nitride, or a combination thereof. For example, each of the plurality of contact plugs 984 may be made of W, Cu, Al, Ti, Ta, TiN, TaN, an alloy thereof, or a combination thereof.

As shown in FIG. 2A , the dummy pattern formed on the first metal layer M1 may be electrically separated from the patterns of the upper and lower layers. The dummy pattern may not be connected to both the gate line 960 and the plurality of source/drain regions 930 of the first standard cell C1 and the second standard cell C2. In an exemplary embodiment, the length by which the dummy pattern extends from the cell boundary into the first standard cell C1 or the second standard cell C2 is the distance between the gate line 960 and the diffusion brake 120 or an adjacent distance between the gate line 960 and the diffusion brake 120. It may be longer than the distance between the gate lines 960 .

As shown in FIG. 2B , the extension pattern formed on the first metal layer M1 may extend from the cell pattern. In an exemplary embodiment, the extension pattern may be electrically connected to a pattern of an upper layer, eg, the second metal layer M2, through the via V1. In the P&R step, an extension pattern may be formed, and a via V1 contacting the extension pattern and a pattern of an upper layer may be formed on the extension pattern at the same time. Also, in an exemplary embodiment, the extension pattern is at least one of the first standard cell C1 and the second standard cell C2, for example, the gate line 960 or the contact plug of the first standard cell C1. (984) can be electrically connected. For example, the extension pattern may be electrically connected to the contact plug 984 through a via VA formed below the cell pattern.

1, 2c, and 2d, a plurality of fin-type active regions F protruding from the substrate 902 of the first standard cell C1 and the second standard cell C2 of the integrated circuit 10 and , A plurality of nanosheet stacks NSS facing upper surfaces of the plurality of fin-type active regions F at positions spaced apart from the plurality of fin-type active regions F in the Z-axis direction. As used herein, the term "nanosheet" refers to a conductive structure having a cross section substantially perpendicular to the direction in which current flows. It should be understood that the nanosheet includes nanowires.

Each of the plurality of nanosheet stacks NSS may include a plurality of nanosheets N1 , N2 , and N3 overlapping each other in the Z-axis direction on the upper surface of the fin-type active region F. In FIGS. 2C and 2D, a case in which the planar shape of the nanosheet stack NSS has a substantially rectangular shape is illustrated, but is not limited thereto.

In addition, in FIGS. 2C and 2D, a case in which each of the plurality of nanosheet stacks (NSS) is composed of three nanosheets is exemplified, but the present invention is not limited to the exemplified examples. For example, the nanosheet stack NSS may include at least two nanosheets, and the number of nanosheets constituting the nanosheet stack NSS is not particularly limited.

Each of the plurality of nanosheets N1 , N2 , and N3 may have a channel region. In example embodiments, the plurality of nanosheets N1 , N2 , and N3 may have substantially the same thickness. In other exemplary embodiments, at least some of the plurality of nanosheets N1 , N2 , and N3 may have different thicknesses.

In example embodiments, the plurality of nanosheets N1 , N2 , and N3 may be formed of semiconductor layers made of the same element. In one example, each of the plurality of nanosheets N1 , N2 , and N3 may be formed of a Si layer. In another example, each of the plurality of nanosheets N1 , N2 , and N3 may be formed of a SiGe layer. In other exemplary embodiments, the plurality of nanosheets N1 , N2 , and N3 may be formed of semiconductor layers including different elements. For example, the first nanosheet N1 may be formed of a SiGe layer, and the second and third nanosheets N2 and N3 may be formed of a Si layer.

The gate line 960 may surround each of the plurality of nanosheets N1 , N2 , and N3 while covering the nanosheet stack NSS on the fin-type active region F. The plurality of gate lines 960 cover the upper surface of the nanosheet stack NSS and are integrally connected to the main gate portion 960M extending in the Y-axis direction and the main gate portion 960M, respectively, and a plurality of nanosheets. It may include a plurality of sub-gate portions 960S disposed one by one between each of (N1, N2, and N3) and between the fin-type active region F and the first nanosheet N1. The plurality of nanosheets N1 , N2 , and N3 may have a gate-all-around (GAA) structure surrounded by the gate line 960 .

A plurality of inner insulating spacers 928 may be disposed between each of the plurality of nanosheets N1 , N2 , and N3 and between the fin-type active region F and the first nanosheet N1 . Both sidewalls of each of the plurality of sub-gate portions 960S may be covered with an inner insulating spacer 928 with the gate insulating layer 952 interposed therebetween.

3 and 4 are diagrams for explaining integrated circuits 10A and 10A' according to exemplary embodiments of the present disclosure. 3 and 4 are layout diagrams for explaining patterns of the second metal layer M2 of the integrated circuits 10A and 10A'.

Referring to FIG. 3 , the integrated circuit 10A may include a first standard cell C1A and a second standard cell C2A disposed adjacent to each other in the Y-axis direction. Each of the first standard cell C1A and the second standard cell C2A may be a single-height cell aligned and disposed in one row, and each of the first standard cell C1A and the second standard cell C2A may be arranged along the Y axis. may have a first cell height CH1 in the direction. However, the integrated circuit 10A is not limited thereto, and the integrated circuit 10A may also include first standard cells C1A and second standard cells C2A, which are multi-height cells, consecutively arranged in two or more adjacent rows.

Each of the first standard cell C1A and the second standard cell C2A may be defined by a cell boundary. The first standard cell C1A and the second standard cell C2A may be logic cells.

A plurality of tracks on which patterns of the second metal layer M2 are disposed may be defined in the integrated circuit 10A. In this case, the second metal layer M2 may be formed on the first metal layer (M1 in FIG. 1 ) and may be a metal layer second closest to the substrate among the plurality of metal layers.

A plurality of tracks of the second metal layer M2 may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction. For example, first to fifth tracks TR21 to TR25 may be formed on the first standard cell C1A and the second standard cell C2A. Conductive patterns extending in the Y-axis direction may be formed in the first to fifth tracks TR21 to TR25. However, unlike shown in FIG. 3, the number of tracks of the second metal layer M2 formed to pass inside the cell boundaries of the first standard cell C1A and the second standard cell C2A can be variously modified. do.

The first standard cell C1A and the second standard cell C2A may include cell patterns of the second metal layer M2. For example, the first standard cell C1A may include cell patterns formed on the first track TR21 , the second track TR22 , the third track TR23 , and the fifth track TR25 . Also, for example, the second standard cell C2A may include cell patterns formed on the first track TR21, the second track TR22, the third track TR23, and the fifth track TR25. .

A cell pattern may not be formed in at least one of the first to fifth tracks TR21 to TR25 in each of the first standard cell C1A and the second standard cell C2A. That is, in at least one of the first to fifth tracks TR21 to TR25, a cell pattern may not be formed within the cell boundary of each of the first standard cell C1A and the second standard cell C2A. For example, the cell pattern of the first standard cell C1A may not be formed in the third track TR23, and the cell pattern of the second standard cell C2A may not be formed in the third track TR23. there is. The first standard cell C1A and the second standard cell C2A may not have a full-track structure.

The integrated circuit 10A may include a dummy pattern and/or an extension pattern formed on the second metal layer M2. The dummy pattern and the extension pattern are disposed on the first standard cell C1A and the second standard cell C2A, but may not be included in the cell pattern. The dummy pattern and the extended pattern may be patterns generated in a P&R step (eg, S20 of FIG. 6 ).

Patterns of the second metal layer M2 of the integrated circuit 10A may be arranged to have a designated interval from each other. A spacing between patterns disposed adjacent to each other on the same track of the second metal layer M2 may be defined as a tip-to-tip space, and the tip-to-tip space has a second specified value T2. Patterns of the second metal layer M2 may be disposed. For example, within the integrated circuit 10A constituting one chip or one functional block, the number of second designated values T2 may be set to 10 or less. In an exemplary embodiment, the number of second designated values T2 set in the integrated circuit 10A may be one or two.

In the manufacturing method of the integrated circuit 10A according to the present disclosure, a tip-to-tip of the second metal layer M2 is formed by forming a dummy pattern and an extension pattern in an empty space of the second metal layer M2 in a P&R step. space requirements can be met. That is, the integrated circuit 10A may have a full-track structure in which patterns satisfying a tip-to-tip space requirement are formed on all tracks of the second metal layer M2.

The dummy pattern of the second metal layer M2 may be electrically separated from patterns of other layers. That is, the dummy pattern may be electrically separated from patterns of other metal layers formed on the second metal layer M2 and may be electrically separated from patterns of the first metal layer M1.

In an exemplary embodiment, the dummy pattern may be formed over the first standard cell C1A and the second standard cell C2A. The dummy pattern of the second metal layer M2 may be formed over two or more standard cells disposed adjacent to each other in the Y-axis direction. For example, the dummy patterns may be disposed on the second track TR22 and the third track TR23 and may be disposed on cell boundaries between the first standard cell C1A and the second standard cell C2A. there is.

The extension pattern of the second metal layer M2 may be formed to extend from the cell pattern of the second standard cell C2A. In an exemplary embodiment, the extension pattern of the second metal layer M2 may be a pattern extending from an output pin or an input pin of the second standard cell C2A. A via may be formed on the extension pattern and may be electrically connected to an upper layer of the second metal layer M2, eg, a third metal layer (eg, M3 of FIG. 5). Also, the extension pattern may be electrically connected to the first metal layer M1 through a via.

In an exemplary embodiment, the extension pattern may be formed over the first standard cell C1A and the second standard cell C2A. The extension pattern of the second metal layer M2 may be formed over two or more standard cells disposed adjacent to each other in the Y-axis direction. For example, the extension pattern may be disposed on the fourth track TR24 and may be disposed on a cell boundary between the first standard cell C1A and the second standard cell C2A.

Referring to FIG. 5 compared to FIG. 4 , the integrated circuit 10A′ may include a first standard cell C1A and a second standard cell C2A′ disposed adjacent to each other in the Y-axis direction. In this case, the first standard cell C1A may have a first cell height CH1, and the second standard cell C2A' may have a second cell height CH2 different from the first cell height CH1. can

In an exemplary embodiment, the second cell height CH2 may be smaller than the first cell height CH1. The number of tracks of the first metal layer M1 formed on the second standard cell C2A′ may be smaller than the number of tracks of the first metal layer M1 formed on the first standard cell C1A. . For example, tracks TR11 to TR15 of five first metal layers M1 may be formed on the first standard cell C1A, and four first metal layers may be formed on the second standard cell C2A'. The tracks TR11' to TR14' of (M1) may be formed.

In the integrated circuits 10A and 10A' according to an exemplary embodiment of the present disclosure, first standard cells C1A and second standard cells ( C2A and C2A′), and may include a dummy pattern or an extension pattern that is an additional pattern additionally formed in the P&R step. Accordingly, in manufacturing the integrated circuits 10A and 10A', the degree of freedom of routing may be increased, and it may be easy to form certain patterns on the second metal layer M2 having a full-track structure.

5 is a diagram for explaining an integrated circuit 10B according to an exemplary embodiment of the present disclosure. 5 is a layout diagram for explaining patterns of the third metal layer M3 of the integrated circuit 10B.

Referring to FIG. 5 , the integrated circuit 10B may include a first standard cell C1B and a second standard cell C2B disposed adjacent to each other in the X-axis direction. Each of the first standard cell C1B and the second standard cell C2B may be a single-height cell aligned and disposed in one row, and each of the first standard cell C1B and the second standard cell C2B may be arranged along the Y axis. may have a first cell height CH1 in the direction. However, the integrated circuit 10B is not limited thereto, and the integrated circuit 10B may include a first standard cell C1B and a second standard cell C2B, which are multi-height cells, consecutively arranged in two or more adjacent rows.

Each of the first standard cell C1B and the second standard cell C2B may be defined by a cell boundary. The first standard cell C1B and the second standard cell C2B may be logic cells.

A plurality of tracks on which patterns of the third metal layer M3 are disposed may be defined in the integrated circuit 10B. In this case, the third metal layer M3 may be a metal layer third closest to the substrate among the plurality of metal layers.

The plurality of tracks of the third metal layer M3 may extend in the X-axis direction and may be spaced apart from each other in the Y-axis direction. For example, first to fifth tracks TR31 to TR35 may be formed on the first standard cell C1B and the second standard cell C2B. Conductive patterns extending in the X-axis direction may be formed in the first to fifth tracks TR31 to TR35. However, unlike shown in FIG. 3, the number of tracks of the third metal layer M3 formed to pass inside the cell boundaries of the first standard cell C1B and the second standard cell C2B can be variously modified. do.

The first standard cell C1B and the second standard cell C2B may include patterns of the third metal layer M3. For example, the first standard cell C1B may include cell patterns formed on the first track TR31 , the third track TR33 , the fourth track TR34 , and the fifth track TR35 . Also, for example, the second standard cell C2B may include cell patterns formed on the first track TR31, the third track TR33, the fourth track TR34, and the fifth track TR35. .

A cell pattern may not be formed in at least one of the first to fifth tracks TR31 to TR35 in each of the first standard cell C1B and the second standard cell C2B. That is, in at least one of the first to fifth tracks TR31 to TR35, a cell pattern may not be formed within the cell boundary of each of the first standard cell C1B and the second standard cell C2B. For example, the cell pattern of the first standard cell C1B may not be formed in the second track TR32, and the cell pattern of the second standard cell C2B may not be formed in the second track TR32. there is. The first standard cell C1B and the second standard cell C2B may not have a full-track structure.

The integrated circuit 10B may include a dummy pattern and/or an extension pattern formed on the third metal layer M3. The dummy pattern and the extension pattern are disposed on the first standard cell C1B and the second standard cell C2B, but may not be included in the cell pattern. The dummy pattern and the extended pattern may be patterns generated in a P&R step (eg, S20 of FIG. 6 ).

Patterns of the third metal layer M3 of the integrated circuit 10B may be arranged to have a designated interval from each other. A spacing between patterns disposed adjacent to each other on the same track of the third metal layer M3 may be defined as a tip-to-tip space, and the tip-to-tip space has a third specified value T3. Patterns of the third metal layer M3 may be disposed. For example, within the integrated circuit 10B constituting one chip or one functional block, the third designation value T3 may be set to 10 or less. In an exemplary embodiment, the number of third designated values T3 set in the integrated circuit 10B may be one or two.

In the manufacturing method of the integrated circuit 10B according to the present disclosure, a tip-to-tip of the third metal layer M3 is formed by forming a dummy pattern and an extension pattern in an empty space of the third metal layer M3 in a P&R step. space requirements can be met. That is, the integrated circuit 10B may have a full-track structure in which patterns satisfying a tip-to-tip space requirement are formed on all tracks of the third metal layer M3.

The dummy pattern of the third metal layer M3 may be electrically separated from patterns of other layers. That is, the dummy pattern can be electrically separated from patterns of other metal layers formed on the third metal layer M3 and electrically separated from patterns of the first and second metal layers M1 and M2. can be separated into

In an exemplary embodiment, the dummy pattern may be formed over the first standard cell C1B and the second standard cell C2B. The dummy pattern of the third metal layer M3 may be formed over two or more standard cells disposed adjacent to each other in the X-axis direction. For example, the dummy pattern may be disposed on the first track TR31 and the second track TR32 and may be disposed on a cell boundary between the first standard cell C1B and the second standard cell C2B. there is.

The extension pattern of the third metal layer M3 may be formed to extend from the cell pattern of the first standard cell C1B. In an exemplary embodiment, the extension pattern of the third metal layer M3 may be a pattern extending from an output pin or an input pin of the first standard cell C1B. A via may be formed on the extension pattern and may be electrically connected to an upper layer of the third metal layer M3. Also, the extension pattern may be electrically connected to the first metal layer M1 or the second metal layer M2.

In an exemplary embodiment, the extension pattern may be formed over the first standard cell C1B and the second standard cell C2B. The extension pattern of the third metal layer M3 may be formed over two or more standard cells disposed adjacent to each other in the X-axis direction. For example, the extension pattern may be disposed on the fifth track TR35 and may be disposed on a cell boundary between the first standard cell C1B and the second standard cell C2B.

An integrated circuit 10B according to an exemplary embodiment of the present disclosure includes first standard cells C1B and second standard cells C2B in which empty tracks on which no cell pattern is formed are disposed in the third metal layer M3. and may include a dummy pattern or an extension pattern, which is an additional pattern additionally formed in the P&R step. Accordingly, in manufacturing the integrated circuit 10B, the degree of freedom of routing may be increased, and it may be easy to form certain patterns on the third metal layer M3 having a full-track structure.

6 is a flowchart illustrating a method of fabricating an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 6 , the standard cell library D10 may include information about standard cells, for example, function information, characteristic information, and layout information. The standard cell library D10 may include data DC defining the layout of standard cells. The data DC may include data defining structures of standard cells that perform the same function and have different layouts. The data DC may include data defining the structure of the standard cells C1, C1A, C1B, C2, C2A, and C2B described in FIGS. 1 to 5 or the standard cell FFC described in FIG. 9 . . The data DC includes first data DC1 performing a first function and defining a structure of standard cells having different layouts, and n-th data DCn performing an n-th function and defining a structure of standard cells having different layouts. , n is a natural number of 2 or more).

Steps S10 and S20 are steps of designing an integrated circuit (IC), and layout data D30 may be generated from RTL data D11. The integrated circuit (IC) may be at least one of the integrated circuits 10 , 10A and 10B of FIGS. 1 to 5 and the integrated circuit 10C of FIG. 10 . In step S10, a logic synthesis operation may be performed to generate netlist data D20 from RTL data D11. For example, a semiconductor design tool (eg, a logic synthesis module) refers to a standard cell library D10 from RTL data D11 written as VHDL (VHSIC Hardware Description Language) and HDL (Hardware Description Language) such as Verilog. By performing logic synthesis by doing so, it is possible to generate netlist data D20 including a bitstream or netlist. The standard cell library D10 performs the same function and may include data (DC) defining the structure of standard cells having different layouts. can be included in

In step S20, a Place & Routing (P&R) operation for generating layout data D30 from netlist data D20 may be performed. Layout data D30 may have a format such as, for example, GDSII, and may include geometric information of standard cells and interconnections. In an exemplary embodiment, step S20 may include steps S21 to S23 of FIG. 7 and may include steps S231 and S232 of FIG. 8 .

The semiconductor design tool (eg, P&R module) may arrange a plurality of standard cells by referring to the standard cell library D10 from the netlist data D20 in step S20. The semiconductor design tool may select one of the standard cell layouts defined by the netlist D103 by referring to the data DC, and may arrange the selected standard cell layout.

In addition, the semiconductor design tool may perform a routing operation, which is an operation of generating interconnections, in step S20. “Routing” may be an operation of placing wiring layers and vias required to properly connect the placed standard cells according to design rules for integrated circuits. The interconnection may electrically connect the output pin and the input pin of the standard cell, and may include, for example, a conductive pattern formed on at least one via and at least one metal layer. Patterns formed on metal layers of different levels may be electrically connected to each other through vias made of a conductive material. In this case, the metal layer may include metal as a conductive material.

In step S30, Optical Proximity Correction (OPC) may be performed. OPC may refer to an operation to form a pattern of a desired shape by correcting distortion phenomena such as refraction caused by the characteristics of light in photolithography included in a semiconductor process for manufacturing an integrated circuit (IC). , the pattern on the mask may be determined by applying OPC to the layout data D30. In an exemplary embodiment, the layout of the integrated circuit (IC) may be limitedly modified in step S30, and the limited modification of the integrated circuit (IC) in step S30 is performed after optimizing the structure of the integrated circuit (IC). As a treatment, it may be referred to as design polishing.

In step S40, an operation of manufacturing a mask may be performed. For example, as OPC is applied to the layout data D30, patterns on a mask may be defined to form patterns formed on a plurality of layers, and at least one mask (or , photomask) can be fabricated.

In step S50, an operation of fabricating an integrated circuit (IC) may be performed. For example, an integrated circuit (IC) may be manufactured by patterning a plurality of layers using at least one mask fabricated in step S40 . Step S50 may include steps S51, S53, and S55, and may include a deposition process, an etching process, an ion process, a cleaning process, and the like. Further, step S50 may include a packaging process of mounting a semiconductor device on a PCB and sealing it with a sealing material, or may include a test process of testing the semiconductor device or package.

In step S51, a front-end-of-line (FEOL) process may be performed. FEOL may refer to a process of forming individual elements, eg, transistors, capacitors, resistors, and the like, on a substrate during the manufacturing process of an integrated circuit (IC). For example, FEOL includes planarizing and cleaning the wafer, forming trenches, forming wells, forming gate lines, forming source and drain regions, and the like. can do.

In step S53, a middle-of-line (MOL) process may be performed. It may refer to a process of forming a connecting member for connecting individual devices produced through the FEOL process in a standard cell. For example, the MOL process may include forming an active contact on an active region, forming a gate contact on a gate line, forming a via on the active contact and the gate line, and the like.

In step S55, a back-end-of-line (BEOL) process may be performed. BEOL may refer to a process of interconnecting individual elements, eg, transistors, capacitors, resistors, and the like, in the manufacturing process of an integrated circuit (IC). For example, BEOL includes silicidation of gate, source and drain regions, adding dielectric, planarization, forming holes, forming metal layers, and forming vias between metal layers. A step of forming, a step of forming a passivation layer, and the like may be included. The integrated circuit (IC) can then be packaged in a semiconductor package and used as a component in various applications.

7 is a flowchart illustrating a method of fabricating an integrated circuit according to an exemplary embodiment of the present disclosure. Step S20 of FIG. 7 is an embodiment of step S20 of FIG. 6 and may include steps S21 to S23.

Referring to FIG. 7 , in step S21, a plurality of standard cells including cell patterns may be disposed. For example, in step S21, at least one of the standard cells C1, C1A, C1B, C2, C2A, and C2B described in FIGS. 1 to 5 may be disposed.

In operation S22, it may be determined whether a distance between adjacent patterns formed on the same track among a plurality of tracks defined on a specific metal layer exceeds a reference value. That is, it may be determined whether the width (tip-to-tip space) of a space in which cell patterns of a plurality of standard cells among a plurality of tracks are not formed exceeds a reference value.

The reference value at this time may be determined according to the specified value of the tip-to-tip space defined in the specific metal layer. A reference value may be set equal to or greater than the designated value, and for example, when a tip-to-tip space is set to have a plurality of designated values, the largest value among the plurality of designated values may be set as the reference value. .

When the distance between adjacent patterns formed on the same track in a specific metal layer exceeds a reference value, an additional pattern may be formed between adjacent patterns (ie, an empty area) in step S23. By forming additional patterns, the tip-to-tip space requirements required for a particular metal layer can be met.

Steps S22 and S23 may be performed on at least some of the plurality of metal layers formed on the integrated circuit. For example, as shown in FIG. 1, it may be performed on the first metal layer M1, or as shown in FIGS. 3 and 4, it may be performed on the second metal layer M2. As shown in FIG. 5, it may be performed on the third metal layer M3.

8 is a flowchart illustrating a method of fabricating an integrated circuit according to an exemplary embodiment of the present disclosure. Step S23 of FIG. 8 is an embodiment of step S23 of FIG. 7 and may include steps S231 and S232. Step S23 described in FIG. 8 may be performed on at least one metal layer among a plurality of metal layers formed in the integrated circuit.

Referring to FIG. 8 , in step S231, an extension pattern extending from the cell pattern of the standard cell may be formed. In an exemplary embodiment, the extension pattern may be formed to extend from the input/output pin of the standard cell.

The extension pattern may be formed inside the cell boundary of the standard cell, or may be formed over the standard cell and standard cells adjacent to the standard cell. This may be determined according to the interval of the empty area in the track where the extended pattern is to be arranged.

In operation S231 , vias may be further formed on the additionally formed extension patterns to connect the extension patterns to patterns of other layers. For example, a via may be formed in contact with the extension pattern to connect a pattern of an upper layer of a metal layer on which an extension pattern is formed, or, for example, a pattern of a lower layer of a metal layer on which an extension pattern is formed. A via may be formed to contact the extension pattern to connect the .

In step S232, a dummy pattern electrically separated from other patterns may be formed. For example, the dummy pattern may be electrically separated from other patterns of the metal layer on which the dummy pattern is to be formed, and may also be electrically separated from patterns formed on other metal layers. Therefore, the dummy pattern may not be connected to the via.

As steps S231 and S233 are performed, even if the first logic cell and the second logic cell including the same cell patterns are disposed in step S21 of FIG. 7 , the extended pattern is disposed on the first logic cell and the second logic cell. Alternatively, the dummy patterns may be different from each other. That is, in the step of forming the additional pattern (step S23), a first additional pattern is formed in the first logic cell, and a second additional pattern having a different pattern from the first additional pattern is formed in the second logic cell. steps may be included.

The manufacturing method of an integrated circuit according to the present disclosure may satisfy a tip-to-tip space requirement of a plurality of metal layers by forming an additional pattern including at least one of an extension pattern and a dummy pattern among a plurality of tracks. . That is, the integrated circuit 10 may include a metal layer having a full-track structure in which patterns satisfying a tip-to-tip space requirement are formed on all tracks.

9 and 10 are diagrams for explaining a method of manufacturing an integrated circuit 10C according to an exemplary embodiment of the present disclosure. FIG. 9 is a layout of the standard cell (FFC), and FIG. 10 is a layout of the integrated circuit 10C in which the standard cell (FFC) of FIG. 9 is disposed. 9 and 10 describe patterns of the first metal layer M1, but the same description may be applied to a plurality of metal layers other than the first metal layer M1.

Referring to FIG. 9 , the standard cell FFC may be a flip-flop cell in which a flip-flop is implemented. The standard cells FFC may be multi-height cells arranged in the first row R1 and the second row R2. Data defining the layout of the standard cell FFC may be stored in the cell library D10 of FIG. 6 .

First to tenth tracks TR11 to TR19 and TR10 on which the first metal layer M1 is disposed may be formed on the standard cell FFC. The first to fifth tracks TR11 to TR15 may be disposed in the first row R1 , and the sixth to tenth tracks TR16 to TR19 and TR10 may be disposed in the second row R2 .

The standard cell FFC may include cell patterns formed on the first metal layer M1. The standard cell FFC may further include vias V1 as cell patterns that contact cell patterns of the first metal layer M1 and are connected to patterns of an upper layer of the first metal layer M1. In addition, the standard cell FFC may further include vias connecting the cell patterns to the gate line or the active region below the cell patterns of the first metal layer M1. An M1 cut region in which cell patterns of the first metal layer M1 are cut may be defined in the standard cell FFC.

7 to 10 , the standard cell FFC may be disposed in the integrated circuit 10C in step S21, and the first to fourth adjacent cells STC1 to STC4 may be disposed adjacent to the standard cell FFC. can be placed. After the standard cell FFC and the first to fourth adjacent cells STC1 to STC4 are disposed, additional patterns may be formed on the first metal layer M1 in step S23. Also, in step S23, vias V1 connecting the first metal layer M1 and an upper layer of the first metal layer M1 may be additionally formed, and cell patterns and additional patterns of the first metal layer M1 may be formed. An M1 cut region to be cleaved can be further defined.

For example, in the first to third, sixth, seventh, ninth, and tenth tracks TR11 to TR13, TR16, TR17, TR19, and TR10, cell patterns of the standard cells FFC are not formed. The width may exceed the standard value. In step S23 , extended patterns and dummy patterns may be formed on the first to third, sixth, seventh, ninth, and tenth tracks TR11 to TR13, TR16, TR17, TR19, and TR10. An extension pattern may be formed on the tenth track TR10, and dummy patterns may be formed on the first to third, sixth, seventh, ninth, and tenth tracks TR11 to TR13, TR16, TR17, TR19, and TR10. can be formed

The extension pattern may be formed to extend from the cell pattern of the standard cell FFC. A via V1 may be formed on the extension pattern to connect to a pattern of an upper layer.

The first dummy pattern DP1 may be formed over the standard cell FFC and the first neighboring cell STC1, and the second dummy pattern DP2 may be formed over the standard cell FFC and the second neighboring cell STC2. It can be formed over the phase. The first dummy pattern DP1 may extend unbroken at the cell boundary of the first adjacent cell STC1. That is, the first dummy pattern may be formed over at least three standard cells including the standard cell FFC and the first adjacent cell STC1.

11 is a diagram for explaining a method of manufacturing an integrated circuit (IC) according to an exemplary embodiment of the present disclosure.

Referring to FIG. 11 , an integrated circuit (IC) may include a first pattern 101 and a second pattern 102 extending in a specific direction. For example, the first pattern 101 and the second pattern 102 may be patterns of the first metal layer M1 extending in the X-axis direction as described in FIG. 1 , and FIGS. 3 and 4 As described above, it may be a pattern of the second metal layer M2 extending in the Y-axis direction, or a pattern of the third metal layer M3 extending in the X-axis direction.

The first pattern 101 and the second pattern 102 may be adjacent to each other. For example, when the first pattern 101 and the second pattern 102 are patterns of the first metal layer M1 of FIG. 1 , the first pattern 101 is disposed on the first track TR11. and the second pattern 102 may be disposed on the second track TR12.

In an exemplary embodiment, the first pattern 101 and the second pattern 102 may be formed using different masks. The first pattern 101 may be formed using the first mask MK1, and the second pattern 102 may be formed using the second mask MK2. For example, when the first pattern 101 and the second pattern 102 are patterns of the first metal layer M1 of FIG. 1 , the first, third, and fifth tracks TR11, TR13, and TR15 ) may be formed using the first mask MK1, and patterns of the second and fourth tracks TR12 and TR14 may be formed using the second mask MK2. However, the method of manufacturing an integrated circuit according to the present disclosure is not limited thereto, and patterns of metal layers may be formed using three or more different masks, or all patterns of a specific metal layer may be formed using one mask. It could be.

The first mask MK1 and the second mask MK2 may be generated in step S40 of FIG. 6 . Specifically, by performing various semiconductor processes on a semiconductor substrate such as a wafer using the first mask MK1 and the second mask MK2, the first pattern 101 and the second pattern ( 102) can be formed. A desired pattern may be formed on a semiconductor substrate or a material layer through a patterning process using the first mask MK1 and the second mask MK2 .

12 is a block diagram illustrating a computing system for design of an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 12 , a computing system for designing an integrated circuit (hereinafter referred to as an 'integrated circuit design system') 100 includes a processor 110, a memory 130, an input/output device 150, and a storage device 170. and bus 190. The integrated circuit design system 100 may perform an integrated circuit design operation including steps S10 and S20 of FIG. 6 , steps S21 to S23 of FIG. 7 , and steps S231 and S232 of FIG. 8 . It can perform integrated circuit design operations including. In an exemplary embodiment, the integrated circuit design system 100 may be implemented as an integrated device, and thus may be referred to as an integrated circuit design apparatus. The integrated circuit design system 100 may be provided as a dedicated device for designing an integrated circuit of a semiconductor device, or may be a computer for driving various simulation tools or design tools. The integrated circuit design system 100 may be a fixed computing system such as a desktop computer, a workstation, or a server, or a portable computing system such as a laptop computer.

The processor 110 may be configured to execute instructions that perform at least one of various operations for designing an integrated circuit. For example, the processor 110 may be any instruction set (eg, IA-32 (Intel Architecture-32), 64-bit extensions IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.) The processor 110 may include a bus 190 ), it is possible to perform communication with the memory 130, the input/output device 150, and the storage device 170. The processor 110 uses the synthesis module 131 loaded in the memory 130, Place and Routing (P&R) ) module 132 and the design rule check (DRC) module 133, it is possible to execute the design operation of the integrated circuit.

The memory 130 may store a synthesis module 131 , a P&R module 132 , and a DRC module 133 . The synthesis module 131 , the P&R module 132 , and the DRC module 133 may be loaded into the memory 130 from the storage device 170 . The synthesis module 131 may be, for example, a program including a plurality of instructions for performing a logic synthesis operation according to step S10 of FIG. 6 . For example, the P&R module 132 may be a program including a plurality of instructions for performing a layout design operation according to step S20 of FIG. 6 .

The DRC module 133 may determine whether a design rule error exists. The DRC module 133 may be, for example, a program including a plurality of instructions for performing a DRC operation including a design rule verification operation according to step S22 of FIG. 7 . If there are design rule violations, the P&R module 132 may adjust the layout of the placed cells. If there is no design rule error, the layout design of the integrated circuit can be completed. In an exemplary embodiment, the DRC module 133 may determine whether patterns formed on tracks defined in a specific metal layer satisfy a tip-to-tip space requirement. The DRC module 133 may form an additional pattern when a distance between adjacent patterns formed on the same track exceeds a reference value.

The memory 130 is a volatile memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic RAM), PRAM (Phase Change RAM), ReRAM (Resistive RAM), NFGM (Nano Floating Gate Memory), PoRAM (Polymer Random Access Memory), magnetic RAM (MRAM), ferroelectric RAM (FRAM), and flash memory.

The input/output device 150 may control user input and output from user interface devices. For example, the input/output device 150 may include an input device such as a keyboard, mouse, or touch pad to receive input data defining an integrated circuit. For example, the input/output device 150 may include an output device such as a display or a speaker to display arrangement results, routing results, layout data, DRC results, and the like.

The storage device 170 may store programs such as the synthesis module 131, the P&R module 132, and the DRC module 133, and the programs are stored in the storage device 170 before being executed by the processor 110. A program or at least a portion thereof may be loaded into memory 130 . The storage device 170 may also store data to be processed by the processor 110 or data processed by the processor 110 . For example, the storage device 170 stores data to be processed by programs such as the synthesis module 131, the P&R module 132, and the DRC module 133 (eg, the standard cell library 171, the netlist data, etc.) and data generated by a program (eg, DRC result data, layout data, etc.) may be stored. The standard cell library 171 stored in the storage device 170 may be the standard cell library D10 of FIG. 6 .

For example, the storage device 170 may include non-volatile memory such as electrically erasable programmable read-only memory (EEPROM), flash memory, PRAM, RRAM, MRAM, FRAM, or the like, or a memory card (MMC, eMMC, SD). , MicroSD, etc.), a solid state drive (SSD), a hard disk drive (HDD), a magnetic tape, an optical disk, or a magnetic disk. Also, the storage device 170 may be removable from the integrated circuit design system 100 .

As above, exemplary embodiments have been disclosed in the drawings and specifications. Although the embodiments have been described using specific terms in this specification, they are only used for the purpose of explaining the technical idea of the present disclosure, and are not used to limit the scope of the present disclosure described in the claims. . Therefore, those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

Claims (20)

A method of manufacturing an integrated circuit comprising a plurality of stacked metal layers, comprising:
disposing a plurality of standard cells each including cell patterns formed on the plurality of metal layers; and
Forming an additional pattern on a specific metal layer among the plurality of metal layers;
In the specific metal layer, patterns extending in a first direction are respectively formed and a plurality of tracks spaced apart from each other in a second direction are defined,
The forming of the additional pattern may include forming the additional pattern between adjacent patterns when a distance between adjacent patterns formed on the same track among the plurality of tracks exceeds a reference value. A method for manufacturing an integrated circuit. According to claim 1,
The forming of the additional pattern may include forming a dummy pattern formed over a first standard cell and a second standard cell disposed adjacent to each other among the plurality of standard cells and electrically separated from other patterns. A method of manufacturing an integrated circuit, characterized in that for doing. According to claim 2,
The method of manufacturing an integrated circuit, characterized in that the first standard cell and the second standard cell are logic cells. According to claim 1,
The method of manufacturing an integrated circuit according to claim 1 , wherein the forming of the additional pattern includes forming an extension pattern extending from a cell pattern of a first standard cell among the plurality of standard cells. According to claim 4,
The method of manufacturing an integrated circuit, characterized in that the forming of the extension pattern comprises forming an extension pattern formed over the first standard cell and a second standard cell adjacent to the first standard cell. According to claim 4,
After the step of forming the extension pattern, forming a via formed to contact the extension pattern to connect the extension pattern and a pattern of an upper layer of the specific metal layer Of the integrated circuit, characterized in that it further comprises manufacturing method. According to claim 1,
The method of manufacturing an integrated circuit, characterized in that adjacent patterns formed on the same track among the plurality of tracks are spaced apart from each other by at least one predetermined value. According to claim 1,
The method of manufacturing an integrated circuit, wherein the plurality of standard cells receives power from a plurality of power rails extending in the first direction. According to claim 1,
The method of manufacturing an integrated circuit, wherein the plurality of standard cells receive power from a plurality of power rails extending in the second direction. An integrated circuit comprising a plurality of stacked metal layers,
first logic cells and second logic cells each including cell patterns formed on the plurality of metal layers; and
A dummy pattern formed over the first logic cell and the second logic cell in a specific metal layer among the plurality of metal layers and electrically separated from other patterns;
In the specific metal layer, patterns extending in a first direction are respectively formed and a plurality of first tracks spaced apart from each other in a second direction are defined,
wherein patterns are formed on all tracks of the plurality of first tracks. According to claim 10,
The integrated circuit, characterized in that the specific metal layer is the lowest layer among the plurality of metal layers. According to claim 10,
wherein the first logic cell and the second logic cell have the same cell heights in the first direction. According to claim 10,
The first logic cell and the second logic cell have different cell heights in the first direction;
In the lower metal layer of the specific metal layer, patterns extending in the second direction are formed and a plurality of second tracks spaced apart from each other in the first direction are defined,
The number of second tracks formed to pass into the cell boundary of the first logic cell among the plurality of second tracks, and second tracks formed to pass into the cell boundary of the second logic cell among the plurality of second tracks An integrated circuit, characterized in that the number of is different from each other. According to claim 10,
characterized in that adjacent patterns formed on the same track among the plurality of first tracks are spaced apart from each other by at least one predetermined value. According to claim 10,
and an extension pattern formed on the specific metal layer and extending from the cell pattern of the first logic cell. An integrated circuit comprising a plurality of stacked metal layers,
first standard cells and second standard cells each including cell patterns formed on the plurality of metal layers; and
An extension pattern formed over the first standard cell and the second standard cell in a specific metal layer among the plurality of metal layers and extending from the cell pattern of the first standard cell;
In the specific metal layer, patterns extending in a first direction are respectively formed and a plurality of first tracks spaced apart from each other in a second direction are defined,
characterized in that adjacent patterns formed on the same track among the plurality of first tracks are spaced apart from each other by at least one predetermined value. According to claim 16,
The integrated circuit, characterized in that the specific metal layer is the lowest layer among the plurality of metal layers. According to claim 16,
wherein the first standard cell and the second standard cell have the same cell heights in the first direction. According to claim 16,
wherein the first standard cell and the second standard cell have different cell heights in the first direction. According to claim 19,
and a dummy pattern formed on the first standard cell and electrically separated from other patterns on the specific metal layer.

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