CN104134460B - A kind of nonvolatile memory reading circuit based on dynamic reference - Google Patents
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Abstract
A kind of nonvolatile memory reading circuit based on dynamic reference, it is by load circuit PR0 and PR1, and dynamic reference cells, NMOS clamp transistors NC0 and NC1, bit line selecting switch MUX and voltage comparison amplifier VC are formed；The source electrode of NMOS clamp transistors is through the MUX connections of bit line selecting switch nonvolatile memory data cell and dynamic reference cells to be read, and the grid of NMOS clamp transistors is by VG_clampSignal is controlled, and the drain electrode of its connection load transistor that drains, load transistor source electrode meets voltage source Vdd, and grid is by VG_loadSignal is controlled, and data cell reads voltage with dynamic reference cells branch road at load transistor source electrode, and accesses two inputs of voltage comparison amplifier, while VdataThe grid of two transistors of dynamic reference cells is also connected with, for controlling the resistance of dynamic reference cells.The present invention solves the problems, such as the parameter error of nonvolatile memory, improves and reads judgement allowance, so as to improve its reliability.
Description
Technical field
The present invention relates to a kind of nonvolatile memory reading circuit based on dynamic reference, for improving nonvolatile memory
Reading reliability, belong to nonvolatile memory technical field.
Background technology
New nonvolatile memory technology in recent years, such as spin-transfer torque magnetic RAM (Spin Transfer
Torque Magnetic Random Access Memory, STT-MRAM), resistive formula random access memory (Resistive
Random Access Memory, RRAM), with phase-change random access memory (Phase Change Random Access
Memory, PCRAM) etc. continue to develop, progressively initially enter actual production and application stage.These nonvolatile memory technologies
Basic storage principle be resistance states by changing its memory cell, allow it in high-resistance state RHWith low resistance state RL
Between switch over, so as to utilize this property store digital information, such as RHCorresponding data bit " 1 ", RLCorresponding data bit
" 0 ", or vice versa.Typical memory cell (has R by data storage sectionLWith RHTwo kinds of Resistance states, are represented by one
Individual variable resistor RX) formed with access control part (NMOS wordline selection transistor), referred to as 1R1T structures, as shown in Figure 1.
In general, a memory includes two kinds of memory cell, one kind is data cell, and its resistance states is variable, is designated as Rdata, use
In storage binary data；Another kind is reference unit, and its resistance states is, it is known that be designated as Rref, during for reading data, to number
Judgement reference is provided according to unit.When reading data, by applying identical electric current (or electricity simultaneously to data cell and reference unit
Pressure) detect their corresponding voltages (or electric current), then contrasted, you can judge the information stored in data cell,
As shown in Figure 2.More specifically, if data cell is low resistance state RL, then can detect the voltage V of data celldata=
VL, it is less than the voltage V of reference unitref, then it is " 0 " to adjudicate data bit；If data cell is high-resistance state RH, then can examine
Measure the voltage V of data celldata=VH, it is more than the voltage V of reference unitref, then it is " 1 " to adjudicate data bit, or instead
Also may be used.
Ideally, all memory cell in same memory all have identical resistance value in high-resistance state
RH_ideal, and all there is identical resistance value R in low resistance stateL_ideal, now adjudicate allowance to obtain optimal reading
(Sensing Margin (SM), it is defined as reference unit voltage (or electric current) and the difference of data cell voltage (or electric current)
The minimum value of absolute value), the resistance value R of reference unitref_idealIt must is fulfilled for Rref_ideal=(RH_ideal+RL_ideal)/2.But
It is, in a practical situation, due to the presence of technological parameter deviation, especially under deep submicron process, RH, RLAnd RrefReality
Actual value may deviate target design value, be reduced so as to cause to read judgement allowance.It can not overcome reading when reading judgement allowance
During circuit input mismatch in itself, then there may be read error, the digital independent reliability of memory is influenceed.
The content of the invention
First, goal of the invention：
The problem of allowance reduces is adjudicated because parameter error causes to read for the nonvolatile memory mentioned in above-mentioned background,
The present invention proposes a kind of nonvolatile memory reading circuit based on dynamic reference, and it overcomes the deficiencies in the prior art, solution
Parameter error problem existing for volatile memory by no means, to improve the reading of nonvolatile memory judgement allowance, so as to improve it
Reliability.
2nd, technical scheme：
A kind of technical scheme of the nonvolatile memory reading circuit based on dynamic reference of the present invention is that one kind is based on dynamic
The nonvolatile memory reading circuit of reference, as shown in Figure 4.It is characterized in that reading of the reading circuit according to data cell
Voltage VdataTo adjust the grid voltage of nmos pass transistor in dynamic reference cells, so as to change the resistance of dynamic reference cells,
Obtain maximum reading judgement allowance.The reading circuit is brilliant by load circuit (PR0 and PR1), dynamic reference cells, NMOS clampers
Body pipe (NC0 and NC1), bit line selecting switch (MUX) and voltage comparison amplifier (VC) composition.Position connection between them is closed
System and signal trend are：The source electrode of NMOS clamp transistors connects non-volatile storage to be read through bit line selecting switch (MUX)
Device data cell and dynamic reference cells, the grid of NMOS clamp transistors is by VG_clampSignal is controlled, its connection that drains
The drain electrode of load transistor, load transistor source electrode meet voltage source Vdd, and grid is by VG_loadSignal is controlled, data cell branch
Road and reading voltage of the dynamic reference cells branch road at load transistor source electrode, are designated as V respectivelydataWith Vref, they connect simultaneously
Enter two inputs of voltage comparison amplifier, while VdataThe grid of two transistors in dynamic reference cells is also connected with, is used
In the resistance of control dynamic reference cells.When performing read operation, electric current is had from Vdd, through load circuit, NMOS clamper crystal
Pipe, bit line selecting switch, nonvolatile memory data cell and dynamic reference cells, eventually flow to low potential Vss.Due to data
Unit is different from the resistance of dynamic reference cells, therefore can produce different electric currents in two branch roads, is designated as I respectivelydataWith
Iref, so that in the presence of load circuit, different voltages are produced between load circuit and NMOS clamp transistors, i.e.,
VdataWith Vref, they are connected to the input of two of voltage comparison amplifier, are compared and amplify simultaneously, final output two
Binary data signal.Because data cell has different resistance states, i.e. RLWith RH, therefore VdataAlso have two it is different
Value, i.e. VLWith VH.When the resistance states of data cell are low resistance state RLWhen, corresponding voltage value Vdata=VL, therefore, when the voltage connects
Into dynamic reference cells during the grid of transistor, dynamic reference cells have higher resistance, so that joining corresponding to it
Examine voltage VrefIncrease；Conversely, when the resistance states of data cell are high-impedance state RHWhen, corresponding voltage value Vdata=VH, now move
State reference unit has relatively low resistance, so that its corresponding reference voltage VrefReduce, as shown in accompanying drawing 5-2, can see
The resistance sizes of dynamic reference cells can be adjusted according to the resistance states of data cell to the reading circuit, are read so as to increase
Adjudicate allowance.
The load circuit is PR0 and PR1, by VG_loadSignal is controlled, for providing data cell and dynamic reference
Conversion of the cell current to voltage；It can also be not construed as limiting with other resistive devices, specific implementation.
The NMOS clamp transistors are NC0 and NC1, by VG_clampSignal is controlled, for clamp down on data cell with
The bit-line voltage of dynamic reference cells, write operation by mistake is avoided, while prevent data cell with dynamic reference cells because of bit-line voltage
It is excessive and damage.
The bit line selecting switch (MUX) is used to select data cell and dynamic reference cells to be read.It is specific real
The mode of applying is not construed as limiting.
The voltage amplification comparator is used to compared with voltage corresponding to dynamic reference cells and put data cell
Greatly, final binary data signal is exported, its embodiment is not construed as limiting.
The dynamic reference cells are a kind of cores of the nonvolatile memory reading circuit based on dynamic reference of the present invention
Part, as shown in figure 3-2, it is made up of (RN1-RN4) 4 data storage sections (M1-M4) and 4 nmos pass transistors.Wherein
M1, M3 are configured to low resistance state, and M2, M4 are configured to high-impedance state, or M1, M2 are configured to low resistance state, and M3, M4 are configured to
High-impedance state, it can thus be concluded that to high low resistance state memory cell conductance or the arithmetic average of resistance.RN1-RN2's (or RN3-RN4)
Grid meets wordline WL, and for the access control of dynamic reference cells, and RN3-RN4 (or RN1-RN2) grid meets Vdata, it is used for
Control the resistance of dynamic reference cells.Wherein M1-M4 resistance states configuration is not construed as limiting.Accompanying drawing 3-2 is only most basic two
The schematic diagram for the dynamic reference cells that row two arranges, dynamic reference cells can be any numbers according to storage part and any NMOS
Transistor combination forms.
3rd, advantage and effect:
The present invention proposes a kind of nonvolatile memory reading circuit based on dynamic reference, can solve non-volatile storage
Device, so as to improve the reading of nonvolatile memory judgement allowance, is improved due to device mismatch problem caused by technological parameter deviation
Data reliability.
Brief description of the drawings
Fig. 1 is nonvolatile memory 1R1T memory cell structure schematic diagrames.
Fig. 2 is traditional reading circuit embodiment schematic diagram of nonvolatile memory.
Fig. 3-1 is the conventional reference cell schematics of nonvolatile memory.
Fig. 3-2 is dynamic reference cells schematic diagram proposed by the present invention.
Fig. 4 is a kind of nonvolatile memory reading circuit schematic diagram based on dynamic reference proposed by the present invention.
Fig. 5-1 is that allowance schematic diagram is adjudicated in the reading of traditional static reading circuit.
Fig. 5-2 is that allowance schematic diagram is adjudicated in the reading proposed by the present invention based on dynamic reference.
Wherein, the parameter definition in Fig. 1 to Fig. 5 is：
BL：Bit line is represented, is Bit-Line abbreviation；
WL：Wordline is represented, is Word-Line abbreviation；
SL：Expression source line, it is Source-Line abbreviation；
SM：Represent to read judgement allowance, the abbreviation for being Sensing Margin；
RX：Memory cell data storage part is represented, is expressed as a variable resistor；
RH：Represent resistance value when memory cell data storage is partially in high-resistance state；
RL：Represent resistance value when memory cell data storage is partially in low resistance state；
NMOS：N-type metal-oxide semiconductor (MOS) is represented, is N-Mental-Oxide-Semiconductor abbreviation；VC：
Voltage comparison amplifier is represented, is Voltage Comparator abbreviation；
Vdd：Represent supply voltage；
Vss：Represent source line voltage；
Rdata：The Resistance states of data unit data storage part are represented, can be RLOr RH；
Rref：The Resistance states of virtual reference cell data storage part are represented, ideal value is (RH+RL)/2；
Idata：The electric current of data cell is flowed through in expression；
Vdata：Represent voltage corresponding to data cell branch road；
Vref：Represent voltage corresponding to reference unit branch road；
Iref：The electric current of reference unit branch road is flowed through in expression；
S0-S1：Represent bit line selecting switch；
NA0-NA1：Represent NMOS wordline selection transistors；
NC0-NC1：Represent NMOS clamp transistors；
PR0-PR1：Represent PMOS load transistor；
VL-VH：Represent that data cell is in R respectivelyLState and RHMagnitude of voltage corresponding to the branch road of state；
VG_clamp：Represent clamp transistor grid-control voltage；
VG_load：Represent load transistor gate control voltage；
VG_access：Represent word line transistors grid-control voltage；
M1-M4：Represent data storage section in reference unit；
RN1-RN4：Represent the nmos pass transistor in reference unit；
Embodiment
Referring to the drawings, a kind of essence of the nonvolatile memory read method based on dynamic reference of the present invention is further illustrated
Property feature.Detailed exemplary embodiment is disclosed that, its specific CONSTRUCTED SPECIFICATION and function detail are only to represent that description is shown
The purpose of example embodiment, therefore, can by it is many it is selectable in the form of implement the present invention, and the present invention is not construed as
The example embodiment herein proposed is limited only to, but all changes fallen within the scope of the present invention, equivalent should be covered
And refill.In addition, the well-known element of the present invention, device and sub-circuit will not be described in detail or will omit, with
Exempt to obscure the correlative detail of embodiments of the invention.
Fig. 1 is nonvolatile memory 1R1T memory cell structure schematic diagrames.Nonvolatile memory 1R1T units are deposited by data
Storage part (i.e. variable resistor RX) formed with access control part (nmos pass transistor), wherein RXCan be in high-resistance state RHWith it is low
Resistance states RLBetween switch over, so as to utilize this property store digital information, such as RHCorresponding data bit " 1 ", RLCorresponding number
According to bit " 0 ", or vice versa.Nmos pass transistor controls for memory unit access, and its grid meets wordline WL (Word-
Line), (or source electrode) is drained via RXBit line BL (Bit-Line) is followed by, source electrode (or drain electrode) meets source electrode line SL (Source-
Line).By the opening and closing for the i.e. controllable nmos pass transistor of voltage for controlling wordline, so as to control the selection of nonvolatile memory cell
Whether, more specifically, when wordline is high level, nmos pass transistor is in the conduction state, and memory cell may have access to, and it can be entered
Row read-write operation, and when wordline is low level, nmos pass transistor is in nonconducting state, memory cell inaccessible.
Fig. 2 is the traditional static reading circuit embodiment schematic diagram of nonvolatile memory.It is born by voltage comparison amplifier
Carry circuit (PR0 and PR1), NMOS clamp transistors (NC0 and NC1) composition.When being read, storage control passes through word
Line selects data cell (its resistance states R to be read with bit line selecting switch (S0 and S1)dataIt is unknown, it is RHOr one in RL
Kind) with corresponding reference unit, while pass through clamp transistor grid-control voltage VG_clampControl bit line voltage, prevents data
Unit damages or caused write operation by mistake with reference unit because bit-line voltage is too high.In the presence of bit-line voltage, it can produce
Flow through the electric current (I of data celldata) with flowing through the electric current (I of reference unitref).Then (its load resistance is remembered in load circuit
It is worth for Rload) in the presence of, IdataWith IrefIt is converted into the voltage V of corresponding data celldata=Idata×RloadIt is single with reference
The voltage V of memberref=Iref×Rload, because data cell from reference unit has different resistance values, therefore Idata≠Iref, from
And Vdata=Idata×Rload≠Vref=Iref×Rload.Last VdataWith VrefAccessed voltage comparison amplifier simultaneously two
Input, it is compared and amplifies, exports final binary data signal.More specifically, if data cell is low resistance
State RL, then Vdata=VL<Vref, output data " 0 "；If instead data cell is high-resistance state RH, then Vdata=VH>Vref, it is defeated
Go out data " 1 ".
It is between memory cell and each due to larger fabrication process parameters deviation under deep submicron process
Device mismatch (such as R between transistor all be presentH, RLAnd RrefActual value may deviate target design value, data cell
The load transistor resistance value of branch road and reference unit branch road is unequal), voltage comparison amplifier there is also input mismatch etc., this
A little device parameters mismatches have a strong impact on the reading judgement allowance of reading circuit, when reading judgement allowance voltage ratio can not be overcome relatively to put
During the input mismatch of big device, it is possible to cause read error, influence the reliability of nonvolatile memory.
Fig. 3-1 and Fig. 3-2 is respectively the conventional reference unit of nonvolatile memory and dynamic reference list proposed by the present invention
First schematic diagram.In traditional reference unit, connected again with a nmos pass transistor after M1-M4 connection in series-parallel, its resistance
State cannot change.Ideal value is RNMOS+(RH+RL)/2, wherein RNMOSFor the resistance value of nmos pass transistor.And the present invention
The grid of dynamic reference cells, wherein RN1-RN2 (or RN3-RN4) meets Vdata, therefore its resistance states can be according to be read
The resistance value of data cell is adjusted, and judgement allowance is read so as to dynamically increase.
4 read below in conjunction with the accompanying drawings with accompanying drawing 5, a kind of nonvolatile memory based on dynamic reference of the detailed description present invention
The embodiment of circuit.
As shown in Figure 4, a kind of nonvolatile memory reading circuit based on dynamic reference of the present invention, it is by load circuit
(PR0 and PR1), dynamic reference cells, NMOS clamp transistors (NC0 and NC1), bit line selecting switch (MUX) and voltage ratio compared with
Amplifier (VC) forms.Position annexation and signal trend between them are：NMOS clamp transistors source electrode (or leakage
Pole) through bit line selecting switch (MUX) connection nonvolatile memory data cell to be read and reference unit, NMOS clamper crystal
The grid of pipe is by VG_clampIt is controlled, the drain electrode (or source electrode) of its (or source electrode) connection load transistor that drains, loads crystal
Pipe source electrode (or drain electrode) meets voltage source Vdd, and grid is by VG_loadControl, data cell branch road are brilliant in load with reference unit branch road
The reading voltage at body pipe source electrode (or drain electrode) place, is designated as V respectivelydataWith Vref, they access the two of voltage comparison amplifier simultaneously
Individual input, while VdataThe grid of two transistors (such as RN1 and RN2) in dynamic reference cells is also connected with, for dynamically controlling
The resistance of reference unit processed.When performing read operation, electric current is had from Vdd, through load circuit, NMOS clamp transistors, bit line
Selecting switch, nonvolatile memory data cell and reference unit, eventually flow to low potential Vss.Due to data cell and reference
The resistance of unit is different, therefore can produce different electric currents in two branch roads, is designated as I respectivelydataWith Iref, so as in load electricity
In the presence of road, different voltages, i.e. V can be produced between load circuit and NMOS clamp transistorsdataWith Vref, they are same
When be connected to two inputs of voltage comparison amplifier, be compared and amplify, final output binary data signal.Due to number
There are different resistance states, i.e. R according to unitLWith RH, therefore VdataAlso there is two different values, i.e. VLWith VH.Work as data sheet
The resistance states of member are low resistance state RLWhen, corresponding low voltage value Vdata=VL, therefore, when the voltage is connected in dynamic reference cells
During the grid of transistor (such as RN1 and RN2), reference unit shows higher resistance, so that its corresponding reference voltage
VrefIncrease；Conversely, when the resistance states of data cell are high-impedance state RHWhen, corresponding high-voltage value Vdata=VH, therefore, when the electricity
When being crimped onto the grid of transistor in dynamic reference cells (such as RN1 and RN2), reference unit shows relatively low resistance, so as to
So that its corresponding reference voltage VrefReduce.
Compared to conventional readout scheme, a kind of nonvolatile memory reading circuit based on dynamic reference of the present invention can be with
According to the reading voltage V of data celldataDynamic adjusts the reference voltage V of reference unitrefSize, sentence so as to increase reading
Certainly allowance.In conventional readout scheme, reference voltage VrefIt is changeless, it is entirely by data cell to read judgement allowance
Reading voltage VdataChange and determine, as shown in accompanying drawing 5-1.In dynamic reference scheme proposed by the invention, reference
Voltage VrefIt is the reading voltage V with data celldataAnd dynamic change, and its variation tendency contrary is in the reading of data cell
V is pressed in power takingdataVariation tendency, as shown in accompanying drawing 5-2.More specifically, as data cell reads voltage VdataIncrease, ginseng
Examine voltage VrefReduce；On the contrary, when data cell reads voltage VdataDuring reduction, reference voltage VrefIncrease.In other words, pass through
VdataControl to transistor in dynamic reference cells (such as RN1 and RN2) grid voltage so that VdataAnd VrefBetween have it is opposite
Variation tendency, so as to promoting voltage difference between the two constantly to increase all the time, therefore it is abundant compared with traditional scheme to increase reading judgement
Amount, improve the reading reliability of nonvolatile memory.
Claims (1)
- A kind of 1. nonvolatile memory reading circuit based on dynamic reference, it is characterised in that：The reading circuit is by load crystal Pipe PR0 and PR1, dynamic reference cells, NMOS clamp transistors NC0 and NC1, bit line selecting switch MUX and voltage ratio are relatively amplified Device VC is formed；The source electrode of NMOS clamp transistors is through bit line selecting switch MUX connections nonvolatile memory data sheet to be read Member and dynamic reference cells, the grid of NMOS clamp transistors is by VG_clampSignal is controlled, its connection load crystal that drains The drain electrode of pipe, load transistor source electrode meet voltage source Vdd, and grid is by VG_loadSignal is controlled, data cell branch road and dynamic Reading voltage of the reference unit branch road at load transistor source electrode, is designated as V respectivelydataWith Vref, they access voltage ratio simultaneously Compared with two inputs of amplifier, while VdataThe grid of two transistors in dynamic reference cells is also connected with, it is dynamic for controlling The resistance of state reference unit；When performing read operation, electric current is had from Vdd, through load circuit, NMOS clamp transistors, bit line Selecting switch, nonvolatile memory data cell and dynamic reference cells, eventually flow to low potential Vss；Data cell and dynamic The resistance of reference unit is different, and different electric currents is produced in two branch roads, is designated as I respectivelydataWith Iref, so as in load circuit In the presence of, different voltage V can be produced between load circuit and NMOS clamp transistorsdataWith Vref, it is compared and puts Greatly, final output binary data signal；Data cell has different resistance states RLWith RH, VdataAlso there are two differences Value VLWith VH, when the resistance states of data cell are low resistance state RLWhen, corresponding voltage value Vdata=VL, when the voltage is connected to dynamic In reference unit during the grid of transistor, dynamic reference cells have higher resistance, so that its corresponding reference voltage VrefIncrease；Conversely, when the resistance states of data cell are high-impedance state RHWhen, corresponding voltage value Vdata=VH, now dynamic reference Unit has relatively low resistance, so that its corresponding reference voltage VrefReduce, the reading circuit is according to the electricity of data cell Resistance state dynamic adjusts the resistance sizes of dynamic reference cells, and judgement allowance is read so as to increase；The load circuit is made up of load transistor PR0 and PR1, by VG_loadSignal is controlled, for providing data sheet Member and the conversion of dynamic reference cells electric current to voltage；The NMOS clamp transistors are used for the bit-line voltage for clamping down on data cell and dynamic reference cells, avoid write operation by mistake, Prevent data cell from being damaged with dynamic reference cells because bit-line voltage is excessive simultaneously；The bit line selecting switch MUX is used to select data cell and dynamic reference cells to be read；The voltage comparison amplifier is used to compared with voltage corresponding to dynamic reference cells and amplify data cell, defeated Go out final binary data signal；The dynamic reference cells are the cores of the reading circuit, and it is by 4 data storage section M1-M4 and 4 NMOS Transistor RN1-RN4 is formed, wherein, M1 and M2 one end are connected with bit line, and M1 and the M2 other end are respectively with RN1's and RN2 Drain electrode is connected, and RN1 and RN2 grid meet the reading voltage V of data cell branch roaddata, RN1 and RN2 source electrode connect respectively M3 and Drain electrode of M4 one end, M3 and the M4 other end respectively with RN3 and RN4 is connected, RN3 and RN4 grid connect wordline WL, RN3 and RN4 source electrode connects source line simultaneously；Wherein M1, M3 are configured to low resistance state, and M2, M4 are configured to high-impedance state, or M1, M2 are configured to low resistance state, M3, M4 High-impedance state is configured to, thus obtains the arithmetic average of high low resistance state memory cell conductance or resistance.
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| CN104778963B (en) * | 2015-04-01 | 2017-04-12 | 山东华芯半导体有限公司 | RRAM sensitive amplifier |
| US9754639B2 (en) | 2015-10-30 | 2017-09-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory device and reference circuit thereof |
| CN108257633B (en) * | 2016-12-28 | 2020-10-23 | 上海磁宇信息科技有限公司 | MRAM chip and reading method of memory cell thereof |
| CN109192235A (en) * | 2018-10-17 | 2019-01-11 | 上海华虹宏力半导体制造有限公司 | The reference current control circuit of memory |
| CN109902822B (en) | 2019-03-07 | 2021-04-06 | 北京航空航天大学合肥创新研究院 | Memory computing system and method based on Sgimenk track storage |
| CN111724830B (en) * | 2019-03-18 | 2022-07-26 | 中芯国际集成电路制造(上海)有限公司 | Voltage enhancement type reading amplification circuit |
| CN111755058A (en) * | 2019-03-27 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | Dynamic feedback reading amplifying circuit |
| CN113517008B (en) * | 2020-04-10 | 2024-06-11 | 中国科学院微电子研究所 | Dynamic clamping in-memory computing circuit, memory and electronic equipment |
| CN114639410A (en) * | 2020-12-15 | 2022-06-17 | 浙江驰拓科技有限公司 | Magnetic random access memory and reading circuit thereof |
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