CN113517008B - Dynamic clamping in-memory computing circuit, memory and electronic equipment - Google Patents
Dynamic clamping in-memory computing circuit, memory and electronic equipment Download PDFInfo
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- CN113517008B CN113517008B CN202010279184.5A CN202010279184A CN113517008B CN 113517008 B CN113517008 B CN 113517008B CN 202010279184 A CN202010279184 A CN 202010279184A CN 113517008 B CN113517008 B CN 113517008B
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- 230000015654 memory Effects 0.000 title claims abstract description 48
- 230000008859 change Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 14
- 238000009825 accumulation Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000006993 memory improvement Effects 0.000 description 1
- 230000007334 memory performance Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052976 metal sulfide Inorganic materials 0.000 description 1
- 239000012782 phase change material Substances 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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Abstract
The invention provides a dynamic clamping in-memory computing circuit, a memory and electronic equipment, which comprises a computing array, an analog-to-digital converter, a clamping transistor group, a clamping controller, a bit line, a source line and a plurality of word lines, wherein the computing array is connected with the analog-to-digital converter; the computing array comprises a plurality of units, each unit comprises a transistor and a memory, one electrode of the memory is connected with a drain electrode of the transistor, the other electrode of the memory is connected with a bit line, a source electrode of the transistor is connected with a source line, and a grid electrode of the transistor is connected with a word line; the analog-to-digital converter is connected with the bit line and is used for obtaining the voltage of the bit line; the clamping transistor group comprises a plurality of clamping transistors which are connected in parallel, the source electrodes of the clamping transistors are connected with bit lines, the drain electrodes of the clamping transistors are grounded, and the grid electrodes of the clamping transistors are connected with a clamping controller; the clamp controller is used for controlling the number of the turned-on clamp transistors according to the number of the turned-on word lines in the plurality of word lines. The invention can reduce hardware cost, reduce current on bit line, and control bit line voltage within a preset range.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuits, and more particularly, to a dynamic clamp in-memory computing circuit, a memory, and an electronic device.
Background
Over the past 20 years, the performance of the processor has increased rapidly at about 55% per year, while the memory performance has increased at about 10% per year. The long-term accumulation of unbalanced development speed causes the current memory access speed to be seriously delayed from the calculation speed of the processor, and the memory bottleneck causes that the high-performance processor is difficult to exert the due efficacy, which forms a great restriction on the increasing high-performance calculation, namely a so-called memory wall which prevents the improvement of the calculation performance.
In order to solve the problem of 'memory wall', the larger and larger researchers turn the eyes to memory internal calculation, the main improvement of memory internal operation is to embed the calculation into the memory, directly complete the functions of storage and calculation through the memory, and complete the operation while reading and writing data, thereby reducing the consumption of data access in the calculation process.
However, referring to the circuit diagram of the existing in-memory computing circuit shown in fig. 1, it can be seen that there are certain drawbacks of the existing in-memory computing circuit, for example: the existing in-memory-calculation readout circuit is complex in design, bit line current is converted into voltage through a transimpedance amplifier and then is read out through an analog-to-digital converter, so that the number of transistors required under a CMOS (complementary metal oxide semiconductor) process is large, and the hardware cost is high; when the number of input values is increased, the range of the output values of the traditional in-memory computing circuit is increased in proportion, and the problem of over-wide output range exists in high-dimensional large-scale computing, so that challenges are presented to the design of the analog-digital converter of the subsequent stage; in addition, when the number of input values increases, the number of word lines which are turned on increases, and thus the current on the bit lines increases, so that the metal wires overheat, and the circuit is disabled or even damaged.
Disclosure of Invention
The invention aims to provide a dynamic clamp in-memory computing circuit, a memory and an electronic device, so as to reduce hardware cost, reduce current on a bit line and control the voltage of the bit line within a preset range.
To achieve the above object, an embodiment of the present invention provides a dynamic clamp in-memory computing circuit, including:
A computing array, an analog-to-digital converter, a clamp transistor group, a clamp controller, a bit line, a source line and a plurality of word lines;
Wherein the compute array comprises a plurality of cells, each cell comprising a transistor and a memory, one electrode of the memory is connected with a drain electrode of the transistor, the other electrode of the memory is connected with the bit line, a source electrode of the transistor is connected with the source line, and a gate electrode of the transistor is connected with the word line;
the analog-to-digital converter is connected with the bit line and is used for obtaining the voltage of the bit line;
The clamping transistor group comprises a plurality of clamping transistors connected in parallel, the source electrode of each clamping transistor is connected with the bit line, the drain electrode of each clamping transistor is grounded, and the grid electrode of each clamping transistor is connected with the clamping controller;
The clamp controller is used for controlling the number of clamp transistors conducted in the clamp transistor group according to the number of word lines which are turned on in the plurality of word lines so as to enable the voltage of the bit line to be in a preset range.
The embodiment of the invention also provides a memory, which comprises the dynamic clamping in-memory computing circuit.
The embodiment of the invention also provides electronic equipment which comprises the memory.
The technical scheme provided by the embodiment of the invention can realize conversion from output current to voltage without using a transimpedance amplifier, thereby saving the number of transistors, reducing the circuit area and further reducing the hardware cost. The clamp controller controls the number of clamp transistors conducted in the clamp transistor group through the on-off selection signal, so that the voltage of the bit line is in a preset range, and therefore, fixed output ranges can be obtained for different numbers of input values, and the design pressure of the analog-to-digital converter is reduced. And because the clamp transistors with lower bias voltage are added, the series resistances on the bit lines become larger, so that the problem of overlarge bit line current caused by the increase of the number of input values is solved, and the input parallelism is increased.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
FIG. 1 is a circuit diagram of a conventional in-memory computing circuit;
FIG. 2 is a flow chart of dynamic clamping of bit line voltage provided by the present invention;
FIG. 3 is a circuit diagram of a dynamic clamp in-memory computing circuit provided by the present invention;
FIG. 4 is a circuit diagram of another dynamic clamp in-memory calculation circuit provided by the present invention;
Fig. 5 (a) is a diagram showing the operation states of the clamp transistors when 8 word lines are turned on, and fig. 5 (b) is a diagram showing the result of accumulation of the bit line voltages and products when 8 word lines are turned on;
Fig. 6 (a) is a diagram showing the operation states of the clamp transistors when 16 word lines are turned on, and fig. 6 (b) is a diagram showing the result of the accumulation of the bit line voltages and the products when 16 word lines are turned on;
Fig. 7 (a) is a diagram of the operation states of the clamp transistors when 32 word lines are turned on, and fig. 7 (b) is a diagram of the result of the accumulation of the bit line voltages and the products when 32 word lines are turned on.
Reference numerals illustrate:
A 1-transistor; 2-memory; 3-word lines; 4-bit lines; 5-source lines; a 6-analog-to-digital converter; 7-a transimpedance amplifier; an 8-clamp transistor; 9-clamping a controller; 10-multiplexer.
Detailed Description
The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and the specific embodiments, it should be understood that these embodiments are only for illustrating the present invention and not for limiting the scope of the present invention, and various modifications of equivalent forms of the present invention will fall within the scope of the appended claims after reading the present invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
It will be understood that when an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like are used herein for illustrative purposes only and are not meant to be the only embodiment.
The dynamic clamp in-memory computing circuit provided by the embodiment of the invention can comprise:
A computing array, an analog-to-digital converter, a clamp transistor group, a clamp controller, a Bit Line (BL), a Source Line (SL) and a plurality of Word Lines (WL);
Wherein the compute array comprises a plurality of cells, each cell comprising a transistor and a memory, one electrode of the memory is connected with a drain electrode of the transistor, the other electrode of the memory is connected with the bit line, a source electrode of the transistor is connected with the source line, and a gate electrode of the transistor is connected with the word line;
the analog-to-digital converter is connected with the bit line and is used for obtaining the voltage of the bit line;
The clamping transistor group comprises a plurality of clamping transistors connected in parallel, the source electrode of each clamping transistor is connected with the bit line, the drain electrode of each clamping transistor is grounded, and the grid electrode of each clamping transistor is connected with the clamping controller;
The clamp controller is used for controlling the number of clamp transistors conducted in the clamp transistor group according to the number of word lines which are turned on in the plurality of word lines so as to enable the voltage of the bit line to be in a preset range.
It can be seen that the dynamic clamp internal computing circuit provided by the invention is equivalent to a group of parallel memories and a group of parallel clamp transistors connected in series between a source line and the ground, the voltage of an intermediate node (the voltage of a bit line) depends on the partial pressure of the two, obviously, the number of the parallel memories can be increased by the number of word lines which are started, so that the resistance values of the parallel memories are changed, and the partial pressure of the parallel memories is changed, therefore, the conversion from output current to voltage can be realized without using a transimpedance amplifier, the number of the transistors is saved, the circuit area is reduced, and the hardware cost is reduced. The clamp controller controls the number of clamp transistors conducted in the clamp transistor group through the on-off selection signal, so that the voltage of the bit line is in a preset range, and therefore, fixed output ranges can be obtained for different numbers of input values, and the design pressure of the analog-to-digital converter is reduced. And because the clamp transistors with lower bias voltage are added, the series resistance on the bit line is increased, so that the problem of overlarge bit line current caused by the increase of the number of input values is solved.
Referring to fig. 2, it can be seen from fig. 2 that the clamp controller includes a counter, the counter outputs the number of word lines turned on, and generates a corresponding on-off selection signal, that is, a clp_sel signal, and controls the number of clamp transistors turned on in the clamp transistor group through the clp_sel signal, so that the voltage of the bit line is within a predetermined range.
When the dynamic clamp memory computing circuit contains a plurality of bit lines, the voltages of the word lines and the bit lines can be adjusted, so that each unit in the computing array can be randomly and independently selected, and the selected unit and the unselected unit can be isolated without crosstalk, therefore, the plurality of bit lines can be configured in the dynamic clamp memory computing circuit, wherein each bit line can be connected with one analog-to-digital converter, but when the area of the circuit occupied by the analog-to-digital converter is larger than the column spacing of the computing array, the plurality of bit lines can be connected with one multiplexer, and the multiplexer can be connected with one analog-to-digital converter.
Specifically, referring to fig. 3, a circuit diagram of each bit line connected to one analog-to-digital converter is shown, referring to fig. 4, a circuit diagram of a plurality of bit lines connected to a multiplexer, and then connecting the multiplexer to one analog-to-digital converter is shown.
Specifically, the transistors in the compute array may be NMOS transistors. In practical application, when different resistance values in a high resistance state and a low resistance state are needed, the memory can be a resistance change memory or a phase change memory, and when the memory is the resistance change memory, the material of the memory can be metal oxide, sulfide or organic medium material; when the memory is a phase change memory, the material of the memory may be a phase change material of Ge 2Sb2Ted5.
Specifically, the sizes of the respective clamp transistors in the clamp transistor group may be the same, the clamp transistors may be NMOS transistors, and in order to make the gate voltages of the clamp transistors low, having a certain on-resistance, the bias voltages of the clamp transistors may be set to 0.55V to 0.75V.
The dynamic clamp in-memory computing circuit of the present invention is further described in the following by way of a specific embodiment.
Referring to fig. 5 (a), it can be seen that, in the operating state diagram of the clamp transistors when the 8 word lines are turned on, the clamp controller turns on one clamp transistor in the clamp transistor group by the signal clp_sel [0] =vdd, thereby turning on the clamp transistor to the circuit, and turns off the other clamp transistors in the clamp transistor group by the signals clp_sel [1] =0, … …, clp_sel [ k ] =0. Referring to fig. 5 (b), an image of the bit line voltage and the multiply-accumulate result is shown when 8 word lines are turned on, wherein the multiply-accumulate result is an accumulation of the product of an input value and a stored value, the input value is a level applied to the word line, and the stored value is a resistance value of the memory. It can be seen that the bit line voltage is clamped between 0.05V and 0.4V by the clamp transistor group.
Referring to fig. 6 (a), in order to show the operation state diagram of the clamp transistors when 16 word lines are turned on, it can be seen that when 16 word lines are turned on, the clamp controller turns on two clamp transistors in the clamp transistor group by the signals clp_sel [0] =vdd, clp_sel [1] =vdd, thereby turning on the two clamp transistors to the circuit, and turns off the other clamp transistors in the clamp transistor group by the signals clp_sel [2] =0, … …, clp_sel [ k ] =0. Referring to fig. 6 (b), in order to turn on 16 word lines, the bit line voltage and the multiplication result are accumulated, and it can be seen that the bit line voltage is still clamped between 0.05V and 0.4V when 16 word lines are turned on by two clamp transistors that are turned on.
Referring to fig. 7 (a), in order to show the operation state of the clamp transistors when 32 word lines are turned on, it can be seen that when 32 word lines are turned on, the clamp controller turns on two clamp transistors in the clamp transistor group by the signals clp_sel [0] =vdd, clp_sel [1] =vdd, clp_sel [2] =vdd, so that the two clamp transistors are connected to the circuit, and turns off the other clamp transistors in the clamp transistor group by the signals clp_sel [3] =0, … …, clp_sel [ k ] =0. Referring to fig. 7 (b), in order to turn on 32 word lines, the bit line voltage and the multiplication result are accumulated, and it can be seen that the bit line voltage is still clamped between 0.05V and 0.4V when turning on 32 word lines by three clamp transistors.
The embodiment of the invention also provides a memory, which comprises the dynamic clamping in-memory computing circuit.
The embodiment of the invention also provides electronic equipment which comprises the memory. The electronic device may be a mobile phone, a tablet computer, a wearable device, a desktop computer, an integrated machine, etc., which is not limited to the present invention.
The foregoing embodiments in the present specification are all described in a progressive manner, and the same and similar parts of the embodiments are mutually referred to, and each embodiment is mainly described in a different manner from other embodiments.
The foregoing description is only a few embodiments of the present invention, and the embodiments disclosed in the present invention are merely embodiments adopted for the purpose of facilitating understanding of the technical solutions of the present invention, and are not intended to limit the present invention. Any person skilled in the art can make any modification and variation in form and detail of the embodiments without departing from the spirit and scope of the present disclosure, but the scope of the present disclosure is still subject to the scope of the appended claims.
Claims (8)
1. A dynamic clamp in-memory computing circuit, comprising:
A computing array, an analog-to-digital converter, a clamp transistor group, a clamp controller, a bit line, a source line and a plurality of word lines;
Wherein the compute array comprises a plurality of cells, each cell comprising a transistor and a memory, one electrode of the memory is connected with a drain electrode of the transistor, the other electrode of the memory is connected with the bit line, a source electrode of the transistor is connected with the source line, and a gate electrode of the transistor is connected with the word line;
the analog-to-digital converter is connected with the bit line and is used for obtaining the voltage of the bit line;
The clamping transistor group comprises a plurality of clamping transistors connected in parallel, the source electrode of each clamping transistor is connected with the bit line, the drain electrode of each clamping transistor is grounded, and the grid electrode of each clamping transistor is connected with the clamping controller;
the clamp controller comprises a counter, the counter outputs the number of word lines which are started, the clamp controller is used for generating on-off selection signals according to the number of word lines which are started in the plurality of word lines, and the number of clamp transistors which are conducted in the clamp transistor group is controlled through the on-off selection signals so that the voltage of the bit line is in a preset range.
2. The dynamic clamp in-memory computing circuit of claim 1, wherein, in the case where the dynamic clamp in-memory computing circuit includes a plurality of bit lines, each bit line is connected to one analog-to-digital converter; or a plurality of bit lines, is coupled to a multiplexer, which is coupled to an analog-to-digital converter.
3. The dynamic clamp in-memory computing circuit of claim 1, wherein the clamp controller generates a corresponding on-off select signal according to a number of turned-on word lines in the plurality of word lines, and controls a number of turned-on clamp transistors in the clamp transistor group by the on-off select signal.
4. The dynamic clamp in-memory computing circuit of claim 1, wherein the transistors in the computing array are NMOS transistors.
5. The dynamic clamp in-memory computing circuit of claim 1, wherein the memory is a resistive random access memory or a phase change memory.
6. The dynamic clamp in-memory computing circuit of claim 1, wherein the clamp transistor is an NMOS transistor, and the bias voltage of the clamp transistor is 0.55V to 0.75V.
7. A memory comprising the dynamic clamp in-memory computing circuit of any one of claims 1 to 6.
8. An electronic device comprising the memory of claim 7.
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| CN202010279184.5A CN113517008B (en) | 2020-04-10 | 2020-04-10 | Dynamic clamping in-memory computing circuit, memory and electronic equipment |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114676834B (en) * | 2022-05-26 | 2022-08-02 | 中科南京智能技术研究院 | Bit line voltage clamping circuit for memory computing array |
| CN115794728B (en) * | 2022-11-28 | 2024-04-12 | 北京大学 | In-memory computing bit line clamping and summing peripheral circuit and application thereof |
| CN117037871B (en) * | 2023-10-09 | 2024-02-27 | 之江实验室 | Reading circuit, reading method and memory for in-memory calculation result |
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| US4373195A (en) * | 1979-10-30 | 1983-02-08 | Fujitsu Limited | Semiconductor integrated circuit device |
| US5223834A (en) * | 1991-11-29 | 1993-06-29 | Industrial Technology Research Institute | Timing control for precharged circuit |
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