CN104133748B - 用以在微处理器内组合来自多个寄存器单元的对应半字单元的方法及系统 - Google Patents

用以在微处理器内组合来自多个寄存器单元的对应半字单元的方法及系统 Download PDF

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Publication number
CN104133748B
CN104133748B CN201410348018.0A CN201410348018A CN104133748B CN 104133748 B CN104133748 B CN 104133748B CN 201410348018 A CN201410348018 A CN 201410348018A CN 104133748 B CN104133748 B CN 104133748B
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CN201410348018.0A
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Chinese (zh)
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CN104133748A (zh
Inventor
曾贸
卢奇安·科德雷斯库
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
CN201410348018.0A 2006-05-10 2007-05-07 用以在微处理器内组合来自多个寄存器单元的对应半字单元的方法及系统 Expired - Fee Related CN104133748B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/431,300 US8127117B2 (en) 2006-05-10 2006-05-10 Method and system to combine corresponding half word units from multiple register units within a microprocessor
US11/431,300 2006-05-10
CNA2007800165248A CN101438236A (zh) 2006-05-10 2007-05-07 用以在微处理器内组合来自多个寄存器单元的对应半字单元的方法及系统

Related Parent Applications (1)

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CNA2007800165248A Division CN101438236A (zh) 2006-05-10 2007-05-07 用以在微处理器内组合来自多个寄存器单元的对应半字单元的方法及系统

Publications (2)

Publication Number Publication Date
CN104133748A CN104133748A (zh) 2014-11-05
CN104133748B true CN104133748B (zh) 2018-10-19

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CN201410348018.0A Expired - Fee Related CN104133748B (zh) 2006-05-10 2007-05-07 用以在微处理器内组合来自多个寄存器单元的对应半字单元的方法及系统
CNA2007800165248A Pending CN101438236A (zh) 2006-05-10 2007-05-07 用以在微处理器内组合来自多个寄存器单元的对应半字单元的方法及系统

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CNA2007800165248A Pending CN101438236A (zh) 2006-05-10 2007-05-07 用以在微处理器内组合来自多个寄存器单元的对应半字单元的方法及系统

Country Status (6)

Country Link
US (1) US8127117B2 (cg-RX-API-DMAC7.html)
EP (1) EP2027533A2 (cg-RX-API-DMAC7.html)
JP (4) JP2009536774A (cg-RX-API-DMAC7.html)
KR (1) KR100988964B1 (cg-RX-API-DMAC7.html)
CN (2) CN104133748B (cg-RX-API-DMAC7.html)
WO (1) WO2007134013A2 (cg-RX-API-DMAC7.html)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8127117B2 (en) * 2006-05-10 2012-02-28 Qualcomm Incorporated Method and system to combine corresponding half word units from multiple register units within a microprocessor
US8417922B2 (en) * 2006-08-02 2013-04-09 Qualcomm Incorporated Method and system to combine multiple register units within a microprocessor
JP2011242995A (ja) * 2010-05-18 2011-12-01 Toshiba Corp 半導体装置
US20120254589A1 (en) * 2011-04-01 2012-10-04 Jesus Corbal San Adrian System, apparatus, and method for aligning registers
KR101783312B1 (ko) 2011-11-15 2017-10-10 삼성전자주식회사 클러스터 간의 통신으로 인한 오버헤드를 최소화하는 장치 및 방법
JP5701930B2 (ja) * 2013-04-22 2015-04-15 株式会社東芝 半導体装置
US11593117B2 (en) 2018-06-29 2023-02-28 Qualcomm Incorporated Combining load or store instructions
KR102685097B1 (ko) 2018-12-07 2024-07-16 한화오션 주식회사 파이프 시편 절단용 지그기구
KR102663496B1 (ko) * 2022-08-02 2024-05-08 이화여자대학교 산학협력단 프로세서의 레지스터 캐시 인덱스 결정 방법 및 이를 수행하는 전자 장치

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NL7317545A (nl) * 1973-12-21 1975-06-24 Philips Nv Geheugensysteem met hoofd- en buffergeheugen.
JPH0415832A (ja) * 1990-05-09 1992-01-21 Nec Corp 障害処理方式
US5564056A (en) * 1994-03-01 1996-10-08 Intel Corporation Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming
DE69524862T2 (de) 1995-05-16 2002-11-07 Oce-Technologies B.V., Venlo Druckersystem, das ein Kommunikationssteuerungsgerät beinhaltet
GB9509987D0 (en) 1995-05-17 1995-07-12 Sgs Thomson Microelectronics Manipulation of data
GB9509988D0 (en) * 1995-05-17 1995-07-12 Sgs Thomson Microelectronics Matrix transposition
CN103064653B (zh) * 1995-08-31 2016-05-18 英特尔公司 控制移位分组数据的位校正的装置
US6141675A (en) * 1995-09-01 2000-10-31 Philips Electronics North America Corporation Method and apparatus for custom operations
US5933650A (en) * 1997-10-09 1999-08-03 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
US6052522A (en) 1997-10-30 2000-04-18 Infineon Technologies North America Corporation Method and apparatus for extracting data stored in concatenated registers
WO2000070446A2 (en) * 1999-05-13 2000-11-23 Arc International U.S. Holdings Inc. Method and apparatus for loose register encoding within a pipelined processor
US6463525B1 (en) * 1999-08-16 2002-10-08 Sun Microsystems, Inc. Merging single precision floating point operands
US6631460B1 (en) * 2000-04-27 2003-10-07 Institute For The Development Of Emerging Architectures, L.L.C. Advanced load address table entry invalidation based on register address wraparound
US7092526B2 (en) * 2000-05-05 2006-08-15 Teleputers, Llc Method and system for performing subword permutation instructions for use in two-dimensional multimedia processing
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JP3776732B2 (ja) 2001-02-02 2006-05-17 株式会社東芝 プロセッサ装置
US7103756B2 (en) * 2002-09-30 2006-09-05 Hewlett-Packard Development Company, L.P. Data processor with individually writable register subword locations
US7689641B2 (en) * 2003-06-30 2010-03-30 Intel Corporation SIMD integer multiply high with round and shift
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US8127117B2 (en) * 2006-05-10 2012-02-28 Qualcomm Incorporated Method and system to combine corresponding half word units from multiple register units within a microprocessor

Also Published As

Publication number Publication date
JP2018156672A (ja) 2018-10-04
US8127117B2 (en) 2012-02-28
KR100988964B1 (ko) 2010-10-20
CN104133748A (zh) 2014-11-05
JP2009536774A (ja) 2009-10-15
WO2007134013A3 (en) 2008-01-10
JP6242615B2 (ja) 2017-12-06
JP2013242892A (ja) 2013-12-05
WO2007134013B1 (en) 2008-02-14
KR20090009959A (ko) 2009-01-23
JP2016194929A (ja) 2016-11-17
EP2027533A2 (en) 2009-02-25
WO2007134013A2 (en) 2007-11-22
US20070266226A1 (en) 2007-11-15
CN101438236A (zh) 2009-05-20

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Granted publication date: 20181019