CN104124249A - Fin-type semiconductor device - Google Patents
Fin-type semiconductor device Download PDFInfo
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- CN104124249A CN104124249A CN201310145997.5A CN201310145997A CN104124249A CN 104124249 A CN104124249 A CN 104124249A CN 201310145997 A CN201310145997 A CN 201310145997A CN 104124249 A CN104124249 A CN 104124249A
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- floating boom
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Abstract
The invention belongs to the technical field of semiconductor memories, and in particular relates to a fin-type semiconductor device. The fin-type semiconductor device comprises at least a substrate, fin-type source and drain regions formed in the substrate, an N-shaped channel region formed between the source region and the drain region, a floating gate, a control gate, and a gate control p-n junction diode for connecting the floating gate and the drain region. The fin-type semiconductor device uses floating gate storage information and conducts charging and discharging for the floating gate through the gate control p-n junction diode; and has the advantages of large driving current, low operation voltage during data storage, high data holding ability and so on.
Description
Technical field
The present invention relates to a kind of semiconductor memory, particularly a kind of fin type semiconductor device, belongs to semiconductor memory technologies field.
Background technology
Semiconductor memory is widely used among various electronic products.Structure, performance and the density of different application field to semiconductor memory has different requirements.Such as, static random access memory (SRAM) has very high arbitrary access speed and lower integration density, and the dynamic random access memory (DRAM) of standard has very high density and medium arbitrary access speed.
Fig. 1 be prior art a kind of semiconductor memory of planar channeling, comprise: having and source region 501 and the drain region 502 of the contrary doping type of Semiconductor substrate of Semiconductor substrate 500 interior formation, Semiconductor substrate 500 can be monocrystalline silicon, polysilicon or be the silicon on insulator.In Semiconductor substrate 500, between source region 501 and drain region 502, be formed with the planar channeling district 601 of device, planar channeling district 601 is this semiconductor memory inversion layers in Semiconductor substrate 500 interior formation in the time carrying out work.In source region 501 and drain region 502, be also formed with respectively doped region 509 and the doped region 510 of high-dopant concentration, doped region 509 and doped region 510 have identical doping type with source region 501 and drain region 502.
On source region 501, channel region 601 and drain region 502, be formed with ground floor insulation film 503, and be formed with a floating boom open area 504 in ground floor insulation film 503 on drain region 502.On ground floor insulation film 503, cover whole planar channeling district 601 and floating boom open area 504 is formed with a floating boom 505 as charge-storage node, floating boom 505 has the doping type contrary with drain region 502, and the impurity in floating boom 505 can be diffused to and in drain region 502, be formed diffusion region 602 by floating boom open area 504, thereby between floating boom 505 and drain region 502, forms a p-n junction diode by floating boom open area 504.
Cover floating boom 205 and described p-n junction diode structure and be formed with second layer insulation film 506.On second layer insulation film 506, cover and surround floating boom 505 and be formed with the control gate 507 of device.Both sides at control gate 507 are also formed with grid curb wall 508.This semiconductor memory also comprises the contact 511 for source region that source region 501, control gate 507, drain region 502, Semiconductor substrate 500 are connected with outer electrode being formed by electric conducting material, contact 512, the contact 513 in drain region and the contact 514 of Semiconductor substrate of control gate.
Along with the continuous reduction of feature sizes of semiconductor devices, the leakage current of the semiconductor device of planar channeling also rises rapidly along with the shortening of raceway groove, causes the ratio of drive current/leakage current to reduce, and this has greatly limited the performance of semiconductor device.
Summary of the invention
In view of this, the object of the invention is to propose a kind of fin type semiconductor device, to obtain larger drive current.
For reaching above-mentioned purpose of the present invention, the present invention proposes a kind of fin type semiconductor device, specifically comprise:
One has the substrate of the first doping type;
Source region and the drain region of the fin type with the second doping type forming in described substrate;
The channel region forming in described substrate and between described source region and described drain region, described channel region becomes " П " shape along the cross section perpendicular to orientation;
Cover described source region and described drain region fin Ji Qi both sides, top and cover the ground floor insulation film that whole described " П " shape channel region forms;
The floating boom open area that the exposed at both sides of the top of the fin in described drain region and fin is gone out forming in the ground floor insulation film in the described drain region of covering;
Cover the floating boom with the first doping type as charge-storage node that described ground floor insulation film and described floating boom open area form, described floating boom is positioned on " П " shape channel region and floating boom open area, for controlling the electric current between source region and drain region;
The p-n junction diode forming between described floating boom and described drain region by described floating boom open area;
Cover described floating boom and described p-n junction diode and surround second layer insulation film and the control gate that described floating boom forms.
Fin type semiconductor device as above, described second layer insulation film and control gate only surround floating boom in the side near described drain region.
Fin type semiconductor device as above, described second layer insulation film and control gate surround floating boom in the side near described drain region and near a side in described source region simultaneously.
Fin type semiconductor device as above, described substrate can be the silicon substrate on silicon substrate or insulator.
Fin type semiconductor device as above, described ground floor insulation film, second layer insulation film are formed by the insulating material of silicon dioxide, silicon nitride, silicon oxynitride or high-k.
Fin type semiconductor device as above, described floating boom is formed by polysilicon, and described control gate is formed by the polysilicon of metal, alloy or doping.
Fin type semiconductor device as above, described the first doping type is N-shaped doping, described the second doping type is p-type doping; Or described the first doping type is p-type doping, described the second doping type is N-shaped doping.
Fin type semiconductor device as above, described p-n junction diode, second layer insulation film and control gate have formed a gate control diode using described control gate as grid, the anode of described gate control diode is connected with described floating boom, and the negative electrode of described gate control diode is connected with described drain region; Or the negative electrode of described gate control diode is connected with described floating boom, the anode of described gate control diode is connected with described drain region.
Fin type semiconductor device by using floating boom storage information proposed by the invention, and carry out charge or discharge by described grid-control p-n junction diode pair floating boom, has the advantages such as drive current is large, operating voltage is low when data are stored, data holding ability is strong.
Brief description of the drawings
Fig. 1 is the sectional view of the semiconductor memory of a kind of planar channeling of prior art.
Fig. 2 is the tomograph of first embodiment of fin type semiconductor device proposed by the invention.
Fig. 3 is the sectional view of the fin type semiconductor device shown in Fig. 2 along xy face.
Fig. 4 is the structural representation of the floating boom open area of the internal structure of the fin type semiconductor device shown in Fig. 2.
Fig. 5 is the tomograph of second embodiment of fin type semiconductor device proposed by the invention.
Fig. 6 is the tomograph of the 3rd embodiment of fin type semiconductor device proposed by the invention.
Fig. 7 is the structural representation of the floating boom open area of the internal structure of the fin type semiconductor device shown in Fig. 6.
Fig. 8 is the tomograph of the 4th embodiment of fin type semiconductor device proposed by the invention.
Fig. 9 is the sectional view of the fin type semiconductor device shown in Fig. 8 along xy face.
Figure 10 is the equivalent circuit diagram of fin type semiconductor device proposed by the invention.
Embodiment
Below with reference to accompanying drawings illustrative embodiments of the present invention is elaborated.In the drawings, for convenience of description, amplified the thickness in layer and region, shown in size do not represent actual size.Reference diagram is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in region shown in figure, but comprises obtained shape, the deviation causing such as manufacture.
In the following description, term substrate can be understood as and comprises the just Semiconductor substrate in processes, may comprise other prepared thin layer thereon.Simultaneously, in the following description, described the first doping type and described the second doping type are contrary doping type, can be N-shaped doping for the first doping type, the second doping type is p-type doping, or, also can be for the first doping type is p-type doping, the second doping type is N-shaped doping.
Fig. 2 to Fig. 4 is first embodiment of fin type semiconductor device proposed by the invention, wherein Fig. 2 is the tomograph of first embodiment of fin type semiconductor device proposed by the invention, Fig. 3 is the sectional view of the fin type semiconductor device shown in Fig. 2 along xy face, and Fig. 4 is the structural representation of the floating boom open area of the internal structure of the fin type semiconductor device shown in Fig. 2.Fig. 5 is the tomograph of second embodiment of fin type semiconductor device proposed by the invention.Fig. 6 to Fig. 7 is the 3rd embodiment of fin type semiconductor device proposed by the invention, wherein Fig. 6 is the tomograph of the 3rd embodiment of fin type semiconductor device proposed by the invention, and Fig. 7 is the structural representation of the floating boom open area of the internal structure of the fin type semiconductor device shown in Fig. 6.Fig. 8 to Fig. 9 is the 4th embodiment of fin type semiconductor device proposed by the invention, wherein, Fig. 8 is the tomograph of the 4th embodiment of fin type semiconductor device proposed by the invention, and Fig. 9 is the sectional view of the fin type semiconductor device shown in Fig. 8 along xy face.
As shown in Fig. 2 to Fig. 9, fin type semiconductor device proposed by the invention comprises a substrate 200 with the first doping type, is formed with source region 201 and the drain region 202 of the fin type with the second doping type in substrate 200.In source region 201 with drain region 202 is interior can also be formed with respectively and doped region 209 and the doped region 210 of the high-dopant concentration of source region 201 and drain region 202 identical doping types, for reducing the ohmic contact of device.
In substrate 200 and be formed with the channel region 402 of device between source region 201 and drain region 202, channel region 402 becomes " П " shape along the cross section perpendicular to orientation." П " shape channel region 402 is inversion layers that this fin type semiconductor device forms while carrying out work in the surface of substrate 200.Cover source region 201 and drain region 202 fin Ji Qi both sides, top and cover whole " П " shape channel region 401 and be formed with ground floor insulation film 203, and be formed with a floating boom open area 401 that the exposed at both sides of the top of the fin in drain region 202 and fin is gone out in the ground floor insulation film that covers drain region 202.Ground floor insulation film 203 can be silicon dioxide, silicon nitride, silicon oxynitride or the insulating material for high-ks such as hafnium oxide, and its physical thickness range is preferably 1-20 nanometer.
Cover ground floor insulation film 203 and floating boom open area 401 and be formed with a floating boom with the first doping type 205 as charge-storage node, floating boom 205 is positioned on " П " shape channel region 402 and floating boom open area, for controlling the electric current between source region 201 and drain region 202.Floating boom is 205 for having the polysilicon of the first doping type, and by floating boom open area 401, floating boom 205 contacts with drain region 202, therefore, impurity in floating boom 205 can be diffused in drain region 202 and be formed and have the diffusion region 204 of the first doping type by floating boom open area 401, thereby between floating boom 205 and drain region 202, forms a p-n junction diode by floating boom open area 401.
Cover floating boom 205 and described p-n junction diode structure and surround floating boom 205 and be formed with second layer insulation film 206 and control gate 207.Second layer insulation film 206 can be silicon dioxide, silicon nitride, silicon oxynitride or the insulating material for high-ks such as hafnium oxide, and its physical thickness range is preferably 1-20 nanometer.Control gate 207 can be metal, alloy or the polysilicon for doping.
In fin type semiconductor device proposed by the invention, substrate 200 can be directly that silicon substrate can be also the silicon substrate on insulator.In four embodiment of fin type semiconductor device proposed by the invention, as Fig. 2, Fig. 3, first embodiment shown in Fig. 4 and as Fig. 8, the 4th embodiment shown in Fig. 9 adopts the silicon substrate structure on insulator, silicon-on-insulator substrate structure comprises thick silicon bottom 100, thin intermediate insulating layer 102 and thin top layer silicon substrate 200, the source region 201 of fin type is formed at the thin top layer silicon substrate 200 being arranged on intermediate insulating layer 102 and is connected with insulating barrier 102 with drain region 202, adopt the silicon substrate structure on insulator, can effectively improve the performance of device, reduce power consumption.Simultaneously, fin type semiconductor device proposed by the invention second embodiment and the 3rd embodiment as shown in Figure 6, Figure 7 as shown in Figure 5 directly adopts silicon substrate structure, in second embodiment of the fin type semiconductor device shown in Fig. 5, source region 201 and drain region 202 are given prominence to and are connected with silicon substrate 200 from the silicon substrate between adjacent fleet plough groove isolation structure, and fleet plough groove isolation structure is the known technique of industry.In the 3rd embodiment of the fin type semiconductor device shown in Fig. 6, Fig. 7, shallow ditch groove structure is not shown, the source region 201 of fin type along becoming " protruding " shape perpendicular to the cross section in device channel length, adopts this structure can effectively increase the control area of floating boom 205 and control gate 207 with drain region 202.Adopt in silicon substrate, form shallow trench isolation from structure compared with the silicon substrate structure adopting on insulator, there is lower production cost.
In fin type semiconductor device proposed by the invention, second layer insulation film 206 and control gate 207 are in covering floating boom 205, can only surround floating boom 205 in the side near drain region 202, also can surround floating boom 205 in the side near source region 201 with near a side in drain region 202 simultaneously.In four embodiment of fin type semiconductor device proposed by the invention, in first embodiment as shown in Figure 2, Figure 3, Figure 4 and second embodiment as shown in Figure 5 and the 3rd embodiment as 6, as shown in Fig. 7,207 of second layer insulation film 206 and control gates surround floating booms 205 in the sides near drain region 202.As 8 and Fig. 9 as shown in the 4th embodiment in, second layer insulation film 206 and control gate 207 are surrounding floating boom 205 near the side in source region 201 and in the side near drain region 202 simultaneously.Second layer insulation film 206 and control gate 207 are in the side near source region 201 and in the time surrounding floating boom 205 near a side in drain region 202 simultaneously, and fin type semiconductor device of the present invention has higher control gate coupling efficiency.
For describing in further detail the 26S Proteasome Structure and Function of fin type semiconductor device proposed by the invention, Figure 10 has shown the equivalent circuit diagram of fin type semiconductor device of the present invention.As shown in figure 10, fin type semiconductor device of the present invention comprises a MOSFET (metal-oxide semiconductor fieldeffect transistor) 336 with source electrode 332, drain electrode 330, floating boom 333 and control gate 331 and control gate 331 taking the MOSFET336 gate control diode 335 as grid.The floating boom 333 of MOSFET336 can be connected with the anode of gate control diode 335, also can be connected with the negative electrode of gate control diode 335, and in embodiment as shown in figure 10 of the present invention, floating boom 333 is connected with the anode of gate control diode 335.By control gate 331, drain electrode 330 and source electrode 331 are applied to suitable voltage, gate control diode 335 can carry out charge or discharge to floating boom 333 and change with this amount of charge being stored in floating boom 333, and this amount of charge has determined the logic state of this fin type semiconductor device.
As mentioned above, in the situation that not departing from spirit and scope of the invention, can also form many embodiment that have very big difference.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the instantiation described in specification.
Claims (9)
1. a fin type semiconductor device, is characterized in that, comprising:
One has the substrate of the first doping type;
Source region and the drain region of the fin type with the second doping type forming in described substrate;
The channel region forming in described substrate and between described source region and described drain region, described channel region becomes " П " shape along the cross section perpendicular to orientation;
Cover described source region and described drain region fin Ji Qi both sides, top and cover the ground floor insulation film that whole described " П " shape channel region forms;
The floating boom open area that the exposed at both sides of the top of the fin in described drain region and fin is gone out forming in the ground floor insulation film in the described drain region of covering;
Cover the floating boom with the first doping type as charge-storage node that described ground floor insulation film and described floating boom open area form, described floating boom is positioned on " П " shape channel region and floating boom open area, for controlling the electric current between source region and drain region;
The p-n junction diode forming between described floating boom and described drain region by described floating boom open area;
Cover described floating boom and described p-n junction diode and surround second layer insulation film and the control gate that described floating boom forms.
2. fin type semiconductor device according to claim 1, is characterized in that, described second layer insulation film and control gate only surround floating boom in the side near described drain region.
3. fin type semiconductor device according to claim 1, is characterized in that, described second layer insulation film and control gate surround floating boom in the side near described drain region and near a side in described source region simultaneously.
4. fin type semiconductor device according to claim 1, is characterized in that, described substrate can be the silicon substrate on silicon substrate or insulator.
5. fin type semiconductor device according to claim 1, is characterized in that, described ground floor insulation film, second layer insulation film are formed by the insulating material of silicon dioxide, silicon nitride, silicon oxynitride or high-k.
6. fin type semiconductor device according to claim 1, is characterized in that, described floating boom is formed by polysilicon, and described control gate is formed by the polysilicon of metal, alloy or doping.
7. fin type semiconductor device according to claim 1, is characterized in that, described the first doping type is N-shaped doping, and described the second doping type is p-type doping.
8. fin type semiconductor device according to claim 1, is characterized in that, described the first doping type is p-type doping, and described the second doping type is N-shaped doping.
9. fin type semiconductor device according to claim 1, it is characterized in that, described p-n junction diode, second layer insulation film and control gate have formed a gate control diode using described control gate as grid, the anode of described gate control diode is connected with described floating boom, and the negative electrode of described gate control diode is connected with described drain region; Or the negative electrode of described gate control diode is connected with described floating boom, the anode of described gate control diode is connected with described drain region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310145997.5A CN104124249A (en) | 2013-04-25 | 2013-04-25 | Fin-type semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310145997.5A CN104124249A (en) | 2013-04-25 | 2013-04-25 | Fin-type semiconductor device |
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| CN104124249A true CN104124249A (en) | 2014-10-29 |
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| CN201310145997.5A Pending CN104124249A (en) | 2013-04-25 | 2013-04-25 | Fin-type semiconductor device |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060284210A1 (en) * | 2005-06-08 | 2006-12-21 | Suraj Mathew | Capacitorless dram on bulk silicon |
| CN100468743C (en) * | 2005-12-06 | 2009-03-11 | 力晶半导体股份有限公司 | Non-volatile memory and mfg. method |
-
2013
- 2013-04-25 CN CN201310145997.5A patent/CN104124249A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060284210A1 (en) * | 2005-06-08 | 2006-12-21 | Suraj Mathew | Capacitorless dram on bulk silicon |
| CN100468743C (en) * | 2005-12-06 | 2009-03-11 | 力晶半导体股份有限公司 | Non-volatile memory and mfg. method |
Non-Patent Citations (1)
| Title |
|---|
| 臧松干等: ""一种新型高速嵌入式动态随机存储器"", 《微电子学》 * |
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