CN212725321U

CN212725321U - LDMOS device and semiconductor device

Info

Publication number: CN212725321U
Application number: CN202021382634.5U
Authority: CN
Inventors: 吴栋华; 石新欢
Original assignee: Warship Chip Manufacturing Suzhou Ltd By Share Ltd
Current assignee: Warship Chip Manufacturing Suzhou Ltd By Share Ltd; Hejian Technology Suzhou Co Ltd
Priority date: 2020-07-14
Filing date: 2020-07-14
Publication date: 2021-03-16
Anticipated expiration: 2030-07-14

Abstract

The utility model discloses a LDMOS device is provided, contains: the P-type substrate is a source electrode; an epitaxial layer on the P-type substrate; a gate on the epitaxial layer, the gate having a field plate surrounding the gate at an upper edge and a side edge; a drain electrode positioned on the grid electrode, and an interlayer isolation medium is arranged between the grid electrode and the drain electrode; and a drain trench and a source trench filled with a conductive medium, the drain trench connecting the epitaxial layer and the drain, the source trench connecting the epitaxial layer and the field plate. The LDMOS device is simple in structure and small in transverse size. The utility model discloses provide a semiconductor device who contains above-mentioned LDMOS device simultaneously.

Description

LDMOS device and semiconductor device

Technical Field

The utility model relates to the field of semiconductor technology, in particular to LDMOS device and contain semiconductor device of this LDMOS device.

Background

LDMOS (laterally diffused metal oxide semiconductor) is a power device based on diffusion technology, and has the advantages of high voltage resistance and the like, and is commonly used in high voltage power integrated circuits. The conventional LDMOS structure includes a substrate, and a source, a gate and a drain laterally disposed on the substrate, and a certain distance is required to be maintained between the gate regions. The Field Plate (Field Plate) is a structure for increasing the radius of curvature of the depletion region boundary at the edge of the PN junction to laterally extend the depletion layer. The arrangement of the field plate is beneficial to reducing the boundary electric field and improving the breakdown voltage. The gate field plate of the conventional LDMOS structure may extend laterally directly to and connect to the source electrode. However, the lateral size of the conventional LDMOS structure is large, which is disadvantageous to the miniaturization of the semiconductor device.

SUMMERY OF THE UTILITY MODEL

In order to solve the prior technical problem, the utility model provides a LDMOS device and contain semiconductor device of this LDMOS device with novel structure.

The foundation the utility model discloses, a LDMOS device is provided, contains:

the P-type substrate is a source electrode;

an epitaxial layer on the P-type substrate;

a gate on the epitaxial layer, the gate having a field plate surrounding the gate at an upper edge and a side edge;

a drain electrode positioned on the grid electrode, and an interlayer isolation medium is arranged between the grid electrode and the drain electrode; and

and the drain electrode groove is filled with a conductive medium and is connected with the epitaxial layer and the drain electrode, and the source electrode groove is connected with the epitaxial layer and the field plate.

According to an embodiment of the present invention, the field plate is made of polysilicon.

According to one embodiment of the present invention, the source trenches extend into the interlayer isolation medium and are bussed to the field plate.

According to an embodiment of the present invention, the epitaxial layer includes a first N-type drift region and a second N-type drift region, wherein a first N-type diffusion layer with a doping concentration greater than that of the first N-type drift region is formed on a surface of the first N-type drift region, and the drain trench extends to an end of the epitaxial layer to contact the first N-type diffusion layer; the second N-type drift region is located on one side, far away from the interlayer isolation medium, of the first N-type drift region, and the doping concentration of the second N-type drift region is smaller than that of the first N-type drift region.

According to the utility model discloses an embodiment, the epitaxial layer contains the district of P type doping, and the surface in the district of P type doping forms second N type diffused layer, and the source trench contacts with the two in the district of second N type diffused layer and P type doping to the depth that the source trench extends to the epitaxial layer is greater than the junction depth in the district of P type doping.

According to an embodiment of the present invention, the depth of the source trench extending to the epitaxial layer is 1-2 μm.

According to one embodiment of the present invention, the conductive medium comprises a Ti/TiN layer covering the inner surfaces of the drain trench and the source trench and a metal tungsten filled in the Ti/TiN layer.

According to an embodiment of the present invention, the gate electrode includes a stacked polysilicon and tungsten silicide.

According to the utility model discloses, a semiconductor device of above-mentioned LDMOS device is provided.

The foundation the utility model discloses, a semiconductor device is provided, contains:

the P-type substrate is a source electrode;

an epitaxial layer on the P-type substrate;

the first grid and the second grid are positioned on the epitaxial layer, and a first field plate and a second field plate are respectively surrounded at the upper edge and the side edge of the first grid and the second grid;

the first drain electrode and the second drain electrode are respectively positioned on the first grid electrode and the second grid electrode, and interlayer isolation media are arranged among the first grid electrode, the second grid electrode, the first drain electrode and the second drain electrode; and

a first drain trench, a second drain trench and a source trench filled with a conductive medium, the first drain trench connecting the epitaxial layer and the first drain, the second drain trench connecting the epitaxial layer and the second drain, the source trench connecting the epitaxial layer to the first field plate and the second field plate.

Due to the adoption of the technical scheme, compared with the prior art, the utility model have the following advantage: the utility model discloses an regard as the source electrode with the back of a wafer, arrange the drain electrode metal at the crystal face to reduce LDMOS transverse dimension in the insulating layer with the grid setting between source electrode and drain electrode, connect source electrode and grid field board through filling W plug at trench.

Drawings

Fig. 1 shows a schematic diagram of an embodiment of an LDMOS device according to the invention.

In the figure, the position of the upper end of the main shaft,

the transistor comprises a 1P type substrate, a 2 epitaxial layer, a 21 first drift region, a 211 first N type diffusion layer, a 22 second drift region, a 23P type doped body region, a 231 second N type diffusion layer, a 3 grid electrode, a 4 field plate, a 5 drain electrode, a 6 interlayer isolation medium, a 7 source electrode groove and an 8 drain electrode groove.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.

Fig. 1 shows an embodiment of an LDMOS device according to the invention. As shown, the LDMOS device generally includes a P-type substrate 1 as a source, an epitaxial layer 2 on the P-type substrate 1, a gate 3 over the epitaxial layer 2, and a drain 5 over the gate 3. Wherein an insulating interlayer isolation dielectric (ILD)6 is disposed between the gate 3 and the drain 5, and a field plate 4 is surrounded at the upper edge and the side edge of the gate 3 to improve the breakdown voltage. Furthermore, the LDMOS device comprises source trenches 7 connecting the epitaxial layer 2 and the field plate 4, and drain trenches 8 connecting the epitaxial layer 2 and the drain 5. The source trench 7 and the drain trench 8 are filled with a conductive medium to electrically connect the epitaxial layer 2 and the field plate 4, and the epitaxial layer 2 and the drain 5, respectively. Preferably, the gate 3 may include stacked polysilicon (Poly) and tungsten silicide (WSi), the drain 5 may be metal, and the conductive medium may include a Ti/TiN layer covering the inner surfaces of the source trench 7 and the drain trench 8 and metal tungsten (W) filled in the Ti/TiN layer.

In an embodiment of the present invention, a first N-type drift region (NDD1)21 and a second N-type drift region (NDD2)22 may be included in the epitaxial layer 2. A first N-type diffusion layer (N +)211 with a doping concentration greater than that of the first N-type drift region 21 is formed on the surface of the first N-type drift region 21, and the drain trench 8 extends to the end of the epitaxial layer 2 and contacts the first N-type diffusion layer 211. The second N-type drift region 22 is located on a side, i.e., a lower side, of the first N-type drift region 21 away from the interlayer isolation medium 6, and has a doping concentration less than that of the first N-type drift region 21. Further, the epitaxial layer 2 further includes a P-type doped body region (PBODY)23, and a second N-type diffusion layer (N +)231 may be formed on a surface of the P-type doped body region 23. The source trench 7 is in contact with both the second N-type diffusion layer 231 and the P-type doped body region 23, and the source trench 7 extends to a depth of the epitaxial layer 2 greater than a junction depth of the P-type doped body region 23. Preferably, the depth of the source trench 7 extending to the epitaxial layer 2 can reach 1 to 2 μm.

Preferably, the field plate 4 may be made of polysilicon. The field plate 4 may be connected to the portion of the source trench 7 extending into the interlayer insulating medium 6 via a BUS (BUS, not shown), and further connected to the epitaxial layer 2 via the source trench 7. Based on this connection, the source trenches 7 can be connected to the plurality of field plates 4, respectively. As shown in fig. 1, the semiconductor device according to the present invention includes a P-type substrate 1 as a source, an epitaxial layer 2 on the P-type substrate 1, a pair of gates 3 over the epitaxial layer 2, and a pair of drains 5 over the pair of gates 3. Wherein an insulating interlayer isolation dielectric (ILD)6 is disposed between the pair of gates 3 and the pair of drains 5, and field plates 4 are respectively surrounded at upper edges and side edges of the pair of gates 3. The source trench 7 is located between the pair of gates 3 and may be connected to the pair of gates 3 through a bus line, respectively. A pair of drain trenches 8 connect the pair of drains 5 to the epitaxial layer 2, respectively. The lateral size of the LDMOS device can be further reduced by sharing one source trench 7 with a plurality of LDMOS devices.

In the LDMOS device with the structure, the P-type substrate 1 positioned at the crystal back is used as a source electrode, the drain electrode 5 is arranged at the crystal plane, the longitudinal space is reasonably utilized, and the transverse size is obviously reduced compared with the traditional LDMOS in which the source electrode, the grid electrode and the drain electrode are transversely arranged. Further, by providing the drain trench 8 to connect the epitaxial layer 2 and the drain 5, the defects of difficult connection and complex structure between the field plate 4 and the source electrode 1 caused by the longitudinal arrangement of the source electrode, the gate electrode and the drain electrode are overcome.

The above embodiments only express the embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims

1. An LDMOS device, comprising:

the P-type substrate is a source electrode;

an epitaxial layer on the P-type substrate;

a gate on the epitaxial layer, the gate having field plates around its upper and side edges;

a drain trench and a source trench filled with a conductive medium, the drain trench connecting the epitaxial layer and the drain, the source trench connecting the epitaxial layer and the field plate.

2. The LDMOS device of claim 1, wherein the field plate is made of polysilicon.

3. The LDMOS device of claim 1, wherein the source trench extends into the interlayer isolation dielectric and is connected to the field plate by a bus.

4. The LDMOS device of claim 1, wherein the epitaxial layer includes a first N-type drift region and a second N-type drift region therein,

a first N-type diffusion layer with the doping concentration larger than that of the first N-type drift region is formed on the surface of the first N-type drift region, and the drain electrode groove extends to the end part of the epitaxial layer to be in contact with the first N-type diffusion layer;

the second N-type drift region is positioned on one side, far away from the interlayer isolation medium, of the first N-type drift region, and the doping concentration of the second N-type drift region is smaller than that of the first N-type drift region.

5. The LDMOS device of claim 1, wherein the epitaxial layer includes a P-doped body region, a surface of the P-doped body region forms a second N-type diffusion layer, the source trench is in contact with both the second N-type diffusion layer and the P-doped body region, and the source trench extends to a depth of the epitaxial layer that is greater than a junction depth of the P-doped body region.

6. The LDMOS device of claim 5, wherein the source trench extends to a depth of 1-2 μm to the epitaxial layer.

7. The LDMOS device set forth in claim 1 wherein said conductive medium comprises a Ti/TiN layer overlying an inner surface of said drain trench and said source trench and a tungsten metal filled within said Ti/TiN layer.

8. The LDMOS device of claim 1, wherein the gate comprises a stack of polysilicon and tungsten silicide.

9. A semiconductor arrangement, characterized in that the semiconductor arrangement comprises an LDMOS device as claimed in any one of claims 1 to 8.

10. A semiconductor device, comprising:

the P-type substrate is a source electrode;

an epitaxial layer on the P-type substrate;

a first drain electrode and a second drain electrode respectively positioned on the first grid electrode and the second grid electrode, wherein interlayer isolation media are arranged among the first grid electrode, the second grid electrode, the first drain electrode and the second drain electrode; and

first drain trenches, second drain trenches and source trenches filled with a conductive medium, the first drain trenches connecting the epitaxial layer and the first drain, the second drain trenches connecting the epitaxial layer and the second drain, the source trenches connecting the epitaxial layer to the first field plate and the second field plate.