CN104124246A - Memory device and manufacturing method thereof - Google Patents
Memory device and manufacturing method thereof Download PDFInfo
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- CN104124246A CN104124246A CN201310150886.3A CN201310150886A CN104124246A CN 104124246 A CN104124246 A CN 104124246A CN 201310150886 A CN201310150886 A CN 201310150886A CN 104124246 A CN104124246 A CN 104124246A
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Abstract
The invention discloses a memory device and a manufacturing method thereof. The memory device comprises a substrate, a memory material layer, a first dielectric layer, a first gate layer, a second gate layer and a source/drain area, wherein the substrate is provided with a groove; the memory material layer is formed on one side wall of the groove; the first dielectric layer, the first gate layer and the second gate layer fill the groove; the first dielectric layer is formed between the first gate layer and the second gate layer; the source/drain area is formed inside the substrate and adjoins the memory material layer; and the extending direction of the first gate layer is vertical with the extending direction of the source/drain area. The invention also provides a manufacturing method of the above memory device. The width of a word line in the memory device is defined by the height of the first gate layer and therefore, the memory device has good operation effectiveness in the condition where the size is reduced.
Description
Technical field
The present invention relates to a kind of memory storage and manufacture method thereof, particularly relate to a kind of memory storage and manufacture method thereof that has size reduction and excellent operation usefulness concurrently.
Background technology
At word line (the word line herein of making memory storage, be character line, all be called word line herein) technique in, after traditional mode is polysilicon (polysilicon) layer that first deposits whole piece, follow etching polysilicon layer and form many word lines, then in etching space out, insert dielectric material between word line.Yet, along with dwindling of memory storage, wordline width and gap each other also reduce, and with etch process, make word line easily because the incomplete and residual polysilicon of etching is short-circuited, or wordline width is inhomogeneous, cause the reliability of memory storage to reduce.And wordline width reduces also to cause the usefulness of memory storage not good.
Therefore, the designers of this area are devoted to operation usefulness and the reliability that developmental research improves memory storage invariably.
Summary of the invention
The object of the invention is to, a kind of new memory storage and manufacture method thereof are provided, technical problem to be solved is that the width (word line width) that makes word line in memory storage is the height definition with first grid layer, make memory storage can the in the situation that of size reduction, still there is good operation usefulness, be very suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of memory storage proposing according to the present invention.It comprises a substrate, a memory material layer, one first dielectric layer, a first grid layer, a second grid layer and a doping bar.Substrate has a groove, and memory material layer is formed on a sidewall of groove.The first dielectric layer, first grid layer and second grid layer are filled in groove, and the first dielectric layer is to be formed between first grid layer and second grid layer.Doping bar is formed in substrate and is adjacent to memory material layer.The direction that the direction that wherein first grid layer extends is extended perpendicular to source/drain regions.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid memory storage, wherein this doping bar comprises multiple source/drain pole region.
Aforesaid memory storage, wherein this substrate has more at least one long recess, and this doping bar is formed within the surface of this long recess (within).
Aforesaid memory storage, also comprises: one second dielectric layer, this second dielectric layer is formed in this long recess.
The object of the invention to solve the technical problems also realizes by the following technical solutions.A kind of memory storage proposing according to the present invention.It comprises a substrate, a plurality of memory material layer, a plurality of the first dielectric layer, a plurality of first grid layer, a plurality of second grid layer and a plurality of doping bar.Substrate has a plurality of grooves.Memory material layer is formed on a sidewall of each groove.Each first dielectric layer is be formed between each first grid layer and each second grid layer and be filled in each groove.Doping bar is formed in substrate and is adjacent to memory material layer.The direction that the direction that first grid layer extends is extended perpendicular to doping bar.
The object of the invention to solve the technical problems realizes in addition more by the following technical solutions.The manufacture method of a kind of memory storage proposing according to the present invention.It comprises the following steps.One substrate is provided, and substrate has a groove; Form a memory material layer on a sidewall of groove; Form one first dielectric layer, a first grid layer and a second grid layer and be filled in groove, wherein the first dielectric series of strata are formed between first grid layer and second grid layer; And form source/drain region in substrate and be adjacent to memory material layer, the direction that the direction that wherein first grid layer extends is extended perpendicular to source/drain regions.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of aforesaid memory storage, the step that wherein forms this first dielectric layer, this first grid layer and this second grid layer comprises: form a conductive material layer; This conductive material layer of etching is to form a gap (gap), and separate this conductive material layer to be split into two parts in this gap; Form a dielectric materials layer on this conductive material layer and in this gap; And grind this dielectric materials layer and this conductive material layer to form this first dielectric layer, this first grid layer and this second grid layer.
The manufacture method of aforesaid memory storage, wherein forms the step of this source/drain regions in this substrate and comprises: this substrate is carried out to an ion cloth and plant (ion implantation) technique to form this source/drain regions in this substrate.
The manufacture method of aforesaid memory storage, also comprises and forms one second dielectric layer on this source/drain regions.
The object of the invention to solve the technical problems also realizes in addition by the following technical solutions.The manufacture method of a kind of memory storage proposing according to the present invention.It comprises the following steps.One substrate is provided, and wherein substrate has a plurality of grooves; Form a plurality of memory material layers respectively on one of each groove sidewall; Form a plurality of the first dielectric layers, a plurality of first grid layer and a plurality of second grid layer, wherein each first dielectric layer is be formed between each first grid layer and each second grid layer and be filled in each groove; And form a plurality of doping bars in substrate and be adjacent to memory material layer; The direction that the direction that wherein first grid layer extends is extended perpendicular to doping bar.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of aforesaid memory storage, wherein forms the step of those doping bars in this substrate and comprises: this substrate is carried out to an ion cloth and plant (ion implantation) technique to form those doping bars in this substrate.
The present invention compared with prior art has obvious advantage and beneficial effect.By technique scheme, memory storage of the present invention and manufacture method thereof at least have following advantages and beneficial effect: it is the height definition with first grid layer that the present invention makes the width of word line in memory storage, thereby makes memory storage can the in the situation that of size reduction, still have good operation usefulness.
In sum, the invention relates to a kind of memory storage and manufacture method thereof.This memory storage comprises a substrate, a memory material layer, one first dielectric layer, a first grid layer, second grid layer and a source/drain region.Wherein, substrate has a groove, and memory material layer is formed on a sidewall of groove.The first dielectric layer, first grid layer and second grid layer are filled in groove, and the first dielectric layer is to be formed between first grid layer and second grid layer.Source/drain regions is formed in substrate and is adjacent to memory material layer.The direction that the direction that first grid layer extends is extended perpendicular to source/drain regions.The present invention has significant progress technically, and has obvious good effect, is really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand technological means of the present invention, and can be implemented according to the content of specification, and for above and other object of the present invention, feature and advantage can be become apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Fig. 1 illustrates the vertical view of memory storage according to an embodiment of the invention.
Fig. 2 A is the profile illustrating along the hatching I-I of Fig. 1.
Fig. 2 B is the profile illustrating along the hatching II-II of Fig. 1.
Fig. 2 C illustrates the stereogram that Fig. 1 dotted line frame a encloses region.
Fig. 3 is the stereogram of mnemon that illustrates the memory storage of Fig. 1.
Fig. 4 to Figure 11 D is the schematic diagram illustrating according to the manufacture method of the memory storage of one embodiment of the invention.
Figure 12 is the circuit diagram illustrating according to the memory storage of the embodiment of Fig. 1.
Figure 13 is wordline width (word line width)-transconductance value (transconductance, the Gm) curve chart that illustrates memory storage.
100: memory storage
110,110 ': substrate
120: memory material layer
120 ': memory material coating layer
120a, 131a, 140a, 170a: end face
131: first grid layer
131b: base
131s, 150s: sidewall
133: second grid layer
135: the first dielectric layers
140: doping bar
150: groove
150b: bottom
170: the second dielectric layers
630: conductive material layer
631,633: the part of conductive material layer
635: dielectric materials layer
C, C ': mnemon
D1, D2: direction
G: gap
HM1, HM2: patterned hard mask layer
HM1 ', HM2 ': hard mask layer
IMP: cloth is planted direction
L1: highly
L2: length
S/D: source/drain regions
T1, T2: long recess
2C, 5D, 7D, 9D, 11D: dotted line frame
2A-2A ', 2B-2B ', 4A-4A ', 6A-6A ', 8A-8A ', 8B-8B ', 10A-10A ', 10B-10B ': hatching
Embodiment
For further setting forth the present invention, reach technological means and the effect that predetermined goal of the invention is taked, below in conjunction with accompanying drawing and preferred embodiment, memory storage and its embodiment of manufacture method, structure, method, step, feature and effect thereof to proposing according to the present invention, be described in detail as follows.
Some embodiments of the present invention will be described in detail as follows.Yet except following description, the present invention can also be widely implements at other embodiment, and protection scope of the present invention is not subject to the restriction of embodiment, and its protection range with claim is as the criterion.Moreover for clearer description being provided and being easier to understand the present invention, graphic interior each several part is not drawn according to its relative size, some size is compared and is exaggerated with other scale dependents; Incoherent detail section does not show completely yet, in the hope of graphic succinct.
Fig. 1 illustrates the vertical view of memory storage 100 according to an embodiment of the invention, Fig. 2 A is the profile illustrating along the hatching I-I of Fig. 1, Fig. 2 B is the profile illustrating along the hatching II-II of Fig. 1, Fig. 2 C illustrates the stereogram that Fig. 1 dotted line frame a encloses region, and Fig. 3 is the stereogram of mnemon C that illustrates the memory storage 100 of Fig. 1.
Refer to shown in Fig. 1, Fig. 2 A to Fig. 2 C and Fig. 3.Memory storage 100 comprises substrate 110, memory material layer 120, first grid layer 131, second grid layer 133, the first dielectric layer 135 and source/drain regions (Source/Drain) S/D.Substrate 110 has groove 150, and memory material layer 120 is formed on the sidewall 150s of groove 150.The first dielectric layer 135, first grid layer 131 and second grid layer 133 are filled in groove 150, and wherein the first dielectric layer 135 is formed between first grid layer 131 and second grid layer 133.Source/drain regions S/D is formed in substrate 110 and is adjacent to memory material layer 120.The direction D2 that the direction D1 that first grid layer 131 extends extends perpendicular to source/drain regions S/D.As shown in Figure 3, memory material layer 120, first grid layer 131, source/drain regions S/D form a mnemon C, and wherein the word line of memory storage 100 extends towards direction D1, bit line (bit line herein, be bit line, be all called bit line herein) towards direction D2, extend.
As shown in Fig. 2 A～Fig. 2 C, in an embodiment, the end face 140a of source/drain regions S/D and the end face 131a of first grid layer 131 are coplines.In other words, as shown in Figure 3, the source/drain regions S/D of part is disposed at the side of first grid layer 131, and in memory storage 100, the position of programming (program) mnemon C is at the sidewall 131s of first grid layer 131 and the adjoiner of memory material layer 120.
In an embodiment, as shown in Fig. 2 A～Fig. 2 C, the end face 140a of source/drain regions S/D and the end face 120a of memory material layer 120 are coplines.
In an embodiment, as shown in Figure 1, memory storage 100 can comprise a plurality of memory material layers 120, a plurality of first grid layer 131, a plurality of second grid layer 133, a plurality of the first dielectric layer 135 and a plurality of doping bar 140.A plurality of memory material layers 120 are formed on a sidewall 150s of each groove 150, the direction D2 that the direction D1 that first grid layer 131 extends extends perpendicular to doping bar 140.
In an embodiment, doping bar 140 comprises source/drain regions S/D.Memory storage 100 comprises a plurality of mnemon C (and/or mnemon C '), except memory material layer 120, first grid layer 131 and source/drain regions S/D can form a mnemon C, memory material layer 120, second grid layer 133 and source/drain regions S/D also can form a mnemon C '.
In an embodiment, the material of substrate 110 is for example P type silicon or N-type silicon, and the material of the material of first grid layer 131 and second grid layer 133 for example comprises doped silicon (doped silicon).
As shown in Fig. 1 and Fig. 2 A～Fig. 2 C, in an embodiment, a plurality of memory material layers 120 are formed on the relative two sidewall 150s of groove 150.In an embodiment, memory material layer 120 can have sandwich construction, for example, be ONO composite bed or ONONO composite bed or BE-SONOS composite bed, or comprises the ONO structure being for example staggeredly stacked to form by silica and silicon nitride.Memory material layer 120 also can be homogenous material layer, comprises silicon nitride or silica for example silicon dioxide, silicon oxynitride.Memory material layer 120 is used for catching (trapping) electronics.
In an embodiment, doping bar 140 (and source/drain regions S/D) is for example heavily doped region (heavily doping region), for example N-type heavily doped region (N type heavily doping region, N+) or P type heavily doped region (P type heavily doping region, P+), the material of doping bar 140 (and source/drain regions S/D) for example comprises arsenic (As), boron difluoride ion (BF
2 +) or phosphorus.
In an embodiment, as shown in Fig. 2 A and Fig. 3, first grid layer 131 has the bottom 150b that a base 131b is parallel to groove 150, and the height L1 of first grid layer 131 is greater than the length L 2 of base 131b.In one embodiment, the height L1 of first grid layer 131 is for example 10～120 nanometers (nm), and the length L 2 of the base 131b of first grid layer 131 is for example between 5 to 40 nanometers.
As shown in Fig. 1 and Fig. 2 A～Fig. 2 C, in an embodiment, substrate 110 more can have a plurality of long recess T2, and each bar 140 that adulterates is formed within the surface of each long recess T2 (within).
As shown in Fig. 1 and Fig. 2 A～Fig. 2 C, in an embodiment, memory storage 100 more can comprise that the second dielectric layer 170, the second dielectric layers 170 are formed on doping bar 140.As shown in Figure 2 B, the second dielectric layer 170 is formed in long recess T2, the end face 140a of the end face 170a of the second dielectric layer 170 and doping bar 140 is coplines, the end face 140a of the end face 131a of first grid layer 131 and doping bar 140 is coplines, and the end face 140a of the end face 133a of second grid layer 133 and doping bar 140 is coplines.
In an embodiment, as shown in Figure 1, memory storage 100 can comprise a plurality of the second dielectric layers 170.Each second dielectric layer 170 is formed on corresponding doping bar 140, and the end face 170a of all the second dielectric layers 170 and the end face 140a of all doping bars 140 are coplines.
As shown in Fig. 1 and Fig. 2 C, doping bar 140 is to be electrically connected different mnemon C (or C ').
In one embodiment, first grid layer 131 is for example the primary structure of word line (word line), and doping bar 140 is for example the primary structure of bit line (bit line), via first grid layer 131, applies operating voltage operative memory device 100.As shown in Figure 1, Figure 2 shown in A～Fig. 2 C and Fig. 3, in memory storage 100, the position of programming mnemon C is at the sidewall 131s of first grid layer 131 and the adjoiner of memory material layer 120, rather than at the base of first grid layer 131 131b, therefore the width (word line width) of word line is the height L1 definition with first grid layer 131, rather than with the sectional width (the namely length L 2 of base 131b) of first grid layer 131.So, the sectional width of the word line of memory storage 100 (length L 2 of base 131b) can be accomplished to minimize in the situation that technique is allowed, and then reach reducing of memory storage 100 overall dimensions, still can there is relatively large wordline width, and then make memory storage 100 can the in the situation that of size reduction, still there is good operation usefulness.
The manufacture method of a kind of memory storage of the embodiment of the present invention is below proposed, however those steps use for illustrating only, not in order to limit the present invention.The technical staff with common knowledge should need to be modified or be changed those steps according to actual example.Should be noted, some elements in part vertical view are to illustrate with clearer expression content of the present invention with perspective fashion.
Fig. 4 to Figure 11 D is the schematic diagram illustrating according to the manufacture method of the memory storage 100 of one embodiment of the invention.Refer to shown in Fig. 4 to Figure 11 D.
Wherein, refer to Fig. 4～Fig. 5 D (Fig. 5 A～Fig. 5 C is the generalized section illustrating along the hatching III-III of Fig. 4, and Fig. 5 D illustrates the stereogram that dotted line frame b in Fig. 4 encloses region).First, as shown in Figure 5A, provide substrate 110 ', then deposit hard mask layer HM1 ' on substrate 110 '.In an embodiment, the material of hard mask layer HM1 ' is for example silicon nitride (SiN).Then, as shown in Figure 5 B, for example with etch process patterned hard mask layer HM1 ' to form the patterned hard mask layer HM1 of strip, then according to patterned hard mask layer HM1 etching substrates 110 ' to form the substrate 110 with a plurality of long recess T1, long recess T1 extends towards direction D1.Then, as shown in Fig. 4 and Fig. 5 C～Fig. 5 D, form memory material coating layer 120 ' on patterned hard mask layer HM1 and in long recess T1.In this step, forming long recess T1 is the position in order to defined word line.
Then, refer to Fig. 6～Fig. 7 D (Fig. 7 A～Fig. 7 C is the generalized section illustrating along the hatching IV-IV of Fig. 6, and Fig. 7 D illustrates the stereogram that dotted line frame c in Fig. 6 encloses region).As shown in Figure 7 A, form conductive material layer 630 on memory material coating layer 120 '.In an embodiment, be for example in memory material coating layer 120 ' in upper and long recess T1 with thin-film technique deposits conductive material layer 630.Then, as shown in Figure 7 B, etching conductive material layer 630 is to form a gap (gap) G, and clearance G is separated conductive material layer 630 to be split into two parts 631 and 633, and exposes a part of bottom surface of long recess T1.In one embodiment, as shown in Figure 7 B, the part memory material coating layer 120 ' in clearance G is also etched and remove.In another embodiment, the part memory material coating layer 120 ' (not illustrating) in also can retention gap G.Then, as shown in Fig. 6 and Fig. 7 C～Fig. 7 D, form dielectric materials layer 635 on conductive material layer 630 (631 and 633) and in clearance G, then removing patterned hard mask layer HM1 and planarization dielectric materials layer 635 and conductive material layer 630, for example, is to remove patterned hard mask layer HM1 and grinding medium material layer 635 and conductive material layer 630 in cmp (CMP) mode.
The thickness of conductive material layer 630 is equivalent to the word line sectional width (length L 2 of base 131b) of memory storage 100.With thin-film technique deposits conductive material layer 630, be easy to control thickness, be easy to form thickness as thin as a wafer, therefore can be in the situation that technique be allowed minimum wordline sectional width (length L 2 of base 131b), and then reach significantly reducing of memory storage 100 overall dimensions.
Moreover, conductive material layer 630 is inserted in long recess T1 and in subsequent technique, is formed a plurality of first grid layers 131 and a plurality of second grid layer 133 in a plurality of grooves 150, between a plurality of first grid layers 131, not with etch process, separate, between a plurality of second grid layers 133, not with etch process, separate, therefore between first grid layer 131 (word line) and do not have residual electric conducting material between second grid layer 133 (word line), can not be short-circuited because of the complete and residual electric conducting material of etching not.Thus, between each word line, there is good insulating properties, and then improve the reliability of memory storage 100.
And tradition is with etching mode defined word line width, when conductive material layer is thicker, etching completely difficulty significantly improves, and is more prone to occur because of the residual not etching situation that electric conducting material is short-circuited completely between word line.In the embodiment of this disclosure, wordline width is with the height definition of first grid layer 131 (or second grid layer 133), therefore in manufacture process, the thickness of conductive material layer is higher, the situation that not only can not be short-circuited completely, can increase wordline width on the contrary, and then promote the operating characteristics of memory storage.
Then, refer to Fig. 8～Fig. 9 D (Fig. 9 A～Fig. 9 B is the generalized section illustrating along the hatching VI-VI of Fig. 8, and Fig. 9 C is the generalized section illustrating along the hatching V-V of Fig. 8, and Fig. 9 D illustrates the stereogram that dotted line frame d in Fig. 8 encloses region).As shown in Figure 9 A, form hard mask layer HM2 ' on substrate 110, dielectric materials layer 635 and conductive material layer 630.Then, as shown in Fig. 8 and Fig. 9 B～Fig. 9 D, for example with etch process patterned hard mask layer HM2 ' to form the patterned hard mask layer HM2 of strip, then according to patterned hard mask layer HM2 etching substrates 110, dielectric materials layer 635 and conductive material layer 630 to form a plurality of long recess T2, long recess T2 extends towards direction D2.In this step, forming long recess T2 is the position in order to definition doping bar 140 (bit line), the direction D2 that the direction D1 that long recess T1 extends extends perpendicular to long recess T2.
Via etch process, form after long recess T2, in this step, the groove 150, the memory material layer 120 that also form substrate 110 are filled in groove 150 at sidewall 150s and first grid layer 131, second grid layer 133 and first dielectric layer 135 of groove 150.
Then, (Figure 11 A～Figure 11 B is the generalized section illustrating along the hatching VIII-VIII of Figure 10 to refer to Figure 10～Figure 11 D, Figure 11 C is the generalized section illustrating along the hatching VII-VII of Figure 10, and Figure 11 D illustrates the stereogram that dotted line frame e in Figure 10 encloses region).As shown in Figure 11 A, substrate 110 is carried out to an ion cloth and plant (ion implantation) technique to form doping bar 140 (and source/drain regions S/D) in substrate 110.In an embodiment, with cloth, plant direction IMP and to substrate 110 surfaces in long recess T2, carry out ion cloth and plant, within doping bar 140 is formed at the surface of z long recess T2.In an embodiment, doping bar 140 (and source/drain regions S/D) plants technique by ion cloth to form in the interior heavily doped region forming of substrate 110.
Then, as shown in Figure 10 and Figure 11 B～Figure 11 D, form dielectric materials layer on patterned hard mask layer HM2 and in long recess T2, then remove the dielectric materials layer in patterned hard mask layer HM2 and planarization long recess T2, to form on the doping bar 140 of the second dielectric layer 170 in long recess T2.In an embodiment, be for example with the dielectric materials layer in cmp mode abrasive pattern hard mask layer HM2 and long recess T2.After this grinding steps, the end face 170a of doping the end face 140a of bar 140, the end face 131a of first grid layer 131 and the second dielectric layer 170 is coplines.So far, form the memory storage 100 shown in A～Fig. 2 D and Fig. 3 as shown in Figure 1, Figure 2, the direction D2 that the direction D1 that wherein first grid layer 131 extends extends perpendicular to doping bar 140, memory material layer 120, first grid layer 131 and source/drain regions S/D form a mnemon C.
Figure 12 is the circuit diagram illustrating according to the memory storage 100 of the embodiment of Fig. 1.Word line extends towards direction D1, and bit line (doping bar 140) extends towards direction D2.
Figure 13 is wordline width (word line width)-transconductance value (transconductance, the Gm) curve chart that illustrates memory storage.Transconductance value (Gm) is proportional to (W/L) * C
eOT* μ, wherein W represents grid (word line) width, L represents grid length, C
eOTthe electric capacity (Capacitance of equivalent oxide thickness) that represents the equivalent oxide thickness of memory material layer, μ represents electrons (hole herein, be electric hole, be all called hole herein) mobility (mobility).When transconductance value is larger, voltage distribution (Vt distribution) is narrower, (product open window) is larger for the peak-to-peak spacing of adjacent wave in voltage distribution curve, and can reduce the memory storage chance of (fail) that lost efficacy, and then can promote the usefulness of memory storage.
As shown in figure 13, wordline width has linear proportional relation with transconductance value substantially.Yet, according to traditional memory storage structure, in order to reach the size of memory storage, to dwindle, wordline width also can be dwindled.When wordline width is less than 40 nanometers, start, transconductance value declines more violently, and this can cause the usefulness of memory storage acutely deteriorated.Relatively, in the embodiment of this disclosure, via reduction word line sectional width (length L 2 of the base 131b of first grid layer 131), and then reach significantly reducing of memory storage 100 overall dimensions, and do not affect wordline width (the height L1 of first grid layer 131), therefore memory storage 100 still can have relatively large wordline width, thereby there is relatively large transconductance value, and then make memory storage 100 can in the situation that size reduction still there is good operation usefulness.
The above, it is only preferred embodiment of the present invention, not the present invention is done to any pro forma restriction, although the present invention discloses as above with preferred embodiment, yet not in order to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when can utilizing the method for above-mentioned announcement and technology contents to make a little change or being modified to the equivalent embodiment of equivalent variations, in every case be the content that does not depart from technical solution of the present invention, any simple modification of above embodiment being done according to technical spirit of the present invention, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (10)
1. a memory storage, is characterized in that it comprises:
One substrate, has a groove;
One memory material layer, is formed on a sidewall of this groove;
One first dielectric layer, a first grid layer and a second grid layer, be filled in this groove, and wherein this first dielectric layer is to be formed between this first grid layer and this second grid layer; And
One doping bar, is formed in this substrate and is adjacent to this memory material layer;
The direction that the direction that wherein this first grid layer extends is extended perpendicular to this doping bar.
2. memory storage according to claim 1, is characterized in that wherein this doping bar comprises multiple source/drain pole region.
3. memory storage according to claim 1, is characterized in that wherein this substrate has more at least one long recess, within this doping bar is formed at the surface of this long recess.
4. memory storage according to claim 3, is characterized in that it also comprises:
One second dielectric layer, this second dielectric layer is formed in this long recess.
5. a manufacture method for memory storage, is characterized in that it comprises the following steps:
One substrate is provided, and wherein this substrate has a groove;
Form a memory material layer on a sidewall of this groove;
Form one first dielectric layer, a first grid layer and a second grid layer and be filled in this groove, wherein this first dielectric layer is to be formed between this first grid layer and this second grid layer; And
Form source/drain region in this substrate and be adjacent to this memory material layer;
The direction that the direction that wherein this first grid layer extends is extended perpendicular to this source/drain regions.
6. the manufacture method of memory storage according to claim 5, is characterized in that the step that wherein forms this first dielectric layer, this first grid layer and this second grid layer comprises:
Form a conductive material layer;
This conductive material layer of etching is to form a gap, and separate this conductive material layer to be split into two parts in this gap;
Form a dielectric materials layer on this conductive material layer and in this gap; And
Grind this dielectric materials layer and this conductive material layer to form this first dielectric layer, this first grid layer and this second grid layer.
7. the manufacture method of memory storage according to claim 5, is characterized in that wherein forming the step of this source/drain regions in this substrate and comprises:
This substrate is carried out to an ion cloth and plant technique to form this source/drain regions in this substrate.
8. the manufacture method of memory storage according to claim 5, is characterized in that it also comprises that formation one second dielectric layer is on this source/drain regions.
9. a manufacture method for memory storage, is characterized in that it comprises the following steps:
One substrate is provided, and wherein this substrate has a plurality of grooves;
Form on the sidewall of a plurality of memory material layers respectively at this groove respectively;
Form a plurality of the first dielectric layers, a plurality of first grid layer and a plurality of second grid layer, wherein respectively this first dielectric layer is to be formed at respectively this first grid layer and respectively between this second grid layer and be filled in respectively in this groove; And
Form a plurality of doping bars in this substrate and be adjacent to those memory material layers;
The direction that the direction that wherein those first grid layers extend is extended perpendicular to those doping bars.
10. the manufacture method of memory storage according to claim 9, is characterized in that wherein forming those doping bars steps in this substrate and comprises:
This substrate is carried out to an ion cloth and plant technique to form those doping bars in this substrate.
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