CN103050445A - Memory body and manufacturing method thereof - Google Patents
Memory body and manufacturing method thereof Download PDFInfo
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- CN103050445A CN103050445A CN2011103194363A CN201110319436A CN103050445A CN 103050445 A CN103050445 A CN 103050445A CN 2011103194363 A CN2011103194363 A CN 2011103194363A CN 201110319436 A CN201110319436 A CN 201110319436A CN 103050445 A CN103050445 A CN 103050445A
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Abstract
The invention provides a memory body and a manufacturing method thereof. The manufacturing method comprises the following steps of forming multiple stacked structures on a substrate extending in a first direction, wherein each stacked structure comprises a plurality of first insulation layers and a plurality of second insulation layers, the first insulation layers are stacked on the substrate and the second insulation layers are respectively arranged between the adjacent first insulation layers; forming a plurality of troughs extending in the first direction in each stacked structure, wherein the troughs are located at two opposite sides of the each second insulation layer; filling a first conductor layer in each trough, and forming a plurality of charge storage structures extending in a second direction on the stacked structures, and forming a second conductor layer on each charge storage structure. According to the memory body and the manufacturing method thereof provided by the invention, as the insulation layers with different etching velocities are stacked on the substrate alternatively, and as the insulation layers of the etched part are adopted to form an area to fill in a bit element line, the limit of the existing lithography can be broken through to form the bit element line with a smaller size, thereby improving the memory density of the memory body.
Description
Technical field
The present invention relates to a kind of memory body and preparation method thereof, particularly relate to a kind of memory body with higher memory density (memory density) and preparation method thereof.
Background technology
Therefore non-volatility memory must possess this type of memory body in many electric equipment products owing to having advantages of that the data that deposits in can not disappear yet after outage, the normal running when starting shooting to keep electric equipment products.
Along with the size of electronic component is dwindled, the size of the memory body that is made of memory cell is also dwindled thereupon.Yet, being subject to present little shadow technology, the memory cell of General Two-Dimensional also is restricted (for example dwindling the spacing between the adjacent memory cell) on the dimension reduction.In addition, because the size of memory cell is dwindled, also caused the reduction of memory density.
In order to increase the data storage ability of memory body, three-dimensional memory cell has been subject to showing great attention to of industry.Yet for present Three Dimensional Memory born of the same parents' array processes, it has higher complexity, and still is subject to the restriction of existing little shadow technology in the reduction of size.
This shows, above-mentioned existing memory body and preparation method thereof obviously still has inconvenience and defective, and demands urgently further being improved in product structure, manufacture method and use.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but have no for a long time applicable design is finished by development always, and common product and method do not have appropriate structure and method to address the above problem, and this obviously is the problem that the anxious wish of relevant dealer solves.Therefore how to found a kind of new memory body and preparation method thereof, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Summary of the invention
The object of the invention is to, overcome the defective that the manufacture method of existing memory body exists, and a kind of manufacture method of new memory body is provided, technical problem to be solved is to make it can produce the memory body with higher memory density, is very suitable for practicality.
Another object of the present invention is to, overcome the defective that existing memory body exists, and a kind of new memory body is provided, technical problem to be solved is to make it have higher memory density, thereby more is suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.The manufacture method of a kind of memory body that proposes according to the present invention, the method is to form many stacked structures that extend at first direction in substrate first.Each stacked structure comprises a plurality of the first insulating barriers and a plurality of the second insulating barrier.These first stacked dielectric layers are in substrate, and the second insulating barrier lays respectively between the first adjacent insulating barrier.Then, in each stacked structure, form many grooves that extend at first direction.These grooves are positioned at relative two sides of each the second insulating barrier.Then, in groove, insert the first conductor layer.Afterwards, form many at the charge storing structure of second direction extension and at each charge storing structure formation the second conductor layer at these stacked structures.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of aforesaid memory body, the etch-rate of wherein said the first insulating barrier are for example less than the etch-rate of the second insulating barrier.
The manufacture method of aforesaid memory body, the material of wherein said the first insulating barrier for example are oxide, nitride or nitrogen oxide.
The manufacture method of aforesaid memory body, the material of wherein said the second insulating barrier for example are oxide, nitride or nitrogen oxide.
The manufacture method of aforesaid memory body, the formation method of wherein said groove for example are to carry out isotropic etching technique, to remove the part of each the second insulating barrier.
The manufacture method of aforesaid memory body, the formation method of wherein said stacked structure for example are to form the first insulation material layer and the second insulation material layer in substrate first, and the superiors are the first insulation material layer.Then, the first insulation material layer in the superiors forms many cover curtain layers that extend at first direction.Afterwards, take cover curtain layer as the cover curtain, remove part the first insulation material layer and the second insulation material layer.
The manufacture method of aforesaid memory body, the formation method of wherein said the first conductor layer for example are to form conductor material layer in substrate first.Conductor material layer covers stacked structure, and inserts in the groove.Afterwards, carry out anisotropic etch process, remove the outer conductor material layer of groove.
The manufacture method of aforesaid memory body, the formation method of wherein said charge storing structure and the second conductor layer for example are to form the charge storage material layer that covers stacked structure in substrate first.Then, form conductor material layer at the charge storage material layer.Then, form many cover curtain layers that extend in second direction at conductor material layer.Afterwards, take cover curtain layer as the cover curtain, remove segment conductor material layer and Partial charge storage material layer.
The object of the invention to solve the technical problems also realizes by the following technical solutions.According to a kind of memory body that the present invention proposes, it comprises many stacked structures, many charge storing structures and many character lines.Stacked structure is disposed in the substrate, and extends at first direction.Each stacked structure comprises a plurality of the first insulating barriers, a plurality of the second insulating barrier and many bit lines.These first stacked dielectric layers are in substrate.The second insulating barrier is disposed at respectively between the first adjacent insulating barrier.Bit line is disposed at relative two sides of each the second insulating barrier.Charge storing structure is disposed in the substrate, and extends upward and cover stacked structure in second party.The character line is disposed on the charge storing structure.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid memory body, the material of wherein said the first insulating barrier are for example different from the material of the second insulating barrier.
Aforesaid memory body, the material of wherein said the first insulating barrier for example are oxide, nitride or nitrogen oxide.
Aforesaid memory body, the material of wherein said the second insulating barrier for example are oxide, nitride or nitrogen oxide.
Aforesaid memory body, the material of wherein said bit line for example are polysilicon or amorphous silicon.
Aforesaid memory body, the material of wherein said charge storing structure for example are oxide/nitride/oxide, oxide/nitride/oxide/nitride/oxide or high dielectric constant material.
Aforesaid memory body, the material of wherein said character line for example are polysilicon.
The present invention compared with prior art has obvious advantage and beneficial effect.By technique scheme, memory body of the present invention and preparation method thereof has following advantages and beneficial effect at least: the present invention replaces stacking insulating barrier with different etch-rates at substrate, and form the zone of inserting bit line by the etching part insulating barrier, therefore can break through the restriction of existing little shadow technology and form the bit line with reduced size.In addition, therefore the distance (namely dwindling the spacing between the adjacent memory cell) about also can dwindling by the thickness of control insulating barrier between two layers the bit line also can break through the existing restriction of little shadow technology on the spacing of adjacent memory cell.By this, the formed memory body of the present invention can have higher memory density.
In sum, the invention relates to a kind of memory body and preparation method thereof.This manufacture method is to form many stacked structures that extend at first direction in substrate first.Each stacked structure comprises a plurality of the first insulating barriers and a plurality of the second insulating barrier.These first stacked dielectric layers are in substrate, and the second insulating barrier lays respectively between the first adjacent insulating barrier.Then in each stacked structure, form many grooves that extend at first direction.These grooves are positioned at relative two sides of each the second insulating barrier.Then, in groove, insert the first conductor layer.Afterwards, form many at the charge storing structure of second direction extension and at each charge storing structure formation the second conductor layer at these stacked structures.The present invention has significant progress technically, and has obvious good effect, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above and other purpose of the present invention, feature and advantage can be become apparent, below especially exemplified by preferred embodiment, and the cooperation accompanying drawing, be described in detail as follows.
Description of drawings
Figure 1A to Fig. 1 E is the stereogram of the making flow process of the memory body that illustrates according to the embodiment of the invention.
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, the memory body that foundation the present invention is proposed and preparation method thereof its embodiment, structure, method, step, feature and effect thereof are described in detail as follows.
Relevant aforementioned and other technology contents of the present invention, Characteristic can be known to present in the following detailed description that cooperates with reference to graphic preferred embodiment.Explanation by embodiment, should be to reach technological means and the effect that predetermined purpose takes to obtain one more deeply and concrete understanding to the present invention, yet appended graphic only provide with reference to the usefulness of explanation, the present invention is limited.
Figure 1A to Fig. 1 E is the stereogram of the making flow process of the memory body that illustrates according to the embodiment of the invention.At first, see also shown in Figure 1A, form many stacked structures 102 that extend in Y-direction in substrate 100.Substrate 100 for example is the dielectric substrate that is formed on the Silicon Wafer.The material of substrate 100 for example is oxide.Each bar stacked structure 102 comprises a plurality of the first insulating barrier 102a and a plurality of the second insulating barrier 102b.These first insulating barriers 102a is stacked in the substrate 100, and the second insulating barrier 102b lays respectively between the first adjacent insulating barrier 102a.That is to say, the first insulating barrier 102a and the second insulating barrier 102b sequentially alternately are formed in the substrate 100, and the superiors are the first insulating barrier 102a.The material of the first insulating barrier 102a is for example different from the material of the second insulating barrier 102b.In the present embodiment, the etch-rate of the first insulating barrier 102a is beneficial to the follow-up etch process that carries out less than the etch-rate of the second insulating barrier 102b, and this will be in hereinafter describing in detail.The material of the first insulating barrier 102a can be oxide (Hf
2O, Al
2O
3, SiO
2, be rich in the SiO of silicon
2Deng), nitride (Si
3N
4, be rich in the Si of silicon
3N
4Deng) or nitrogen oxide (SiON).The material of the second insulating barrier 102b can be oxide, nitride or nitrogen oxide equally, as long as the etch-rate of the first insulating barrier 102a is less than the etch-rate of the second insulating barrier 102b in follow-up etch process.Special one what carry is that the etch-rate of substrate 100 is also less than the etch-rate of the second insulating barrier 102b, and is badly damaged to avoid substrate 100 to be subject in follow-up etch process.
Furtherly, the formation method of stacked structure 102 for example is sequentially to form the first insulation material layer and the second insulation material layer first in substrate 100, and the superiors are the first insulation material layer.Then, the first insulation material layer in the superiors forms many cover curtain layers that extend in Y-direction, the zone of its covering wish formation stacked structure 102.Afterwards, take cover curtain layer as the cover curtain, carry out anisotropic etch process, remove part the first insulation material layer and the second insulation material layer.In the present embodiment, graphic clear in order to make, only show three stacked structures 102, but the present invention is not as limit.In addition, the present invention is not restricted the rete number in the stacked structure 102 yet.
Then, see also shown in Figure 1B, in each bar stacked structure 102, form many grooves 104 that extend in Y-direction.These grooves 104 are positioned at relative two sides of the second insulating barrier 102b of every one deck.The formation method of groove 104 for example is to carry out isotropic etching technique, removes the part of the second insulating barrier 102b.Special one carry be, because the etch-rate of the first insulating barrier 102a and substrate 100 is less than the etch-rate of the second insulating barrier 102b, therefore in the process of isotropic etching, can be easily from two sidesways of stacked structure 102 except part the second insulating barrier 102b forming many grooves 104, and can not cause serious infringement to the first insulating barrier 102a and substrate 100.Groove 104 is the zone of follow-up formation bit line, and its degree of depth can be adjusted by the control etching period, to control the size of follow-up formed bit line.Therefore in addition, in the present embodiment, form the zone of configuration bit line by etching, can break through the restriction of existing little shadow technology and further dwindle component size.
Then, see also shown in Fig. 1 C, in groove 104, insert conductor layer 106.Conductor layer 106 is as the bit line in the follow-up formed memory body.The material of conductor layer 106 for example is polysilicon or amorphous silicon.The formation method of conductor layer 106 for example is to form conductor material layer in substrate 100 first.Conductor material layer covers stacked structure 102, and inserts in the groove 104.Afterwards, carry out anisotropic etch process, remove the conductor material layer outside the groove 104.At this moment, comprised the first insulating barrier 102a, the second insulating barrier 102b and conductor layer 106 (bit line) in each bar stacked structure 102, and two conductor layers 106 lay respectively at relative two sides of the second insulating barrier 102b in same layer.
Then, see also shown in Fig. 1 D, be conformally formed the charge storage material layer 108 that covers stacked structure 102 in substrate 100.Composite bed (being the ONONO layer) or high dielectric constant layer that charge storage material layer 108 for example is the composite bed (being the ONO layer) that is made of oxide layer/nitration case/oxide layer, be made of oxide layer/nitration case/oxide layer/nitration case/oxide layer.The formation method of charge storage material layer 108 is well known to those skilled in the art, at this NES.Then, form conductor material layer 110 at charge storage material layer 108.The material of conductor material layer 110 for example is polysilicon.Then, form many cover curtain layers 112 that extend at directions X at conductor material layer 110.Cover curtain layer 112 for example is photoresist layer, and it covers the zone that follow-up wish forms the character line.
Afterwards, see also shown in Fig. 1 E, take cover curtain layer 112 as the cover curtain, remove segment conductor material layer 110 and Partial charge storage material layer 108, extend and cover the charge storing structure 114 of stacked structure 102 and be positioned at character line 116 on these charge storing structures 114 at directions X to form many.Thus, can form the Three Dimensional Memory body 10 with higher memory density.
In the memory body 10 of the present embodiment, each bar stacked structure 102 has and sequentially replaces the first stacking insulating barrier 102a and the second insulating barrier 102b, and two sides of the second insulating barrier 102b of every one deck dispose respectively a bit line 106, therefore can effectively improve the memory density of memory body 10.
In detail, memory body 10 has four layer of second insulating barrier 102b, and two sides of the second insulating barrier 102b of every one deck dispose respectively a bit line 106.In addition, dispose five charge storing structures 114 and character line 116 on each bar stacked structure 102.Therefore, for the memory body 10 shown in Fig. 1 E, the charge storing structure 114 of each bar stacked structure 102 and its top and character line 116 can consist of 40 memory cells (memory cell can as dotted line shown in), thereby can have higher memory density.
In addition, in memory body 10, the spacing between two layers the memory cell is the thickness of the first insulating barrier 102a up and down.In other words, in the present embodiment, can control up and down spacing between two layers the memory cell by the thickness of control the first insulating barrier 102a, therefore can break through the restriction of existing little shadow technology and further dwindle spacing between the adjacent memory cell.
In addition, for the memory body 10 of the present embodiment, can utilize the FN that generally knows to inject (Fowler-Nordheim injection) and come it is carried out sequencing step and erase step.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, although the present invention discloses as above with preferred embodiment, yet be not to limit the present invention, any those skilled in the art, within not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, any simple modification that foundation technical spirit of the present invention is done above embodiment, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (10)
1. the manufacture method of a memory body is characterized in that it may further comprise the steps:
Form many stacked structures that extend at a first direction in a substrate, each stacked structure comprises a plurality of the first insulating barriers and a plurality of the second insulating barrier, those first stacked dielectric layers are in this substrate, and those second insulating barriers lay respectively between those adjacent first insulating barriers;
Form many grooves that extend at this first direction in each stacked structure, those grooves are positioned at relative two sides of each the second insulating barrier;
In those grooves, insert one first conductor layer; And
Form many at the charge storing structure of second direction extension and at each charge storing structure formation one second conductor layer at those stacked structures.
2. the manufacture method of memory body according to claim 1 is characterized in that the etch-rate of those the first insulating barriers wherein is less than the etch-rate of those the second insulating barriers.
3. the manufacture method of memory body according to claim 2, it is characterized in that wherein the formation method of those grooves comprises carries out first-class tropism's etch process, removes the part of each the second insulating barrier.
4. the manufacture method of memory body according to claim 1 is characterized in that wherein the formation method of those stacked structures comprises:
Form a plurality of the first insulation material layers and a plurality of the second insulation material layer in this substrate, and the superiors are this first insulation material layer;
This first insulation material layer in the superiors forms many cover curtain layers that extend at this first direction; And
Take those cover curtain layers as the cover curtain, remove those first insulation material layers of part and those second insulation material layers of part.
5. the manufacture method of memory body according to claim 1 is characterized in that the formation method of wherein said the first conductor layer comprises:
Form a conductor material layer in this substrate, this conductor material layer covers those stacked structures, and inserts in those grooves; And
Carry out an anisotropic etch process, remove this outer conductor material layer of those grooves.
6. the manufacture method of memory body according to claim 1 is characterized in that wherein the formation method of those charge storing structures and those the second conductor layers comprises:
Form a charge storage material layer in this substrate, this charge storage material layer covers those stacked structures;
Form a conductor material layer at this charge storage material layer;
Form many cover curtain layers that extend in this second direction at this conductor material layer; And
Take those cover curtain layers as the cover curtain, remove this conductor material layer of part and this charge storage material layer of part.
7. memory body is characterized in that it comprises:
Many stacked structures are disposed in the substrate, and extend at a first direction, and each stacked structure comprises:
A plurality of the first insulating barriers are stacked in this substrate;
A plurality of the second insulating barriers are disposed at respectively between those adjacent first insulating barriers; And
Many bit lines are disposed at relative two sides of each the second insulating barrier;
Many charge storing structures are disposed in this substrate, and extend upward and cover many character lines in a second party, are disposed on those charge storing structures.
8. memory body according to claim 7 is characterized in that the material of wherein said the first insulating barrier is different from the material of this second insulating barrier.
9. memory body according to claim 8 is characterized in that wherein the material of those the first insulating barriers comprises oxide, nitride or nitrogen oxide.
10. memory body according to claim 8 is characterized in that wherein the material of those the second insulating barriers comprises oxide, nitride or nitrogen oxide.
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| CN201110319436.3A CN103050445B (en) | 2011-10-13 | 2011-10-13 | Memory body and preparation method thereof |
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| CN201110319436.3A CN103050445B (en) | 2011-10-13 | 2011-10-13 | Memory body and preparation method thereof |
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| CN103050445B CN103050445B (en) | 2015-09-09 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104124246A (en) * | 2013-04-26 | 2014-10-29 | 旺宏电子股份有限公司 | Memory device and manufacturing method thereof |
| CN107293549A (en) * | 2016-03-30 | 2017-10-24 | 旺宏电子股份有限公司 | Semiconductor structure and its manufacture method |
| CN107978674A (en) * | 2016-10-25 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method, electronic device |
| US10559592B1 (en) | 2018-08-08 | 2020-02-11 | Yangtze Memory Technologies Co., Ltd. | Memory device and forming method thereof |
| CN112670296A (en) * | 2020-12-24 | 2021-04-16 | 长江存储科技有限责任公司 | Three-dimensional memory structure and preparation method thereof |
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| CN101764134A (en) * | 2008-11-25 | 2010-06-30 | 三星电子株式会社 | Three-dimensional semiconductor devices and methods of operating the same |
| CN102034760A (en) * | 2009-09-29 | 2011-04-27 | 三星电子株式会社 | Three-dimensional semiconductor memory device and method of fabricating the same |
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| CN101764134A (en) * | 2008-11-25 | 2010-06-30 | 三星电子株式会社 | Three-dimensional semiconductor devices and methods of operating the same |
| CN102034760A (en) * | 2009-09-29 | 2011-04-27 | 三星电子株式会社 | Three-dimensional semiconductor memory device and method of fabricating the same |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104124246A (en) * | 2013-04-26 | 2014-10-29 | 旺宏电子股份有限公司 | Memory device and manufacturing method thereof |
| CN104124246B (en) * | 2013-04-26 | 2017-09-08 | 旺宏电子股份有限公司 | Memory storage and its manufacture method |
| CN107293549A (en) * | 2016-03-30 | 2017-10-24 | 旺宏电子股份有限公司 | Semiconductor structure and its manufacture method |
| CN107293549B (en) * | 2016-03-30 | 2019-10-18 | 旺宏电子股份有限公司 | Semiconductor structure and its manufacturing method |
| CN107978674A (en) * | 2016-10-25 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method, electronic device |
| US10559592B1 (en) | 2018-08-08 | 2020-02-11 | Yangtze Memory Technologies Co., Ltd. | Memory device and forming method thereof |
| WO2020029115A1 (en) * | 2018-08-08 | 2020-02-13 | Yangtze Memory Technologies Co., Ltd. | Memory device and forming method thereof |
| CN112670296A (en) * | 2020-12-24 | 2021-04-16 | 长江存储科技有限责任公司 | Three-dimensional memory structure and preparation method thereof |
| CN112670296B (en) * | 2020-12-24 | 2023-10-27 | 长江存储科技有限责任公司 | Three-dimensional memory structure and preparation method thereof |
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| CN103050445B (en) | 2015-09-09 |
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