CN103050445B - Memory body and preparation method thereof - Google Patents
Memory body and preparation method thereof Download PDFInfo
- Publication number
- CN103050445B CN103050445B CN201110319436.3A CN201110319436A CN103050445B CN 103050445 B CN103050445 B CN 103050445B CN 201110319436 A CN201110319436 A CN 201110319436A CN 103050445 B CN103050445 B CN 103050445B
- Authority
- CN
- China
- Prior art keywords
- those
- insulating barrier
- memory body
- substrate
- stacked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title abstract description 10
- 230000004888 barrier function Effects 0.000 claims abstract description 83
- 238000000034 method Methods 0.000 claims abstract description 49
- 239000004020 conductor Substances 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims description 40
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 24
- 239000012774 insulation material Substances 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 12
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 238000003860 storage Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 abstract description 5
- 239000000243 solution Substances 0.000 description 7
- 230000008901 benefit Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000006396 nitration reaction Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000011232 storage material Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- SEOYNUHKXVGWFU-UHFFFAOYSA-N mu-oxidobis(oxidonitrogen) Chemical compound O=NON=O SEOYNUHKXVGWFU-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention relates to a kind of memory body and preparation method thereof.This manufacture method is in substrate, first form many stacked structures extended at first direction.Every stacked arrangement comprises multiple first insulating barrier and multiple second insulating barrier.These first stacked dielectric layers are in substrate, and the second insulating barrier lays respectively between the first adjacent insulating barrier.Then in every stacked arrangement, form many grooves extended at first direction.These grooves are positioned at relative two sides of each the second insulating barrier.Then, the first conductor layer is inserted in the trench.Afterwards, these stacked structures are formed many second direction extend charge storing structure and on each charge storing structure, form the second conductor layer.The present invention replaces the stacking insulating barrier with different etch-rate by substrate, and the region inserting bit line is formed by etching part insulating barrier, the restriction that can break through existing micro-shadow technology forms the bit line with reduced size, improves the memory density of memory body.
Description
Technical field
The present invention relates to a kind of memory body and preparation method thereof, particularly relate to one and there is memory body of higher memory density (memory density) and preparation method thereof.
Background technology
Non-volatility memory due to have stored in the data advantage that also can not disappear after a loss of power, therefore must possess this type of memory body in many electric equipment products, to maintain normal running during electric equipment products start.
Along with the size of electronic component reduces, the size of the memory body be made up of memory cell also reduces thereupon.But be limited to current micro-shadow technology, the memory cell of General Two-Dimensional (such as reduces the spacing between adjacent memory born of the same parents) and is also restricted on dimension reduction.In addition, because the size of memory cell reduces, also result in the reduction of memory density.
In order to increase the data storage ability of memory body, three-dimensional memory cell has been subject to showing great attention to of industry.But for current Three Dimensional Memory born of the same parents array processes, it has higher complexity, and in the reduction of size, be still subject to the restriction of existing micro-shadow technology.
As can be seen here, above-mentioned existing memory body and preparation method thereof, in product structure, manufacture method and use, obviously still has inconvenience and defect, and is urgently further improved.In order to solve above-mentioned Problems existing, relevant manufactures there's no one who doesn't or isn't seeks solution painstakingly, but have no applicable design for a long time to be completed by development always, and common product and method do not have appropriate structure and method to solve the problem, this is obviously the anxious problem for solving of relevant dealer.Therefore how to found a kind of new memory body and preparation method thereof, one of current important research and development problem of real genus, also becomes the target that current industry pole need be improved.
Summary of the invention
The object of the invention is to, the defect that the manufacture method overcoming existing memory body exists, and provide a kind of manufacture method of new memory body, technical problem to be solved makes it can produce the memory body with higher memory density, is very suitable for practicality.
Another object of the present invention is to, overcome the defect that existing memory body exists, and provide a kind of new memory body, technical problem to be solved makes it have higher memory density, thus be more suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.The manufacture method of a kind of memory body proposed according to the present invention, the method is in substrate, first form many stacked structures extended at first direction.Every stacked arrangement comprises multiple first insulating barrier and multiple second insulating barrier.These first stacked dielectric layers are in substrate, and the second insulating barrier lays respectively between the first adjacent insulating barrier.Then, in every stacked arrangement, form many grooves extended at first direction.These grooves are positioned at relative two sides of each the second insulating barrier.Then, the first conductor layer is inserted in the trench.Afterwards, these stacked structures are formed many second direction extend charge storing structure and on each charge storing structure, form the second conductor layer.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of aforesaid memory body, the etch-rate of the first wherein said insulating barrier is such as less than the etch-rate of the second insulating barrier.
The manufacture method of aforesaid memory body, the material of the first wherein said insulating barrier is such as oxide, nitride or nitrogen oxide.
The manufacture method of aforesaid memory body, the material of the second wherein said insulating barrier is such as oxide, nitride or nitrogen oxide.
The manufacture method of aforesaid memory body, the formation method of wherein said groove is such as carry out isotropic etch process, to remove a part for each the second insulating barrier.
The manufacture method of aforesaid memory body, the formation method of wherein said stacked structure is such as first in substrate, form the first insulation material layer and the second insulation material layer, and the superiors are the first insulation material layer.Then, the first insulation material layer of the superiors is formed many cover curtain layers extended at first direction.Afterwards, be cover curtain with cover curtain layer, remove part first insulation material layer and the second insulation material layer.
The manufacture method of aforesaid memory body, the formation method of the first wherein said conductor layer is such as first in substrate, form conductor material layer.Conductor material layer covers stacked structure, and inserts in groove.Afterwards, carry out anisotropic etch process, remove the conductor material layer outside groove.
The manufacture method of aforesaid memory body, the formation method of wherein said charge storing structure and the second conductor layer is such as first in substrate, form the charge storage layers covering stacked structure.Then, charge storage layers forms conductor material layer.Then, conductor material layer is formed many cover curtain layers extended in second direction.Afterwards, be cover curtain with cover curtain layer, remove segment conductor material layer and Partial charge storage material layer.
The object of the invention to solve the technical problems also realizes by the following technical solutions.According to a kind of memory body that the present invention proposes, it comprises many stacked structures, many charge storing structures and many character lines.Stacked structure is configured in substrate, and extends at first direction.Every stacked arrangement comprises multiple first insulating barrier, multiple second insulating barrier and many bit lines.These first stacked dielectric layers are in substrate.Second insulating barrier is configured between the first adjacent insulating barrier respectively.Bit line is configured at relative two sides of each the second insulating barrier.Charge storing structure is configured in substrate, and extends in a second direction and cover stacked structure.Character line is configured on charge storing structure.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid memory body, the material of the first wherein said insulating barrier is such as different from the material of the second insulating barrier.
Aforesaid memory body, the material of the first wherein said insulating barrier is such as oxide, nitride or nitrogen oxide.
Aforesaid memory body, the material of the second wherein said insulating barrier is such as oxide, nitride or nitrogen oxide.
Aforesaid memory body, the material of wherein said bit line is such as polysilicon or amorphous silicon.
Aforesaid memory body, the material of wherein said charge storing structure is such as oxide/nitride/oxide, oxide/nitride/oxide/nitride/oxide or high dielectric constant material.
Aforesaid memory body, the material of wherein said character line is such as polysilicon.
The present invention compared with prior art has obvious advantage and beneficial effect.By technique scheme, memory body of the present invention and preparation method thereof at least has following advantages and beneficial effect: the present invention replaces the stacking insulating barrier with different etch-rate on substrate, and the region inserting bit line is formed by etching part insulating barrier, therefore can break through the restriction of existing micro-shadow technology and form the bit line with reduced size.In addition, also by the distance (namely reducing the spacing between adjacent memory born of the same parents) between the bit line controlling the thickness of insulating barrier and reduce upper and lower two layers, the restriction of existing micro-shadow technology in the spacing of adjacent memory born of the same parents can therefore also can be broken through.By this, the memory body that the present invention is formed can have higher memory density.
In sum, the invention relates to a kind of memory body and preparation method thereof.This manufacture method is in substrate, first form many stacked structures extended at first direction.Every stacked arrangement comprises multiple first insulating barrier and multiple second insulating barrier.These first stacked dielectric layers are in substrate, and the second insulating barrier lays respectively between the first adjacent insulating barrier.Then in every stacked arrangement, form many grooves extended at first direction.These grooves are positioned at relative two sides of each the second insulating barrier.Then, the first conductor layer is inserted in the trench.Afterwards, these stacked structures are formed many second direction extend charge storing structure and on each charge storing structure, form the second conductor layer.The present invention has significant progress technically, and has obvious good effect, is really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of specification, and can become apparent to allow above and other object of the present invention, feature and advantage, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Figure 1A to Fig. 1 E is the stereogram of the Making programme of the memory body illustrated according to the embodiment of the present invention.
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to the memory body proposed according to the present invention and preparation method thereof its embodiment, structure, method, step, feature and effect thereof, be described in detail as follows.
Aforementioned and other technology contents, Characteristic for the present invention, can know and present in the detailed description of following cooperation with reference to graphic preferred embodiment.By the explanation of embodiment, should to the present invention for the technological means reaching predetermined object and take and effect obtain one more deeply and concrete understanding, but institute's accompanying drawings is only to provide with reference to the use with explanation, is not used for being limited the present invention.
Figure 1A to Fig. 1 E is the stereogram of the Making programme of the memory body illustrated according to the embodiment of the present invention.First, refer to shown in Figure 1A, substrate 100 is formed many stacked structures extended in the Y direction 102.Substrate 100 is such as the dielectric substrate be formed on Silicon Wafer.The material of substrate 100 is such as oxide.Each stacked structure 102 comprises multiple first insulating barrier 102a and multiple second insulating barrier 102b.These first insulating barriers 102a is stacked in substrate 100, and the second insulating barrier 102b lays respectively between the first adjacent insulating barrier 102a.That is, the first insulating barrier 102a and the second insulating barrier 102b is sequentially alternately formed in substrate 100, and the superiors are the first insulating barrier 102a.The material of the first insulating barrier 102a is such as different from the material of the second insulating barrier 102b.In the present embodiment, the etch-rate of the first insulating barrier 102a is less than the etch-rate of the second insulating barrier 102b, and be beneficial to follow-up carried out etch process, this will in hereafter describing in detail.The material of the first insulating barrier 102a can be oxide (Hf
2o, Al
2o
3, SiO
2, be rich in the SiO of silicon
2deng), nitride (Si
3n
4, be rich in the Si of silicon
3n
4deng) or nitrogen oxide (SiON).The material of the second insulating barrier 102b can be oxide, nitride or nitrogen oxide equally, as long as the etch-rate of the first insulating barrier 102a is less than the etch-rate of the second insulating barrier 102b in follow-up etch process.Special one carries, and the etch-rate of substrate 100 is also less than the etch-rate of the second insulating barrier 102b, badly damaged to avoid substrate 100 to be subject in follow-up etch process.
Furtherly, the formation method of stacked structure 102 is such as first in substrate 100, sequentially form the first insulation material layer and the second insulation material layer, and the superiors are the first insulation material layer.Then, the first insulation material layer of the superiors forms many cover curtain layers extended in the Y direction, it covers the region for forming stacked structure 102.Afterwards, take cover curtain layer as cover curtain, carry out anisotropic etch process, remove part first insulation material layer and the second insulation material layer.In the present embodiment, graphic clear in order to make, only show three stacked structures 102, but the present invention is not as limit.In addition, the present invention is not also restricted the rete number in stacked structure 102.
Then, refer to shown in Figure 1B, in each stacked structure 102, form many grooves extended in the Y direction 104.These grooves 104 are positioned at relative two sides of the second insulating barrier 102b of every one deck.The formation method of groove 104 is such as carry out isotropic etch process, removes a part of the second insulating barrier 102b.Special one carry be, etch-rate due to the first insulating barrier 102a and substrate 100 is less than the etch-rate of the second insulating barrier 102b, therefore in the process of isotropic etching, easily can remove part second insulating barrier 102b to form many grooves 104 from two sidesways of stacked structure 102, and serious infringement can not be caused to the first insulating barrier 102a and substrate 100.Groove 104 is the region of follow-up formation bit line, and its degree of depth can adjust by control etching period, to control the size of follow-up formed bit line.In addition, in the present embodiment, by etching the region forming configuration bit line, therefore can break through the restriction of existing micro-shadow technology and reducing component size further.
Then, refer to shown in Fig. 1 C, in groove 104, insert conductor layer 106.Conductor layer 106 is as the bit line in follow-up formed memory body.The material of conductor layer 106 is such as polysilicon or amorphous silicon.The formation method of conductor layer 106 is such as first in substrate 100, form conductor material layer.Conductor material layer covers stacked structure 102, and inserts in groove 104.Afterwards, carry out anisotropic etch process, remove the conductor material layer outside groove 104.Now, in each stacked structure 102, include the first insulating barrier 102a, the second insulating barrier 102b and conductor layer 106 (bit line), and two conductor layers 106 lay respectively at relative two sides of the second insulating barrier 102b within the same layer.
Then, refer to shown in Fig. 1 D, substrate 100 is conformally formed the charge storage layers 108 covering stacked structure 102.Charge storage layers 108 is such as the composite bed (i.e. ONO layer) be made up of oxide layer/nitration case/oxide layer, the composite bed (i.e. ONONO layer) be made up of oxide layer/nitration case/oxide layer/nitration case/oxide layer or high dielectric constant layer.The formation method of charge storage layers 108 is well known to those skilled in the art, at this NES.Then, charge storage layers 108 forms conductor material layer 110.The material of conductor material layer 110 is such as polysilicon.Then, conductor material layer 110 is formed many cover curtain layers 112 extended in X-direction.Cover curtain layer 112 is such as photoresist layer, and it covers the follow-up region for forming character line.
Afterwards, refer to shown in Fig. 1 E, be cover curtain with cover curtain layer 112, remove segment conductor material layer 110 and Partial charge storage material layer 108, extend in the X direction and the charge storing structure 114 covering stacked structure 102 and the character line 116 be positioned on these charge storing structures 114 to form many.Thus, the Three Dimensional Memory body 10 with higher memory density can be formed.
In the memory body 10 of the present embodiment, each stacked structure 102 has sequentially alternately the first stacking insulating barrier 102a and the second insulating barrier 102b, and two sides of the second insulating barrier 102b of every one deck are configured with a bit line 106 respectively, therefore effectively can improve the memory density of memory body 10.
In detail, memory body 10 has four layer of second insulating barrier 102b, and two sides of the second insulating barrier 102b of every one deck are configured with a bit line 106 respectively.In addition, each stacked structure 102 is configured with five charge storing structures 114 and character line 116.Therefore, for the memory body 10 shown in Fig. 1 E, each stacked structure 102 and charge storing structure 114 and the character line 116 above it can form 40 memory cells (memory cell can shown in dotted line), thus can have higher memory density.
In addition, in memory body 10, the spacing between the memory cell of upper and lower two layers is the thickness of the first insulating barrier 102a.In other words, in the present embodiment, the spacing between the memory cell that can control upper and lower two layers by the thickness of control first insulating barrier 102a, therefore can break through the restriction of existing micro-shadow technology and the spacing reduced further between adjacent memory born of the same parents.
In addition, for the memory body 10 of the present embodiment, the FN generally known can be utilized to inject (Fowler-Nordheim injection) programmed steps and erase step are carried out to it.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when the method and technology contents that can utilize above-mentioned announcement are made a little change or be modified to the Equivalent embodiments of equivalent variations, in every case be the content not departing from technical solution of the present invention, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (10)
1. a manufacture method for memory body, is characterized in that it comprises the following steps:
A substrate is formed many stacked structures extended at a first direction, every stacked arrangement comprises multiple first insulating barrier and multiple second insulating barrier, those first stacked dielectric layers are in this substrate, and those second insulating barriers lay respectively between those adjacent first insulating barriers;
In every stacked arrangement, form many grooves extended at this first direction, those grooves are positioned at relative two sides of each the second insulating barrier;
One first conductor layer is inserted in those grooves; And
Those stacked structures are formed many one second direction extend charge storing structure and on each charge storing structure formed one second conductor layer.
2. the manufacture method of memory body according to claim 1, is characterized in that the etch-rate of wherein those the first insulating barriers is less than the etch-rate of those the second insulating barriers.
3. the manufacture method of memory body according to claim 2, is characterized in that the formation method of wherein those grooves comprises and carries out an isotropic etch process, remove a part for each the second insulating barrier.
4. the manufacture method of memory body according to claim 1, is characterized in that the formation method of wherein those stacked structures comprises:
Form multiple first insulation material layer and multiple second insulation material layer on this substrate, and the superiors are this first insulation material layer;
This first insulation material layer of the superiors forms many cover curtain layers extended at this first direction; And
With those cover curtain layers for cover curtain, remove those first insulation material layers of part and those second insulation material layers of part.
5. the manufacture method of memory body according to claim 1, is characterized in that the formation method of the first wherein said conductor layer comprises:
Form a conductor material layer on this substrate, this conductor material layer covers those stacked structures, and inserts in those grooves; And
Carry out an anisotropic etch process, remove this conductor material layer outside those grooves.
6. the manufacture method of memory body according to claim 1, is characterized in that the formation method of wherein those charge storing structures and those the second conductor layers comprises:
Form a charge storage layers on this substrate, this charge storage layers covers those stacked structures;
This charge storage layers is formed a conductor material layer;
This conductor material layer is formed many cover curtain layers extended in this second direction; And
With those cover curtain layers for cover curtain, remove this conductor material layer of part and this charge storage layers of part.
7. a memory body, is characterized in that it comprises:
Many stacked structures, are configured in a substrate, and extend at a first direction, and every stacked arrangement comprises:
Multiple first insulating barrier, is stacked in this substrate;
Multiple second insulating barrier, is configured between those adjacent first insulating barriers respectively; And
Many bit lines, are configured at relative two sides of each the second insulating barrier;
Many charge storing structures, are configured in this substrate, and extend in a second direction and cover those stacked structures;
Many character lines, are configured on those charge storing structures.
8. memory body according to claim 7, is characterized in that the material of the first wherein said insulating barrier is different from the material of this second insulating barrier.
9. memory body according to claim 8, is characterized in that the material of wherein those the first insulating barriers comprises oxide, nitride or nitrogen oxide.
10. memory body according to claim 8, is characterized in that the material of wherein those the second insulating barriers comprises oxide, nitride or nitrogen oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110319436.3A CN103050445B (en) | 2011-10-13 | 2011-10-13 | Memory body and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110319436.3A CN103050445B (en) | 2011-10-13 | 2011-10-13 | Memory body and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103050445A CN103050445A (en) | 2013-04-17 |
| CN103050445B true CN103050445B (en) | 2015-09-09 |
Family
ID=48063042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110319436.3A Active CN103050445B (en) | 2011-10-13 | 2011-10-13 | Memory body and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103050445B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104124246B (en) * | 2013-04-26 | 2017-09-08 | 旺宏电子股份有限公司 | Memory storage and its manufacture method |
| TWI625845B (en) * | 2016-03-30 | 2018-06-01 | 旺宏電子股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN107978674A (en) * | 2016-10-25 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method, electronic device |
| CN109155319B (en) * | 2018-08-08 | 2019-09-10 | 长江存储科技有限责任公司 | Memory device and the method for forming memory device |
| CN112670296B (en) * | 2020-12-24 | 2023-10-27 | 长江存储科技有限责任公司 | Three-dimensional memory structure and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101764134A (en) * | 2008-11-25 | 2010-06-30 | 三星电子株式会社 | Three-dimensional semiconductor devices and methods of operating the same |
| CN102034760A (en) * | 2009-09-29 | 2011-04-27 | 三星电子株式会社 | Three-dimensional semiconductor memory device and method of fabricating the same |
-
2011
- 2011-10-13 CN CN201110319436.3A patent/CN103050445B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101764134A (en) * | 2008-11-25 | 2010-06-30 | 三星电子株式会社 | Three-dimensional semiconductor devices and methods of operating the same |
| CN102034760A (en) * | 2009-09-29 | 2011-04-27 | 三星电子株式会社 | Three-dimensional semiconductor memory device and method of fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103050445A (en) | 2013-04-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101110355B1 (en) | 3d stacked array having cut-off gate line and fabrication method thereof | |
| US9543313B2 (en) | Nonvolatile memory device and method for fabricating the same | |
| KR101206508B1 (en) | Method for manufacturing 3d-nonvolatile memory device | |
| CN103426824B (en) | The method for manufacturing nonvolatile semiconductor memory member | |
| CN103050445B (en) | Memory body and preparation method thereof | |
| JP2018160612A (en) | Semiconductor device and manufacturing method for the same | |
| CN107946310B (en) | 3D NAND flash memory preparation method adopting air gap as dielectric layer and flash memory | |
| KR20120066331A (en) | 3d structured non-volatile memory device and method for manufacturing the same | |
| US8921922B2 (en) | Nonvolatile memory device and method for fabricating the same | |
| KR20120035468A (en) | Three dimensional semiconductor memory device and method of fabricating the same | |
| KR101949375B1 (en) | Method for fabricating nonvolatile memory device | |
| CN109742084B (en) | Electronic equipment, three-dimensional memory and manufacturing method thereof | |
| KR20140122057A (en) | Nonvolatile memory device and method for fabricating the same | |
| CN110299366B (en) | Three-dimensional memory and forming method thereof | |
| TW200921859A (en) | Method for manufacturing flash memory device | |
| CN112820736A (en) | Three-dimensional memory and preparation method thereof | |
| US9048139B2 (en) | Method for fabricating non-volatile memory device | |
| KR20140030483A (en) | Nonvolatile memory device and method for fabricating the same | |
| TWI440138B (en) | Memory and manufacturing method thereof | |
| KR20090118816A (en) | Flash memory device and manufacturing method thereof | |
| CN110265404B (en) | Laminated structure for three-dimensional memory, three-dimensional memory and preparation method thereof | |
| TW201640652A (en) | Method for forming a semiconductor structure | |
| CN110137176B (en) | 3D NAND flash memory and preparation method | |
| KR101162197B1 (en) | 3d stacked nand flash memory array having connection gate and fabrication method of the same | |
| US20140061741A1 (en) | Semiconductor device and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |