CN104124246B - Memory storage and its manufacture method - Google Patents
Memory storage and its manufacture method Download PDFInfo
- Publication number
- CN104124246B CN104124246B CN201310150886.3A CN201310150886A CN104124246B CN 104124246 B CN104124246 B CN 104124246B CN 201310150886 A CN201310150886 A CN 201310150886A CN 104124246 B CN104124246 B CN 104124246B
- Authority
- CN
- China
- Prior art keywords
- layer
- memory storage
- substrate
- grid layer
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention relates to a kind of memory storage and its manufacture method.The memory storage includes a substrate, memory material layer, one first dielectric layer, a first grid layer, second grid layer and source/drain region.Wherein, substrate has a groove, and memory material layer is formed on the side wall of groove.First dielectric layer, first grid layer and second grid layer are filled in groove, and the first dielectric layer is formed between first grid layer and second grid layer.Source/drain regions are formed in substrate and are adjacent to memory material layer.The direction that the direction of first grid layer extension extends perpendicular to source/drain regions.The present invention additionally provides the manufacture method of above-mentioned memory storage simultaneously.The present invention makes the width of wordline in memory storage be with the height definition of first grid layer, so that memory storage can still have good operation efficiency in the case where size reduces.
Description
Technical field
The present invention relates to a kind of memory storage and its manufacture method, more particularly to one kind has size concurrently and reduced and good behaviour
Make the memory storage and its manufacture method of efficiency.
Background technology
Making wordline (wordline herein, as word-line, herein referred to as wordline of memory storage）Technique in,
Traditional mode be first deposition whole piece polysilicon (polysilicon) layer after, then etch polysilicon layer and form a plurality of
Dielectric material is inserted in wordline, then the space etched between wordline.However, with the diminution of memory storage, wordline is wide
Degree and gap each other also reduce, and make wordline easily with etch process because the polysilicon that etching is not exclusively remained is sent out
Raw short circuit, or wordline width are uneven, and causing the reliability of memory storage reduces.Also, wordline width, which reduces, to be also resulted in
The efficiency of memory storage is not good.
Therefore, the designers of this area are directed to developmental research and improve the operation efficiency of memory storage and reliable invariably
Property.
The content of the invention
It is an object of the present invention to provide a kind of new memory storage and its manufacture method, technical problem to be solved
Be make wordline in memory storage width (word line width) be with first grid layer height definition so that memory dress
Good operation efficiency can still be had in the case where size reduces by putting, and be very suitable for practicality.
The object of the invention to solve the technical problems is realized using following technical scheme.According to present invention proposition
A kind of memory storage.It includes a substrate, memory material layer, one first dielectric layer, a first grid layer, a second grid
Layer and a doping bar.Substrate has a groove, and memory material layer is formed on the side wall of groove.First dielectric layer, first
Grid layer and second grid layer are filled in groove, and the first dielectric layer is formed between first grid layer and second grid layer.
Doping bar is formed in substrate and is adjacent to memory material layer.Wherein the direction of first grid layer extension is perpendicular to source/drain
The direction of area's extension.
The object of the invention to solve the technical problems can be also applied to the following technical measures to achieve further.
Foregoing memory storage, wherein the doping bar include multiple source/drain pole region.
Foregoing memory storage, the wherein substrate have more an at least long recess, and the doping bar is formed at the long recess
Within surface (within).
Foregoing memory storage, in addition to：One second dielectric layer, second dielectric layer is formed in the long recess.
The object of the invention to solve the technical problems is also realized using following technical scheme.According to proposed by the present invention
A kind of memory storage.It includes a substrate, multiple memory materials layer, multiple first dielectric layers, multiple first grids layer, Duo Ge
Two grid layers and multiple doping bars.Substrate has multiple grooves.Memory material layer is formed on the side wall of each groove.Each
One dielectric layer is formed between each first grid layer and each second grid layer and is filled in each groove.Doping bar is formed at base
Plate is interior and is adjacent to memory material layer.The direction of first grid layer extension is perpendicular to the direction of doping bar extension.
The object of the invention to solve the technical problems is realized using following technical scheme again in addition.Carried according to the present invention
A kind of manufacture method of the memory storage gone out.It comprises the following steps.A substrate is provided, substrate has a groove；One is formed to remember
Material layer is recalled on the side wall of groove；Formed one first dielectric layer, a first grid layer and a second grid layer be filled in it is recessed
In groove, wherein the first dielectric series of strata are formed between first grid layer and second grid layer；And formed source/drain region in
Substrate is interior and is adjacent to memory material layer, the direction that the direction that wherein first grid layer extends extends perpendicular to source/drain regions.
The object of the invention to solve the technical problems can be also applied to the following technical measures to achieve further.
The manufacture method of foregoing memory storage, wherein forming first dielectric layer, first grid layer and the second gate
The step of pole layer, includes：Form a conductive material layer；The conductive material layer is etched to form a gap (gap), the gap should
Conductive material layer, which separates, is split into two parts；A dielectric materials layer is formed on the conductive material layer and in the gap；And grind
The dielectric materials layer and the conductive material layer is ground to form first dielectric layer, first grid layer and second grid layer.
The manufacture method of foregoing memory storage, wherein form the source/drain regions includes in the step in the substrate：It is right
The substrate carries out an ion implant (ion implantation) technique to form the source/drain regions in the substrate.
The manufacture method of foregoing memory storage, in addition to one second dielectric layer is formed on the source/drain regions.
The object of the invention to solve the technical problems is also realized using following technical scheme in addition.Carried according to the present invention
A kind of manufacture method of the memory storage gone out.It comprises the following steps.A substrate is provided, wherein substrate has multiple grooves；Shape
Into multiple memory materials layer respectively on the side wall of each groove;Formed multiple first dielectric layers, multiple first grids layer and it is many
Individual second grid layer, wherein each first dielectric layer is formed between each first grid layer and each second grid layer and is filled in each
In groove；And formed it is multiple doping bars in substrate and be adjacent to memory material layer；The direction that wherein first grid layer extends
Perpendicular to the direction of doping bar extension.
The object of the invention to solve the technical problems can be also applied to the following technical measures to achieve further.
The manufacture method of foregoing memory storage, wherein form those doping bars includes in the step in the substrate：To this
Substrate carries out an ion implant (ion implantation) technique to form those doping bars in the substrate.
The present invention has clear advantage and beneficial effect compared with prior art.By above-mentioned technical proposal, the present invention
Memory storage and its manufacture method at least have following advantages and beneficial effect：The present invention makes the width of wordline in memory storage be
With the height definition of first grid layer, so that memory storage can still have good operation in the case where size reduces
Efficiency.
In summary, the invention relates to a kind of memory storage and its manufacture method.The memory storage include a substrate,
One memory material layer, one first dielectric layer, a first grid layer, second grid layer and source/drain region.Wherein, base
Plate has a groove, and memory material layer is formed on the side wall of groove.First dielectric layer, first grid layer and second grid layer
It is filled in groove, the first dielectric layer is formed between first grid layer and second grid layer.Source/drain regions are formed at base
Plate is interior and is adjacent to memory material layer.The direction that the direction of first grid layer extension extends perpendicular to source/drain regions.The present invention
Technically there is significant progress, and be really a new and innovative, progressive, practical new design with obvious good effect.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention,
And can be practiced according to the content of specification, and in order to allow the above and other objects, features and advantages of the present invention can
Become apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, describe in detail as follows.
Brief description of the drawings
Fig. 1 is the top view for illustrating memory storage according to an embodiment of the invention.
Fig. 2A is to illustrate the profile along Fig. 1 hatching I-I.
Fig. 2 B are to illustrate the profile along Fig. 1 hatching II-II.
Fig. 2 C are to illustrate the stereogram that Fig. 1 dotted line frames a encloses region.
Fig. 3 is the stereogram of the mnemon for the memory storage for illustrating Fig. 1.
Fig. 4 to Figure 11 D is the schematic diagram for the manufacture method for illustrating the memory storage according to one embodiment of the invention.
Figure 12 is the circuit diagram for the memory storage for illustrating the embodiment according to Fig. 1.
Figure 13 is wordline width (word line the width)-transconductance value for illustrating memory storage
(transconductance, Gm) curve map.
100：Memory storage
110、110’：Substrate
120：Memory material layer
120’：Memory material coating layer
120a、131a、140a、170a：Top surface
131：First grid layer
131b:Base
131s、150s：Side wall
133：Second grid layer
135：First dielectric layer
140：Adulterate bar
150：Groove
150b:Bottom
170：Second dielectric layer
630：Conductive material layer
631、633：The part of conductive material layer
635：Dielectric materials layer
C、C’：Mnemon
D1、D2:Direction
G：Gap
HM1、HM2：Patterned hard mask layer
HM1’、HM2’：Hard mask layer
IMP：Implant direction
L1：Highly
L2：Length
S/D：Source/drain regions
T1、T2:Long recess
2C、5D、7D、9D、11D：Dotted line frame
2A-2A’、2B-2B’、4A-4A’、6A-6A’、8A-8A’、8B-8B’、10A-10A’、10B-10B’:Hatching
Embodiment
Further to illustrate the present invention to reach the technological means and effect that predetermined goal of the invention is taken, below in conjunction with
Accompanying drawing and preferred embodiment, to according to memory storage proposed by the present invention and its manufacture method its embodiment, structure, side
Method, step, feature and its effect, are described in detail as after.
Some embodiments of the present invention will be described in as follows.But, in addition to following description, the present invention can also be extensively
Ground is implemented in other embodiment, and protection scope of the present invention is not limited by embodiment, and it is with the protection of claim
Scope is defined.Furthermore, do not have to provide clearer description and being easier to understand each several part in the present invention, schema according to its phase
Size is drawn, some sizes are exaggerated compared with other scale dependents；Incoherent detail section is not also illustrated completely
Go out, in the hope of the succinct of schema.
Fig. 1 is the top view for illustrating memory storage 100 according to an embodiment of the invention, and Fig. 2A is to illustrate cuing open along Fig. 1
Upper thread I-I profile, Fig. 2 B are to illustrate the profile along Fig. 1 hatching II-II, and Fig. 2 C are to illustrate Fig. 1 dotted line frames a to enclose
The stereogram in region, Fig. 3 is the mnemon C for the memory storage 100 for illustrating Fig. 1 stereogram.
Refer to shown in Fig. 1, Fig. 2A to Fig. 2 C and Fig. 3.Memory storage 100 includes substrate 110, memory material layer 120, the
One grid layer 131, second grid the 133, first dielectric layer 135 of layer and source/drain regions (Source/Drain) S/D.Substrate
110 have groove 150, and memory material layer 120 is formed on the side wall 150s of groove 150.First dielectric layer 135, first grid
Layer 131 and second grid layer 133 are filled in groove 150, wherein the first dielectric layer 135 is formed at first grid layer 131 and the
Between two grid layers 133.Source/drain regions S/D is formed in substrate 110 and is adjacent to memory material layer 120.First grid layer
The direction D2 that the direction D1 of 131 extensions extends perpendicular to source/drain regions S/D.As shown in figure 3, memory material layer 120, first
Grid layer 131, source/drain regions S/D constitute a mnemon C, and the wherein wordline of memory storage 100 extends towards direction D1, position
Line (bit line herein, as bit line, herein referred to as bit line）Towards direction D2 extensions.
As shown in Fig. 2A~Fig. 2 C, in embodiment, source/drain regions S/D top surface 140a and first grid layer 131
Top surface 131a is copline.In other words, as shown in figure 3, partial source/drain regions S/D is configured at first grid layer 131
Sideways, in memory storage 100, programming (program) mnemon C position be first grid layer 131 side wall 131s and
The adjoiner of memory material layer 120.
In embodiment, as shown in Fig. 2A~Fig. 2 C, source/drain regions S/D top surface 140a and memory material layer 120
Top surface 120a is copline.
In embodiment, as shown in Figure 1, memory storage 100 may include multiple memory material layers 120, multiple first grids
Layer 131, multiple second grids layer 133, multiple first dielectric layers 135 and multiple doping bars 140.Multiple memory material layers 120
It is formed on the side wall 150s of each groove 150, the direction D1 of the extension of first grid layer 131 is perpendicular to the doping extension of bar 140
Direction D2.
In embodiment, doping bar 140 includes source/drain regions S/D.Memory storage 100 includes multiple mnemon C
(and/or mnemon C '), except memory material layer 120,131 and source/drain regions S/D of first grid layer may make up a memory
Unit C, memory material layer 120,133 and source/drain regions S/D of second grid layer also may make up a mnemon C '.
In embodiment, the material of substrate 110 is, for example, P-type silicon or N-type silicon, the material and second of first grid layer 131
The material of grid layer 133 is for example including doped silicon (doped silicon).
As shown in Fig. 1 and Fig. 2A~Fig. 2 C, in embodiment, multiple memory material layers 120 are formed at the relative of groove 150
On two side wall 150s.In embodiment, memory material layer 120 can have sandwich construction, and e.g. ONO composite beds or ONONO is answered
Close layer or BE-SONOS composite beds, or the ONO structure including being for example staggeredly stacked to form by silica and silicon nitride.Remember material
The bed of material 120 or homogenous material layer, including silicon nitride or silica such as silica, silicon oxynitride.Memory material layer 120
For catching (trapping) electronics.
In embodiment, doping bar 140 (and source/drain regions S/D) is, for example, heavily doped region (heavily doping
Region), e.g. N-type heavily doped region (N type heavily doping region, N+) or p-type heavily doped region (P
Type heavily doping region, P+), the material of doping bar 140 (and source/drain regions S/D) is for example including arsenic
(As), boron difluoride ion (BF2 +) or phosphorus.
In embodiment, as illustrated in figs. 2 a and 3, first grid layer 131 has a base 131b parallel to groove 150
Bottom 150b, the height L1 of first grid layer 131 is more than base 131b length L2.In one embodiment, first grid layer 131
Height L1 be, for example, 10~120 nanometers (nm), the base 131b of first grid layer 131 length L2 is, for example, between 5 to 40
Nanometer.
As shown in Fig. 1 and Fig. 2A~Fig. 2 C, in embodiment, substrate 110 can more have multiple long recess T2, and respectively adulterate bar
140 are formed within each long recess T2 surface (within).
As shown in Fig. 1 and Fig. 2A~Fig. 2 C, in embodiment, memory storage 100 more may include the second dielectric layer 170, the
Two dielectric layers 170 are formed on doping bar 140.As shown in Figure 2 B, the second dielectric layer 170 is formed in long recess T2, and second is situated between
The top surface 140a of the top surface 170a of electric layer 170 and the bar 140 that adulterates is copline, the top surface 131a of first grid layer 131 and doping
The top surface 140a of bar 140 is copline, and the top surface 133a of second grid layer 133 and the top surface 140a of doping bar 140 are coplines.
In embodiment, as shown in figure 1, memory storage 100 may include multiple second dielectric layers 170.Each second dielectric
Layer 170 is formed on corresponding doping bar 140, the top surface of the top surface 170a of all second dielectric layers 170 and all doping bars 140
140a is copline.
As shown in Fig. 1 and Fig. 2 C, doping bar 140 is to be electrically connected with different mnemon C (or C ').
In one embodiment, first grid layer 131 is, for example, the primary structure of wordline (word line), and adulterate bar 140
The primary structure of bit line (bit line), operating voltage operative memory device 100 is applied via first grid layer 131 in this way.Such as
Shown in Fig. 1, Fig. 2A~Fig. 2 C and Fig. 3, in memory storage 100, programming mnemon C position is in first grid layer 131
Side wall 131s and memory material layer 120 adjoiner, rather than in the base 131b of first grid layer 131, therefore the width of wordline
Degree (word line width) is the height L1 definition with first grid layer 131, rather than with the section of first grid layer 131
Width (namely base 131b length L2).So, sectional width (the base 131b length of the wordline of memory storage 100
L2 it) can accomplish to minimize in the case where technique is allowed, and then reach the reduction of the overall dimensions of memory storage 100, remain to tool
There is relatively large wordline width, and then allow memory storage 100 that still there is good operation in the case where size reduces
Efficiency.
A kind of manufacture method of memory storage of the embodiment of the present invention set forth below, but those steps are by way of example only
It is used, and is not used to limit the present invention.Technical staff with usual knowledge should can be according to actual embodiment the need for
Those steps are modified or changed.It is noted that some elements in top partial view diagram be illustrate in a perspective fashion with
Become apparent from expressing present invention.
Fig. 4 to Figure 11 D is the schematic diagram for the manufacture method for illustrating the memory storage 100 according to one embodiment of the invention.
Refer to shown in Fig. 4 to Figure 11 D.
Wherein, referring to Fig. 4~Fig. 5 D, (Fig. 5 A~Fig. 5 C are to illustrate the section signal along Fig. 4 hatching III-III
Figure, Fig. 5 D are to illustrate the stereogram that dotted line frame b in Fig. 4 encloses region).First, as shown in Figure 5A there is provided substrate 110 ', then
Hard mask layer HM1 ' is deposited on substrate 110 '.In embodiment, hard mask layer HM1 ' material is, for example, silicon nitride (SiN).
Then, as shown in Figure 5 B, for example with etch process patterned hard mask layer HM1 ' to form the patterned hard mask layer of strip
HM1, etches substrate 110 ' to form the substrate 110 with multiple long recess T1, length is recessed then according to patterned hard mask layer HM1
Groove T1 extends towards direction D1.Then, as shown in Fig. 4 and Fig. 5 C~Fig. 5 D, memory material coating layer 120 ' is formed hard in patterning
On mask layer HM1 and in long recess T1.In this step, it is the position for defining wordline to form long recess T1.
Then, refer to Fig. 6~Fig. 7 D (Fig. 7 A~Fig. 7 C are to illustrate the diagrammatic cross-section along Fig. 6 hatching IV-IV,
Fig. 7 D are to illustrate the stereogram that dotted line frame c in Fig. 6 encloses region).As shown in Figure 7 A, conductive material layer 630 is formed in memory material
Expect on coating layer 120 '.It is, for example, that conductive material layer 630 is deposited in memory material coating layer with thin-film technique in embodiment
On 120 ' and in long recess T1.Then, as shown in Figure 7 B, conductive material layer 630 is etched to form a gap (gap) G, gap
G, which separates conductive material layer 630, is split into two parts 631 and 633, and exposure long recess T1 a part of bottom surface.Implement one
In example, as shown in Figure 7 B, the part memory material coating layer 120 ' in clearance G is also etched and removed.In another embodiment,
Also part memory material coating layer 120 ' (not illustrating) that can be in retention gap G.Then, as shown in Fig. 6 and Fig. 7 C~Fig. 7 D, shape
Into dielectric materials layer 635 on conductive material layer 630 (631 and 633) and in clearance G, patterned hard mask layer HM1 is then removed
And planarization dielectric materials layer 635 and conductive material layer 630, it is, for example, that patterning is removed in cmp (CMP) mode
Hard mask layer HM1 and grinding dielectric materials layer 635 and conductive material layer 630.
Wordline sectional width (base 131b length L2) of the thickness of conductive material layer 630 equivalent to memory storage 100.
The easily controllable thickness of conductive material layer 630 is deposited with thin-film technique, it is easy to form very thin thickness, therefore can allow in technique
In the case of minimize wordline sectional width (base 131b length L2), and then reach the big of the overall dimensions of memory storage 100
Width reduces.
Furthermore, conductive material layer 630 is inserted in long recess T1 and 131 He of multiple first grid layers is formed in subsequent technique
Multiple second grid layers 133 are not separated in multiple grooves 150 between multiple first grid layers 131 with etch process, multiple
Second grid layer 133 between not with etch process separate, therefore first grid layer 131 (wordline) between and second grid layer
The conductive material of residual is not had between 133 (wordline), will not occur short circuit because of conductive material that is complete and remaining is not etched.
Consequently, it is possible to have good insulating properties between each wordline, and then improve the reliability of memory storage 100.
Also, tradition defines wordline width with etching mode, when conductive material layer is thicker, complete difficulty is etched significantly
Improve, be more prone to occur not etch the situation that short circuit occurs for complete conductive material because remaining between wordline.In this exposure
In the embodiment of content, wordline width is defined with the height of first grid layer 131 (or second grid layer 133), therefore in manufacture
During, the thickness of conductive material layer is higher, the situation that short circuit will not only occur completely, can increase wordline width on the contrary, enter
And lift the operating characteristics of memory storage.
Then, refer to Fig. 8~Fig. 9 D (Fig. 9 A~Fig. 9 B are to illustrate the diagrammatic cross-section along Fig. 8 hatching VI-VI,
Fig. 9 C are to illustrate the diagrammatic cross-section along Fig. 8 hatching V-V, and Fig. 9 D are to illustrate the solid that dotted line frame d in Fig. 8 encloses region
Figure).As shown in Figure 9 A, hard mask layer HM2 ' is formed on substrate 110, dielectric materials layer 635 and conductive material layer 630.Then,
As shown in Fig. 8 and Fig. 9 B~Fig. 9 D, for example, covered firmly with the patterning for forming strip with etch process patterned hard mask layer HM2 '
Film layer HM2, substrate 110, dielectric materials layer 635 and conductive material layer 630 are etched with shape then according to patterned hard mask layer HM2
Extend into multiple long recess T2, long recess T2 towards direction D2.In this step, it is to define doping bar to form long recess T2
The position of 140 (bit lines), the direction D2 that the direction D1 that long recess T1 extends extends perpendicular to long recess T2.
After etch process formation long recess T2, in this step, groove 150, the memory material of substrate 110 are also formed
Layer 120 is filled in side wall 150s and the first grid layer 131, second grid layer 133 and the first dielectric layer 135 of groove 150
In groove 150.
Then, referring to Figure 10~Figure 11 D, (Figure 11 A~Figure 11 B are to illustrate cuing open along Figure 10 hatching VIII-VIII
Face schematic diagram, Figure 11 C are to illustrate the diagrammatic cross-section along Figure 10 hatching VII-VII, and Figure 11 D are to illustrate dotted line frame in Figure 10
E encloses the stereogram in region).As shown in Figure 11 A, an ion implant (ion implantation) technique is carried out to substrate 110
To form doping bar 140 (and source/drain regions S/D) in substrate 110.It is recessed to length with implant direction IMP in embodiment
The surface of substrate 110 in groove T2 carries out ion implant, and doping bar 140 is formed within z long recess T2 surface.In embodiment
In, doping bar 140 (and source/drain regions S/D) is the heavily doped region and shape formed by ion implanting processes in the substrate 110
Into.
Then, as shown in Figure 10 and Figure 11 B~Figure 11 D, dielectric materials layer is formed on patterned hard mask layer HM2 and long
In groove T2, the dielectric materials layer in patterned hard mask layer HM2 and planarization long recess T2 is then removed, to form second Jie
Electric layer 170 is on the doping bar 140 in long recess T2.It is, for example, with cmp mode abrasive pattern in embodiment
Change the dielectric materials layer in hard mask layer HM2 and long recess T2.After this grinding steps, the top surface 140a of doping articles 140, the
The top surface 170a of the top surface 131a of one grid layer 131 and the second dielectric layer 170 is copline.So far, formed as shown in Figure 1, Figure 2 A~
What the direction D1 of the extension of the memory storage 100 shown in Fig. 2 D and Fig. 3, wherein first grid layer 131 extended perpendicular to doping bar 140
Direction D2, memory material layer 120,131 and source/drain regions S/D of first grid layer constitute a mnemon C.
Figure 12 is the circuit diagram for illustrating the memory storage 100 according to Fig. 1 embodiment.Wordline extends towards direction D1, bit line
(doping bar 140) extends towards direction D2.
Figure 13 is wordline width (word line the width)-transconductance value for illustrating memory storage
(transconductance, Gm) curve map.Transconductance value (Gm) is proportional to (W/L) * CEOT* μ, wherein W represent that grid (wordline) is wide
Degree, L represents grid length, CEOTRepresent electric capacity (the Capacitance of of the equivalent oxide thickness of memory material layer
Equivalent oxide thickness), μ represents that (hole herein, is electric hole to electrons, referred to as empty herein
Cave）Mobility (mobility).When transconductance value is bigger, voltage's distribiuting (Vt distribution) narrower, voltage distribution curves
Spacing (product open window) between middle adjacent peaks is bigger, and can reduce memory storage failure (fail)
Chance, and then the efficiency of memory storage can be lifted.
As shown in figure 13, wordline width substantially has linear proportional relation with transconductance value.However, according to traditional memory
Apparatus structure, in order to reach the size reduction of memory storage, wordline width can also reduce.When wordline width is opened less than 40 nanometers
Begin, transconductance value declines more violent, and this can cause the efficiency of memory storage acutely to deteriorate.Relatively, in this disclosure
In embodiment, via reduction wordline sectional width (the base 131b of first grid layer 131 length L2), and then memory dress is reached
Put the significantly reduction of 100 overall dimensions, and not influence wordline width (the height L1 of first grid layer 131), therefore memory
Device 100 is remained to relatively large wordline width, thus with relatively large transconductance value, and then make it that memory storage 100 can
Still there is good operation efficiency in the case of to reduce in size.
The above described is only a preferred embodiment of the present invention, any formal limitation not is made to the present invention, though
So the present invention is disclosed above with preferred embodiment, but is not limited to the present invention, any to be familiar with this professional technology people
Member, without departing from the scope of the present invention, when method and technology contents using the disclosure above make it is a little more
Equivalent embodiment that is dynamic or being modified to equivalent variations, as long as being the content without departing from technical solution of the present invention, according to the present invention's
Any simple modification, equivalent variations and modification that technical spirit is made to above example, still fall within technical solution of the present invention
In the range of.
Claims (10)
1. a kind of memory storage, it is characterised in that it includes：
One substrate, with a groove；
One memory material layer, is formed on the side wall of the groove；
One first dielectric layer, first grid layer and second grid layer, are filled in the groove, wherein first dielectric layer is
It is formed between first grid layer and second grid layer；And
One doping bar, is formed in the substrate and is adjacent to memory material layer；
The direction that the direction of wherein first grid layer extension extends perpendicular to the doping bar, the width of the wordline of the memory storage
With the height definition of first grid layer, the height of the first grid layer is defined as perpendicular to first grid layer extension
The direction that direction and the doping bar extend.
2. memory storage according to claim 1, it is characterised in that wherein the doping bar includes multiple source/drain pole region.
3. memory storage according to claim 1, it is characterised in that wherein the substrate has more an at least long recess, and this is mixed
Miscellaneous bar is formed within the surface of the long recess.
4. memory storage according to claim 3, it is characterised in that it also includes：
One second dielectric layer, second dielectric layer is formed in the long recess.
5. a kind of manufacture method of memory storage, it is characterised in that it comprises the following steps：
A substrate is provided, wherein the substrate has a groove；
Memory material layer is formed on the side wall of the groove；
Form one first dielectric layer, first grid layer and second grid layer to be filled in the groove, wherein first dielectric
Layer is formed between first grid layer and second grid layer；And
Formed source/drain region in the substrate and be adjacent to the memory material layer；
The direction that the direction of wherein first grid layer extension extends perpendicular to the source/drain regions, the wordline of the memory storage
Width defined with the height of first grid layer, the height of first grid layer is defined as perpendicular to first grid layer
The direction that the direction of extension and the source/drain regions extend.
6. the manufacture method of memory storage according to claim 5, it is characterised in that wherein formed first dielectric layer,
The step of first grid layer and second grid layer, includes：
Form a conductive material layer；
The conductive material layer is etched to form a gap, the gap, which separates the conductive material layer, is split into two parts；
A dielectric materials layer is formed on the conductive material layer and in the gap；And
The dielectric materials layer and the conductive material layer is ground to form first dielectric layer, first grid layer and the second grid
Layer.
7. the manufacture method of memory storage according to claim 5, it is characterised in that wherein form the source/drain regions
Include in the step in the substrate：
The substrate is carried out an ion implanting processes to form the source/drain regions in the substrate.
8. the manufacture method of memory storage according to claim 5, it is characterised in that it also includes forming one second dielectric
Layer is on the source/drain regions.
9. a kind of manufacture method of memory storage, it is characterised in that it comprises the following steps：
A substrate is provided, wherein the substrate has multiple grooves；
Multiple memory material layers are formed respectively on the side wall of the respectively groove；
Multiple first dielectric layers, multiple first grids layer and multiple second grids layer are formed, wherein respectively first dielectric layer is shape
Into in the respectively first grid layer and respectively the second grid layer between and be filled in the respectively groove；And
Formed it is multiple doping bars in the substrate and be adjacent to those memory materials layer；
Wherein the direction of those first grids layer extension is perpendicular to the direction of those doping bar extensions.
10. the manufacture method of memory storage according to claim 9, it is characterised in that wherein formed those doping bars in
Step in the substrate includes：
An ion implanting processes are carried out to the substrate to form those doping bars in the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310150886.3A CN104124246B (en) | 2013-04-26 | 2013-04-26 | Memory storage and its manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310150886.3A CN104124246B (en) | 2013-04-26 | 2013-04-26 | Memory storage and its manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104124246A CN104124246A (en) | 2014-10-29 |
| CN104124246B true CN104124246B (en) | 2017-09-08 |
Family
ID=51769604
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310150886.3A Active CN104124246B (en) | 2013-04-26 | 2013-04-26 | Memory storage and its manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104124246B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5973352A (en) * | 1997-08-20 | 1999-10-26 | Micron Technology, Inc. | Ultra high density flash memory having vertically stacked devices |
| US6438024B1 (en) * | 2001-01-11 | 2002-08-20 | Sun Microsystems, Inc. | Combining RAM and ROM into a single memory array |
| CN1971964A (en) * | 2005-11-21 | 2007-05-30 | 旺宏电子股份有限公司 | Vacuum cell thermal isolation for a phase change memory device |
| CN103050445A (en) * | 2011-10-13 | 2013-04-17 | 旺宏电子股份有限公司 | Memory body and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7510929B2 (en) * | 2006-10-18 | 2009-03-31 | Macronix International Co., Ltd. | Method for making memory cell device |
-
2013
- 2013-04-26 CN CN201310150886.3A patent/CN104124246B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5973352A (en) * | 1997-08-20 | 1999-10-26 | Micron Technology, Inc. | Ultra high density flash memory having vertically stacked devices |
| US6438024B1 (en) * | 2001-01-11 | 2002-08-20 | Sun Microsystems, Inc. | Combining RAM and ROM into a single memory array |
| CN1971964A (en) * | 2005-11-21 | 2007-05-30 | 旺宏电子股份有限公司 | Vacuum cell thermal isolation for a phase change memory device |
| CN103050445A (en) * | 2011-10-13 | 2013-04-17 | 旺宏电子股份有限公司 | Memory body and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104124246A (en) | 2014-10-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10460788B2 (en) | Memory cell and methods thereof | |
| DE102016114573B4 (en) | Three-dimensional semiconductor devices with a cavity between a channel structure and a residue layer | |
| US6534811B2 (en) | DRAM cell with high integration density | |
| EP1550154B1 (en) | Field effect transistor with local source/drain insulation and associated method of production | |
| DE102005021118B4 (en) | Non-volatile semiconductor memories and methods for producing such memories | |
| EP3701562A1 (en) | Memory cell and methods thereof | |
| DE102015213529A1 (en) | Device with a floating gate electrode and a layer of ferroelectric material and method for their preparation | |
| EP3891804B1 (en) | Split gate non-volatile memory cells with finfet structure and hkmg memory and logic gates, and method of making same | |
| CN103811320B (en) | Semiconductor devices and its manufacture method | |
| DE102018110017B4 (en) | SEMICONDUCTOR MEMORY DEVICE AND PRODUCTION METHOD THEREOF | |
| US10312246B2 (en) | Split-gate flash memory cell with improved scaling using enhanced lateral control gate to floating gate coupling | |
| US20230052477A1 (en) | Semiconductor device | |
| CN107017299A (en) | Semiconductor device and its manufacture method | |
| TW202209645A (en) | Memory device and method for forming the same | |
| US20190371799A1 (en) | Memory cell, semiconductor integrated circuit device, and method for manufacturing semiconductor integrated circuit device | |
| DE102011004757B4 (en) | Vertical memory transistors having a self-adjusting body potential fabricated in bulk substrate devices and having buried interrogation and word lines and methods of fabricating the memory transistors | |
| US20060186558A1 (en) | Methods of fabricating scalable two transistor memory devices | |
| EP0987753A2 (en) | Stacked DRAM fin capacitor and method of making the same | |
| US9299856B2 (en) | Selective gate oxide properties adjustment using fluorine | |
| CN112018184A (en) | Device with ferroelectric or negative capacitance material, method of manufacturing the same, and electronic apparatus | |
| US6737314B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
| US20100237406A1 (en) | Semiconductor memory device and manufacturing method thereof | |
| CN104124246B (en) | Memory storage and its manufacture method | |
| US9559297B2 (en) | Vertical transistor for resistive memory | |
| KR100213189B1 (en) | Semiconductor memory device and its fabrication method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |