CN104124233A - Monitoring structure and method for N-type lightly-doped ion implantation registration - Google Patents
Monitoring structure and method for N-type lightly-doped ion implantation registration Download PDFInfo
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- 238000005468 ion implantation Methods 0.000 title claims abstract description 125
- 238000012544 monitoring process Methods 0.000 title claims abstract description 111
- 238000000034 method Methods 0.000 title claims abstract description 56
- 238000005040 ion trap Methods 0.000 claims abstract description 59
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 98
- 238000010894 electron beam technology Methods 0.000 claims description 40
- 239000000758 substrate Substances 0.000 claims description 19
- 230000007547 defect Effects 0.000 claims description 16
- 238000002360 preparation method Methods 0.000 claims description 7
- 230000002159 abnormal effect Effects 0.000 claims description 5
- 238000012360 testing method Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 abstract description 57
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 4
- 150000004706 metal oxides Chemical class 0.000 abstract description 4
- 230000000295 complement effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 8
- 238000002513 implantation Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 101100204059 Caenorhabditis elegans trap-2 gene Proteins 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012067 mathematical method Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Abstract
The invention provides a monitoring structure and method for an N-type lightly-doped ion implantation registration. The monitoring structure comprises a photoresistance region and an N-type lightly-doped ion implantation region, the N-type lightly-doped ion implantation region is composed of an N-type trap-N-type lightly-doped ion trap structure which comprises N-type traps, N-type lightly-doped ion traps, gates, dielectric layers and contact holes corresponding to the N-type lightly-doped ion traps; the photoresistance region comprises an N-type trap-P-type lightly-doped ion trap structure which comprises N-type traps, P-type lightly-doped ion traps, gates, dielectric layers and contact holes corresponding to the P-type lightly-doped ion traps; negative potential electro beam scanning is utilized, brightness display differences of the contact holes corresponding to homojunctions and heterojunctions are utilized, the former displays dark holes, the latter display bright holes, the registration of the photoresistance region can be monitored according to the contact holes with brightness changes, accordingly real-time monitoring of the N-type lightly-doped ion implantation registration in the CMOS (complementary metal oxide semiconductor) can be achieved, the N-type lightly-doped ions can be prevented from being implanted into a PMOS (Positive Metal Oxide Semiconductor), and therefore electric leakage can be avoided.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a monitoring structure and a monitoring method for monitoring the alignment degree of N-type lightly doped ion implantation in a CMOS (complementary metal oxide semiconductor).
Background
With the development of the integrated circuit process and the scaling-down of the critical dimension, the process windows of various processes are smaller and smaller, the CMOS device becomes one of the important electronic elements in the existing integrated circuit, and in the preparation process of the CMOS device, the requirements on various process procedures are higher and higher, such as the alignment degree of the ion implantation of the source and drain electrodes, the alignment degree of the ion implantation of the light doping ion, and the like; as shown in fig. 1, a schematic diagram of a leakage defect of a PMOS obtained by scanning an electron beam is shown, and it is found through research that one of the reasons for forming the leakage defect of the PMOS is that alignment deviation is generated during implantation of N-type lightly doped ions, so that N-type lightly doped ions are implanted into a lightly doped region in the PMOS, and as shown in fig. 1, a position in a dashed line frame, which should be a dark hole, is shown as a bright hole, which indicates that N-type lightly doped ions are implanted into the PMOS, that is, alignment deviation is generated by implantation of N-type lightly doped ions. The PMOS leakage defect will cause the whole CMOS device and even yield failure, thereby increasing the cost. Therefore, it is necessary to monitor the alignment of the N-type lightly doped ion implantation. The reason why the misalignment generated by the N-type lightly doped ion implantation is completely attributed to the misalignment of the photoresist covering the PMOS region when the N-type lightly doped ion implantation is performed. Therefore, monitoring the alignment deviation of the N-type lightly doped ion implantation can be realized by monitoring the photoresist alignment deviation in the process of the N-type lightly doped ion implantation.
As shown in fig. 2, the various conditions of the misalignment of the photoresist generated during the implantation of the N-type lightly doped ions are schematically illustrated, wherein the dotted line represents the abnormal position, and the solid line represents the normal position, and it can be seen that the conditions of the misalignment of the photoresist include: unidirectional offset (fig. 2(a)), overflow (fig. 2(b)), adduction (fig. 2(c)), rotation (fig. 2(d)), and comprehensiveness (fig. 2 (e)). At present, optical detection is adopted in the industry for monitoring, but due to the limitation of resolution and the complexity of alignment deviation in the actual photoresist process, accurate monitoring is difficult to obtain, and more importantly, the detection result cannot be directly related to the electric leakage problem.
Therefore, a test structure and a method capable of accurately monitoring the implantation alignment of N-type lightly doped ions in a CMOS in real time are urgently needed, so as to avoid the problem that the PMOS device generates leakage to cause the failure of the whole device.
Disclosure of Invention
In order to overcome the above problems, the present invention provides a monitoring structure and a monitoring method for the alignment degree of N-type lightly doped ion implantation in CMOS, which monitor the alignment degree of N-type lightly doped ion implantation by using the alignment degree of a photoresist used in the N-type lightly doped ion implantation, thereby implementing accurate and effective real-time monitoring of the alignment degree of N-type lightly doped ion implantation and avoiding the occurrence of electric leakage caused by the injection of N-type lightly doped ions in PMOS devices.
The invention provides a monitoring structure of N-type lightly doped ion implantation alignment, which is positioned in a non-functional area of a semiconductor substrate, wherein the monitoring structure comprises an N-type lightly doped ion implantation area and a light resistance area, and the light resistance area is an area for performing P-type lightly doped ion implantation; wherein,
the N-type lightly doped ion implantation region is formed by an N-type trap-N-type lightly doped ion trap structure and comprises: the ion source comprises an N-type trap arranged in a non-functional area, N-type lightly doped ion wells arranged in the N-type trap, a grid electrode positioned between the N-type lightly doped ion wells, a dielectric layer positioned on the surface of the non-functional area, and contact holes positioned in the dielectric layer and corresponding to the N-type lightly doped ion wells;
the photoresistance region is formed by an N-type trap-P type lightly doped ion trap structure and comprises: the ion trap structure comprises an N-type trap arranged in a non-functional region, a P-type lightly doped ion trap arranged in the N-type trap, a grid electrode positioned between the P-type lightly doped ion traps, a dielectric layer positioned on the surface of the non-functional region and a contact hole positioned in the dielectric layer and corresponding to the P-type lightly doped ion trap;
in a voltage contrast image obtained in a negative potential electron beam scanning mode, the contact hole corresponding to the N-type trap-N type lightly doped ion trap structure is a dark hole, and the contact hole corresponding to the N-type trap-P type lightly doped ion trap structure is a bright hole.
Preferably, the photoresist region is arranged around the N-type lightly doped ion implantation region; the shape of the light resistance area is a regular polygon with a hollow-out inner part, and the figure of the outline of the hollow-out area of the light resistance area is the figure of the N-type lightly doped ion implantation area.
Preferably, the outline of the photoresist region and the outline of the hollow region have the same shape and have the same geometric center; the pattern of the light resistance area comprises the outer contour and a pattern obtained by rotating the hollow area along the geometric center.
Preferably, the N-type wells in the monitoring structure are arranged in a plurality of parallel rows at equal intervals, and the gates are arranged in a plurality of parallel rows at equal intervals; the rows where the grid electrodes are located and the columns where the N-type wells are located are distributed in an orthogonal mode;
in the photoresistance region, a P-type lightly doped ion well is arranged in an N-type trap between the grids; and in the N-type lightly doped ion implantation region, an N-type lightly doped ion well is arranged in an N-type trap between the grids.
The invention also provides a method for monitoring the alignment degree of N-type lightly doped ion implantation, which comprises two processes of preparing a monitoring structure and scanning an electron beam, wherein,
the preparation of the monitoring structure comprises the following steps:
step S01: providing a non-functional area of a semiconductor substrate, and arranging an N-type lightly doped ion implantation area and a light resistance area in the non-functional area;
step S02: sequentially preparing an N-type well and a grid electrode in the non-functional region;
step S03: covering a layer of N-type lightly doped ion implantation photoresist on the photoresist area;
step S04: performing N-type lightly doped ion implantation in an N-type well of the N-type lightly doped ion implantation region, thereby forming an N-type lightly doped ion well in the N-type well;
step S05: removing the N-type lightly doped ion implantation photoresist;
step S06: shielding the region outside the light resistance region by adopting a photoetching process, and carrying out P-type lightly doped ion implantation in an N-type well in the light resistance region so as to form a P-type lightly doped ion well in the N-type well;
step S07: forming a dielectric layer on the surface of the non-functional area, and forming contact holes in the dielectric layer and above the N-type lightly doped ion well and the P-type lightly doped ion well respectively;
the electron beam scanning process includes:
step S08: scanning the monitoring structure by adopting an electron beam in a negative potential scanning mode to obtain an actual voltage contrast image of the test structure; the contact hole corresponding to the N-type trap-N type lightly doped ion trap structure is displayed as a dark hole, and the contact hole corresponding to the N-type trap-P type lightly doped ion trap structure is displayed as a bright hole;
step S09: setting a standard voltage contrast image map of the monitoring structure under the condition of no alignment deviation; the contact hole corresponding to the N-type trap-N type lightly doped ion trap structure is displayed as a dark hole, and the contact hole corresponding to the N-type trap-P type lightly doped ion trap structure is displayed as a bright hole;
step S10: comparing the actual voltage contrast image with the standard voltage contrast image, and finding out the contact holes with brightness change: the ion trap structure comprises a contact hole which is formed in the N-type trap-N type lightly doped ion trap structure and is changed from a dark hole into a bright hole or is formed in the N-type trap-P type lightly doped ion trap structure and is changed from a bright hole into a dark hole;
step S11: and obtaining the alignment deviation of the light resistance region according to the data of the contact hole with the brightness change, namely the alignment deviation of the N-type lightly doped ion implantation.
Preferably, the step S09 specifically includes: and setting a defect scanning program in an electron beam scanner, assuming that at least one group of contact holes in the photoresist region and the N-type lightly doped ion implantation region is abnormal, and simulating a standard voltage contrast image of the monitoring structure by combining the type of the monitoring structure.
Preferably, in step S11, the data of the contact hole with the brightness change includes position data and number data.
Preferably, the photoresist region is arranged around the N-type lightly doped ion implantation region; the shape of the light resistance area is a regular polygon with a hollow inner part, and the graph of the hollow area is the graph of the N-type lightly doped ion implantation area.
The invention relates to a monitoring structure and a method for N-type lightly doped ion implantation alignment degree in a CMOS (complementary metal oxide semiconductor), which utilize the principle that a special NP junction is conducted and a same NN junction is not conducted in a negative potential electron beam scanning mode, wherein an N-type lightly doped ion implantation area formed by an N-type trap-N-type lightly doped ion trap structure and a light resistance area formed by the N-type trap-P-type lightly doped ion trap structure are arranged in the monitoring structure; and then obtaining the alignment deviation of the photoresist region according to the data, such as position data, quantity and the like, of the contact holes with brightness change, namely obtaining the alignment deviation of the N-type lightly doped ion implantation, thereby realizing the real-time monitoring of the alignment of the N-type lightly doped ion implantation in the CMOS and avoiding the unnecessary waste of the failure and cost of the PMOS device.
Drawings
FIG. 1 is a schematic diagram of leakage defect of PMOS obtained by electron beam scanning
FIG. 2 is a schematic diagram of various alignment deviations of photo-resist generated during N-type lightly doped ion implantation
FIG. 3 is a top view of a monitoring structure for the alignment of N-type lightly doped ion implantation in CMOS according to a preferred embodiment of the present invention
FIG. 4 is a partial cross-sectional view of a monitoring structure for the alignment of N-type lightly doped ion implantation in CMOS according to a preferred embodiment of the present invention
FIG. 5 is a flow chart of a method for monitoring the alignment of N-type lightly doped ion implantation in CMOS
FIGS. 6-12 are schematic top-view structural diagrams corresponding to various steps of manufacturing a monitoring structure according to a preferred embodiment of the present invention
FIG. 13 is a schematic voltage contrast image of the cross-sectional structure of the monitoring structure having N-type lightly doped ion implantation region and photoresist region under negative potential scan mode and the contact hole thereof according to a preferred embodiment of the present invention
FIG. 14 is a standard voltage contrast image of a monitoring structure according to a preferred embodiment of the present invention
FIG. 15 is a schematic diagram showing the comparison between the actual voltage contrast image and the standard voltage contrast image of the monitoring structure formed after performing the electron beam scanning according to the preferred embodiment of the present invention
Detailed Description
In order to make the contents of the present invention more comprehensible, the present invention is further described below with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.
The principle of the monitoring structure and the monitoring method of the invention is as follows: according to the electron beam scanning process, the N-type well-N type lightly doped ion well structure with the same type structure and the N-type well-P type lightly doped ion well structure with the different type structure have different absorption degrees for secondary electrons in an electron beam, so that the obtained contact holes corresponding to the two structures are judged to have different colors, under the condition of negative potential, the contact hole corresponding to the former is displayed as a dark hole, and the contact hole corresponding to the latter is displayed as a bright hole; when the position of the photoresist in the N-type lightly doped ion implantation process has alignment deviation, the photoresist area in the monitoring structure also changes, the contact hole which should be displayed as a bright hole (or a dark hole) originally is displayed as a dark hole (or a bright hole), and the alignment deviation of the photoresist area obtained according to the position of the contact hole which changes is also the alignment deviation of the N-type lightly doped ion implantation.
The reason why the N-type trap-P type lightly doped ion trap structure shows a bright hole is that: under the condition of negative potential, the structure is conducted, most of secondary electrons incident in an electron beam are absorbed by the structure, and flow from the P-type lightly doped ion trap to the N-type well, so that the contact hole corresponding to the structure is displayed as a bright hole; similarly, the N-type well-N lightly doped ion well structure appears as a dark hole due to: under the condition of negative potential, the structure is not conducted, most of secondary electrons incident in an electron beam are blocked on the surface of the structure, and therefore the contact hole corresponding to the structure is displayed as a dark hole.
The structure for monitoring the alignment of the N-type lightly doped ion implantation in CMOS will be described in further detail with reference to fig. 3-4 and the specific embodiments. It should be noted that the drawings are in a simplified form and are not to precise scale, and are only used for conveniently and clearly achieving the purpose of assisting in describing the embodiment.
The monitoring structure is arranged on a semiconductor substrate, the semiconductor substrate adopted by the invention is provided with a functional area and a non-functional area, and the non-functional area refers to an area which does not influence the function of the semiconductor substrate, such as a cutting path, a virtual area and the like. The semiconductor substrate may be, but is not limited to, a silicon substrate; the monitoring structure is positioned in a non-functional area of the semiconductor substrate and comprises an N-type lightly doped ion implantation area and a light resistance area, wherein the light resistance area is an area for carrying out P-type lightly doped ion implantation.
The reason for this is that one of the reasons for the PMOS leakage phenomenon is that the masking adopted during the N-type lightly doped ion implantation does not require the occurrence of misalignment of the photoresist in the N-type lightly doped ion implantation region, thereby causing the N-type lightly doped ions to be implanted into the N-type well of the PMOS; therefore, the monitoring of the alignment degree of the N-type lightly doped ion implantation can be realized by monitoring the alignment degree of the photoresist, and the alignment degree of the photoresist can be monitored by utilizing the alignment degree of a photoresist area in the monitoring structure. Therefore, an N-type lightly doped ion implantation area and a light resistance area are arranged in the monitoring structure, the N-type lightly doped ion implantation area is an area for implanting N-type lightly doped ions, the light resistance area is an area for implanting P-type lightly doped ions, in the process of implanting the N-type lightly doped ions, the light resistance area is provided with light resistance for preventing the N-type lightly doped ions from being implanted into the light resistance area, if the light resistance area has alignment deviation, the N-type lightly doped ion implantation has alignment deviation, and therefore the alignment deviation of the N-type lightly doped ion implantation can be found by monitoring the alignment deviation of the light resistance area.
The N-type lightly doped ion implantation region is formed by an N-type trap-N-type lightly doped ion trap structure and comprises: the ion trap structure comprises an N-type trap arranged in a non-functional area, an N-type lightly doped ion trap arranged in the N-type trap, a grid electrode positioned between the N-type lightly doped ion traps, a dielectric layer positioned on the surface of the non-functional area, and a contact hole positioned in the dielectric layer and corresponding to the N-type lightly doped ion trap.
The photoresistance region is formed by N type trap-P type lightly doped ion well structure, includes: the ion trap structure comprises an N-type trap arranged in a non-functional region, a P-type lightly doped ion trap arranged in the N-type trap, a grid electrode positioned between the P-type lightly doped ion traps, a dielectric layer positioned on the surface of the non-functional region, and a contact hole positioned in the dielectric layer and corresponding to the P-type lightly doped ion trap; it should be noted that the photoresist region should not be shielded above the N-type wells of the N-type lightly doped ion implantation region, and therefore, the outline of the photoresist region may be located above the gate or above the region between the N-type wells.
In a voltage contrast image obtained in a negative potential electron beam scanning mode, the contact hole corresponding to the N-type trap-N type lightly doped ion trap structure is a dark hole, and the contact hole corresponding to the N-type trap-P type lightly doped ion trap structure is a bright hole.
In the present invention, a contact hole may be formed in the dielectric layer above the gate in the photoresist region or the N-type lightly doped ion implantation region.
FIG. 3 is a schematic top view of a monitoring structure for the alignment of N-type lightly doped ion implantation in CMOS according to a preferred embodiment of the present invention; in the embodiment, the monitoring structure is located in a non-functional region 1 of a semiconductor substrate, the N-type wells 2 are arranged in a plurality of parallel rows and a plurality of parallel columns at equal intervals, and the gates 3 are arranged in a plurality of parallel rows at equal intervals and are orthogonally arranged with the N-type wells 2; the area formed by the two dotted line frames is a light resistance area a, the area in the internal dotted line frame is an N-type lightly doped ion implantation area b, the light resistance area a is arranged around the N-type lightly doped ion implantation area b in a surrounding manner, the light resistance area is in the shape of a regular polygon with a hollow interior, the outer contour of the light resistance area a is the same as the inner contour of the hollow interior area, and has the same geometric center, for example, the graph of the light resistance area comprises an outer contour and a graph obtained by rotating the hollow interior area along the geometric center by a certain angle, such as 90 degrees and the like; the pattern of the photoresist region is designed in such a way that the photoresist region with the inner and outer profiles is more sensitive to the offset or rotation of the photoresist, which facilitates finding and calculating more accurate alignment. The figure of the outline of the hollow-out area is also the figure of the N-type lightly doped ion implantation area b, can be a regular polygon, and can be but not limited to rhombus, regular hexagon, regular triangle, square and the like; since the regular polygons have the same side length and known inner angles, which is convenient for the subsequent calculation of the alignment deviation, the regular polygons are preferably used as the outer contour pattern of the photoresist region a and the pattern of the inner hollow region thereof in the embodiment. A P-type lightly doped ion well 6 is arranged in the N-type well 2 between the gates 3; in the N-type lightly doped ion implantation region b, an N-type lightly doped ion well 5 is arranged in the N-type trap 2 between the grid electrodes 3; contact holes 8 are arranged between the grid electrodes 3 and above the P-type lightly doped ion well 6 and the N-type lightly doped ion well 5 respectively; note that, for convenience of expression, the dielectric layer is not shown in fig. 3.
The photoresist region a in the invention can also have the following characteristics: each contour line of the photoresist area a can find a straight line parallel to the contour line in the straight lines formed by two adjacent contact holes. Therefore, when the light resistance area a deviates, the brightness change of each contact hole on a straight line formed by the contact holes parallel to the contour lines of the light resistance area a is ensured to be consistent, so that the deviation direction of the light resistance area a can be effectively judged; or, when the photoresist area a rotates, the data such as the rotation angle can be effectively judged according to the brightness change of the contact hole on the straight line parallel to the contour line of the photoresist area a. That is, the profile parallel to the line of the contact hole is very sensitive to the deviation or rotation of the photoresist region a, so that the alignment condition of the photoresist region can be effectively detected. It should be noted that, no matter how the outline of the photoresist region a is set, it cannot be shielded above the N-type well in the N-type lightly doped ion implantation region, which requires the outline of the photoresist region a to be above the region between the N-type wells or above the gate.
To facilitate the clear and complete expression of the monitoring structure of the present invention, please refer to fig. 4, which shows a schematic cross-sectional structure diagram of the monitoring structure including the N-type lightly doped ion implantation region and the photoresist region according to a preferred embodiment of the present invention; wherein, the inside of the dotted line frame is a photoresistance area; the N-type lightly doped ion implantation region is formed by an N-type trap-N-type lightly doped ion trap structure and comprises: the ion implantation device comprises an N-type well 2 arranged in a non-functional region 1, an N-type lightly doped ion well 5 arranged in the N-type well 2, a grid electrode (not shown) located between the N-type lightly doped ion wells 5, a dielectric layer 9 located on the surface of the non-functional region 1, and a contact hole 8 located in the dielectric layer 9 and corresponding to the N-type lightly doped ion well 5. The photoresistance region is formed by N type trap-P type lightly doped ion well structure, includes: the ion trap structure comprises an N-type well 2 arranged in a non-functional region 1, a P-type lightly doped ion well 6 arranged in the N-type well 2, a grid electrode (not shown) located between the P-type lightly doped ion wells 6, a dielectric layer 9 located on the surface of the non-functional region 1, and a contact hole 8 located in the dielectric layer 9 and corresponding to the P-type lightly doped ion well 6.
The method for monitoring the alignment of the N-type lightly doped ion implantation in the CMOS will be described in further detail with reference to fig. 5-15 and the specific embodiments. It should be noted that the drawings are in a simplified form and are not to precise scale, and are only used for conveniently and clearly achieving the purpose of assisting in describing the embodiment.
Please refer to fig. 5, which is a flow chart of the method for monitoring alignment of N-type lightly doped ion implantation in CMOS according to the present invention; the method for monitoring the alignment degree of the N-type lightly doped ion implantation in the CMOS comprises two processes of preparation of a monitoring structure and electron beam scanning:
first, please refer to fig. 6-12, which are schematic top view structure diagrams corresponding to each manufacturing step of the monitoring structure according to a preferred embodiment of the present invention; the monitoring structure of the present embodiment adopts the monitoring structure shown in fig. 3 and 4, and a method for preparing and scanning the monitoring structure shown in fig. 3 and 4 by using an electron beam is described as an example; the preparation of the monitoring structure of the present embodiment includes:
step S01: referring to fig. 6, a non-functional region 1 of a semiconductor substrate is provided, and an N-type lightly doped ion implantation region b and a photoresist region a are disposed in the non-functional region 1;
specifically, in the invention, the semiconductor substrate comprises a functional area for preparing a CMOS device and a non-functional area for preparing a monitoring structure; the semiconductor substrate may be any semiconductor substrate, and in this embodiment, the semiconductor substrate is a silicon substrate; for convenience of description, in fig. 6-12, only the monitoring structure of the non-functional region 1 is shown, and the structure and fabrication of the CMOS device in the functional region are prior art and will not be described herein again. The photoresist region a is a region for performing P-type lightly doped ion implantation, such as a region formed by two dashed frames in fig. 6; the N-type lightly doped ion implantation area b is an area in an inner broken line frame. In this embodiment, the photoresist region is disposed around the N-type lightly doped ion implantation region; the photoresist region a may be a regular polygon with a hollowed-out interior, for example, a hollow center, the pattern of the hollowed-out region is the pattern of the N-type lightly doped ion implantation region b, and the outer contour of the photoresist region a and the inner contour of the hollowed-out region have the same shape and have the same geometric center, and the pattern of the N-type lightly doped ion implantation region b may be, but not limited to, a rhombus, a regular hexagon, a square, a rectangle, or the like. The monitoring structure in the method adopts the structure shown in fig. 3 in the above embodiment, and the structure thereof is not described again.
Step S02: referring to fig. 7, the preparation of the N-well 2 and the gate 3 is sequentially performed in the non-functional region 1;
specifically, in this embodiment, the N-type well 2 and the gate 3 may be sequentially prepared in the non-functional region 1 by using the existing method, which is not described again in the present invention; it should be noted that, in order to implement real-time monitoring of the N-type lightly doped ion implantation in the CMOS fabrication process, in the process of fabricating the monitoring structure of the present invention, the CMOS device is also fabricated in the functional region, so that once the misalignment of the photoresist region is found in the monitoring structure, the misalignment of the N-type lightly doped ion implantation of the NMOS device can be known, and thus the fabrication can be stopped, and corresponding corrections can be made to eliminate the misalignment of the N-type lightly doped ion implantation. The N-type trap 2 is arranged into a plurality of parallel rows which are arranged at equal intervals, and the grid 3 is arranged into a plurality of parallel rows which are arranged at equal intervals and are orthogonally arranged with the N-type trap 2.
Step S03: referring to fig. 8, an N-type lightly doped ion implantation photoresist 4 is covered on the photoresist region;
specifically, in this embodiment, since the N-type lightly doped ion implantation process is performed on the non-functional region 1 of the entire silicon substrate, the P-type lightly doped ion implantation region needs to be shielded by using the photoresist; in the preparation process of the monitoring structure, the photoresist adopted in the process of injecting the N-type lightly doped ions is called as N-type lightly doped ion injection photoresist 4, and the region corresponding to the N-type lightly doped ion injection photoresist 4 is a photoresist region; that is, the photoresist region is the region where the P-type lightly doped ion implantation is required, and the pattern of the N-type lightly doped ion implantation photoresist 4 is the same as the pattern of the photoresist region.
Step S04: referring to fig. 9, N-type lightly doped ion implantation is performed into the N-type well 2 in the N-type lightly doped ion implantation region, so as to form an N-type lightly doped ion well 5 in the N-type well;
specifically, in this embodiment, under the protection of the N-type lightly doped ion implanted photoresist 4, N-type lightly doped ion implantation is performed only in the N-type well 2 where the N-type lightly doped ion implantation is required to be performed in the region outside the photoresist region; each process parameter of the N-type lightly doped ion implantation may be set according to the actual process requirement, which is not limited in the present invention.
Step S05: referring to fig. 10, the N-type lightly doped ion implanted photoresist 4 is removed;
specifically, in this embodiment, after the N-type lightly doped ion implantation is completed, the N-type lightly doped ion implantation photoresist 4 may be removed by, but not limited to, wet etching.
Step S06: referring to fig. 11, a photolithography process is used to shield the region outside the photoresist region, and P-type lightly doped ion implantation is performed into the N-type well 2 of the photoresist region, so as to form a P-type lightly doped ion well 6 in the N-type well 2;
specifically, in this embodiment, a photoresist 7 may be covered on the N-type lightly doped ion implantation region outside the photoresist region (as shown in fig. 11 a), and then P-type lightly doped ion implantation is performed into the N-type well of the photoresist region, so as to prepare a P-type lightly doped ion well in the N-type well 2. The process parameters of the P-type lightly doped ion implantation may be set according to actual process conditions, which is not limited in the present invention. After the P-type lightly doped ion implantation is completed, the photoresist 7 may be removed by, but not limited to, wet etching (as shown in fig. 11 b).
Step S07: referring to fig. 12, a dielectric layer (not shown in fig. 12) is formed on the surface of the nonfunctional area, and contact holes 8 are formed in the dielectric layer and above the N-type lightly doped ion well 5 and the P-type lightly doped ion well 6 respectively;
specifically, in this embodiment, the dielectric layer may be deposited by, but not limited to, a chemical vapor deposition method, and the material of the dielectric layer may be, but not limited to, silicon oxide.
In this embodiment, the contact hole may be formed by using the prior art, including forming a contact hole structure in the dielectric layer by using photolithography and plasma dry etching processes, and then filling a conductive material, such as metal tungsten, in the contact hole structure, thereby forming a contact hole having a conductive function.
So far, the monitoring structure in this embodiment is completed, and the electron beam scanning process in this embodiment is further described below with reference to fig. 13 to 15, where the electron beam scanning process in this embodiment includes the following steps:
step S08: scanning the monitoring structure by adopting an electron beam in a negative potential electron beam scanning mode to obtain an actual voltage contrast image of the test structure;
specifically, in this embodiment, the parameters of the scanning of the monitoring structure by the electron beam may be set according to the actual process requirements, and preferably, may be: the pixel is 30-80 nm, the landing energy is 1800-2500 eV, and the current is 50-100 nA. The voltage contrast image reaction is called as a voltage contrast image in a picture; in the negative potential electron beam scanning mode, the contact hole in the N-type lightly doped ion implantation area in the monitoring structure is shown as a dark hole, and the contact hole in the photoresist area is shown as a bright hole, as shown in fig. 13, which is a schematic view of a cross-sectional structure of the monitoring structure containing the N-type lightly doped ion implantation area and the photoresist area in the negative potential scanning mode and a voltage contrast image of the contact hole thereof according to a preferred embodiment of the present invention, wherein two dotted frames form the photoresist area; the contact hole displays a bright hole or a dark hole which is determined according to the absorption degree of the structure corresponding to the contact hole to the secondary electrons in the electron beam; under a negative potential electron beam scanning mode, when the structure corresponding to the contact hole is conducted, a large amount of secondary electrons are absorbed, so that the contact hole is displayed as a bright hole, and otherwise, the contact hole is displayed as a dark hole; in this embodiment, in the negative potential electron beam scanning mode, the N-type well 2-P-type lightly doped ion well 6 forms a special-shaped structure in an on state, which can absorb a large amount of secondary electrons, and the secondary electrons flow from the P-type lightly doped ion well 6 to the N-type well 2 thereunder, so that the contact hole 7 corresponding to the structure is shown as a bright hole; the same type structure formed by the N-type trap 2-N type lightly doped ion trap 5 is in a non-conducting state, a large amount of secondary electrons are gathered on the surface of the N-type lightly doped ion trap 5, and therefore the contact hole 7 corresponding to the structure is displayed as a dark hole.
Step S09: setting a standard voltage contrast image of the monitoring structure under the condition of no alignment deviation;
specifically, please refer to fig. 14, which is a standard voltage contrast image of the monitoring structure according to a preferred embodiment of the present invention; and the standard voltage contrast image is reflected in the standard voltage contrast image, according to the principle, under the condition of no alignment deviation, the contact hole of the N-type well 2-N type lightly doped ion well 5 structure in the N-type lightly doped ion implantation area is displayed as a dark hole, and the contact hole of the N-type well 2-P type lightly doped ion well 6 structure in the light resistance area is displayed as a bright hole. The standard voltage contrast image is data without alignment deviation, and the standard voltage contrast image can be obtained by inputting relevant data according to the existing graphic simulation software.
Here, the standard voltage contrast image may also be obtained by: a defect scanning program is set in an electron beam scanner, at least one contact hole in the monitoring structure is set to be abnormal, and a standard voltage contrast image of the monitoring structure is simulated according to the type of the monitoring structure.
Step S10: comparing the actual voltage contrast image with the standard voltage contrast image to find out a contact hole with brightness variation; the ion trap structure comprises a contact hole which is formed in an N-type trap-N type lightly doped ion trap structure and is changed from a dark hole into a bright hole or is formed in an N-type trap-P type lightly doped ion trap structure and is changed from a bright hole into a dark hole;
specifically, please refer to fig. 15, which is a schematic diagram illustrating a comparison between an actual voltage contrast image and a standard voltage contrast image of a monitoring structure formed after performing electron beam scanning according to a preferred embodiment of the present invention, for convenience of description, the P-type and N-type lightly doped ion wells and the non-functional region of the semiconductor substrate in the monitoring structure are not shown in fig. 15.
The contrast between the actual voltage contrast image and the standard voltage contrast image can effectively detect the misalignment of the photoresist region; when the alignment deviation occurs in the photoresist area, that is, under the condition that the actual photoresist area is misaligned, the data corresponding to a certain contact hole in the standard voltage contrast image and the data corresponding to the actual voltage contrast image are different, which indicates that the actual photoresist area has the alignment deviation, and the data such as the position or the number of the contact holes which generate the image change can reflect the condition that the photoresist area has the alignment deviation.
In fig. 15, the thick dotted line represents an actual photoresist region, the thin dotted line represents a photoresist region that is not shifted, and the actual photoresist region is shifted downward as a whole, so that the contact hole showing the dark hole in the standard voltage contrast image is shown as a bright hole in the actual voltage contrast image, and the contact hole showing the bright hole in the standard voltage contrast image is shown as a dark hole in the actual voltage contrast image, which indicates that the misalignment occurs in the photoresist region.
Step S11: and obtaining the alignment deviation of the photoresist region, namely the alignment deviation of the N-type lightly doped ion implantation according to the data of the contact hole with the brightness change.
Specifically, referring to fig. 15, according to the data of the contact holes with image changes, such as the position data of the contact hole pitch, the vertical distance between the contact hole and the photoresist region, and the number of the contact holes with abnormal changes, the offset of the photoresist region, i.e. the alignment deviation, can be calculated; in fig. 15, the photoresist region is shifted downward by the distance between two adjacent contact holes in the vertical direction, i.e., the ion implantation alignment deviation of the N-type lightly doped ion trap. In the actual monitoring process, the offset of the photoresist area may not be an integral multiple of the contact hole pitch, however, when N-type lightly doped ions are implanted into the N-type well area of the photoresist area due to the offset of the photoresist area, the implantation position will also be displayed as a dark hole, which inevitably causes inaccuracy of only taking the integral multiple of the contact hole pitch, and at this time, the actual photoresist area is adjusted to shield all the N-type wells therebelow. The present invention is not limited in that the existing mathematical method can be used to obtain the misalignment of the photoresist region according to the comparison between the actual voltage contrast image and the standard voltage contrast image. For example, setting the offset within the range of x-x +1, wherein x is a non-negative integer, adopting a quadratic iteration method or other iteration methods to gradually select the offset, adjusting the position of the photoresist region according to the offset, and re-preparing the monitoring structure and the electron beam scanning until the actual voltage contrast image is the same as the standard voltage contrast image.
It should be noted that, in the electron beam scanning process of the CMOS, since different types of defects exist in the CMOS device, a plurality of different types of monitoring structures need to be established, and how to accurately find the voltage contrast image of the required monitoring structure during the electron beam scanning is also very important; therefore, in another preferred embodiment of the present invention, the electron beam scanning process may further specifically include:
step A01: scanning the monitoring structure by using an electron beam scanning instrument according to the defect detection program to obtain an image of the actual position of the contact hole in the monitoring structure; here, the image of the actual position of the contact hole can be obtained by taking an electronic scanning picture.
Specifically, in a defect detection program, at least one contact hole in different types of monitoring structures is set to have a defect; said defect is not necessarily a real defect, but is only an assumption; and obtaining type data of the monitoring structure according to the assumed position with the defect, and comparing the type data with the image of the actual position of the contact hole to find the image of the actual position of the contact hole of the monitoring structure.
Step A02: establishing a defect detection program in an electron beam scanning instrument, and obtaining an image of a standard position of a contact hole in the monitoring structure according to the defect detection program; here, the image of the standard position of the contact hole may be obtained by a data simulation program;
step A03: comparing the image at the actual position with the image at the standard position to obtain alignment deviation distribution data of the actual position of the contact hole;
step A04: and obtaining the alignment deviation of the photoresist area according to the alignment deviation distribution data.
In summary, the present invention provides a monitoring structure and a monitoring method for alignment of N-type lightly doped ion implantation in CMOS, which utilize the principle that a non-shaped NP junction is conducted and a non-shaped NN junction is not conducted in a negative potential electron beam scanning mode, and the monitoring structure and the monitoring method are provided with an N-type lightly doped ion implantation region formed by an N-type well-N-type lightly doped ion well structure and a photoresist region formed by an N-type well-P-type lightly doped ion well structure, wherein in an actual voltage contrast image obtained in the negative potential electron beam scanning mode, a contact hole corresponding to the former is displayed as dark, and a contact hole corresponding to the latter is displayed as bright, so that once the photoresist region is changed, the brightness of the corresponding contact hole is changed; and then obtaining the alignment deviation of the photoresist region according to the data, such as position data, quantity and the like, of the contact holes with brightness change, namely obtaining the alignment deviation of the N-type lightly doped ion implantation, thereby realizing the real-time monitoring of the alignment of the N-type lightly doped ion implantation in the CMOS and avoiding the unnecessary waste of the failure and cost of the PMOS device.
Although the present invention has been described with reference to preferred embodiments, which are illustrated for the purpose of illustration only and not for the purpose of limitation, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (9)
1. A monitoring structure of the alignment degree of N-type lightly doped ion implantation is positioned in a non-functional area of a semiconductor substrate, and is characterized in that the monitoring structure comprises an N-type lightly doped ion implantation area and a light resistance area, wherein the light resistance area is an area for carrying out P-type lightly doped ion implantation; wherein,
the N-type lightly doped ion implantation region is formed by an N-type trap-N-type lightly doped ion trap structure and comprises: the ion source comprises an N-type trap arranged in a non-functional area, N-type lightly doped ion wells arranged in the N-type trap, a grid electrode positioned between the N-type lightly doped ion wells, a dielectric layer positioned on the surface of the non-functional area, and contact holes positioned in the dielectric layer and corresponding to the N-type lightly doped ion wells;
the photoresistance region is formed by an N-type trap-P type lightly doped ion trap structure and comprises: the ion trap structure comprises an N-type trap arranged in a non-functional region, a P-type lightly doped ion trap arranged in the N-type trap, a grid electrode positioned between the P-type lightly doped ion traps, a dielectric layer positioned on the surface of the non-functional region and a contact hole positioned in the dielectric layer and corresponding to the P-type lightly doped ion trap;
in a voltage contrast image obtained in a negative potential electron beam scanning mode, the contact hole corresponding to the N-type trap-N type lightly doped ion trap structure is a dark hole, and the contact hole corresponding to the N-type trap-P type lightly doped ion trap structure is a bright hole.
2. The monitoring structure of claim 1, wherein the photoresist region is disposed around the N-type lightly doped ion implantation region; the shape of the light resistance area is a regular polygon with a hollow-out inner part, and the figure of the outline of the hollow-out area of the light resistance area is the figure of the N-type lightly doped ion implantation area.
3. The monitoring structure of claim 2, wherein the outline of the photoresist region and the outline of the hollow region have the same shape and the same geometric center; the pattern of the light resistance area comprises the outer contour and a pattern obtained by rotating the hollow area along the geometric center.
4. The monitoring structure of claim 1, wherein the N-wells in the monitoring structure are equally spaced in parallel columns and the gates are equally spaced in parallel rows; the rows where the grid electrodes are located and the columns where the N-type wells are located are distributed in an orthogonal mode;
in the photoresistance region, a P-type lightly doped ion well is arranged in an N-type trap between the grids; and in the N-type lightly doped ion implantation region, an N-type lightly doped ion well is arranged in an N-type trap between the grids.
5. The monitoring structure of claim 1, wherein each contour of the photoresist region is capable of finding a parallel straight line among straight lines formed by two adjacent contact holes.
6. A method for monitoring the alignment degree of N-type lightly doped ion implantation includes preparing monitoring structure and scanning electron beam,
the preparation of the monitoring structure comprises the following steps:
step S01: providing a non-functional area of a semiconductor substrate, and arranging an N-type lightly doped ion implantation area and a light resistance area in the non-functional area;
step S02: sequentially preparing an N-type well and a grid electrode in the non-functional region;
step S03: covering a layer of N-type lightly doped ion implantation photoresist on the photoresist area;
step S04: performing N-type lightly doped ion implantation in an N-type well of the N-type lightly doped ion implantation region, thereby forming an N-type lightly doped ion well in the N-type well;
step S05: removing the N-type lightly doped ion implantation photoresist;
step S06: shielding the region outside the light resistance region by adopting a photoetching process, and carrying out P-type lightly doped ion implantation in an N-type well in the light resistance region so as to form a P-type lightly doped ion well in the N-type well;
step S07: forming a dielectric layer on the surface of the non-functional area, and forming contact holes in the dielectric layer and above the N-type lightly doped ion well and the P-type lightly doped ion well respectively;
the electron beam scanning process includes:
step S08: scanning the monitoring structure by adopting an electron beam in a negative potential scanning mode to obtain an actual voltage contrast image of the test structure; the contact hole corresponding to the N-type trap-N type lightly doped ion trap structure is displayed as a dark hole, and the contact hole corresponding to the N-type trap-P type lightly doped ion trap structure is displayed as a bright hole;
step S09: setting a standard voltage contrast image map of the monitoring structure under the condition of no alignment deviation; the contact hole corresponding to the N-type trap-N type lightly doped ion trap structure is displayed as a dark hole, and the contact hole corresponding to the N-type trap-P type lightly doped ion trap structure is displayed as a bright hole;
step S10: comparing the actual voltage contrast image with the standard voltage contrast image, and finding out the contact holes with brightness change: the ion trap structure comprises a contact hole which is formed in the N-type trap-N type lightly doped ion trap structure and is changed from a dark hole into a bright hole or is formed in the N-type trap-P type lightly doped ion trap structure and is changed from a bright hole into a dark hole;
step S11: and obtaining the alignment deviation of the light resistance region according to the data of the contact hole with the brightness change, namely the alignment deviation of the N-type lightly doped ion implantation.
7. The monitoring method according to claim 6, wherein the step S09 specifically includes: and setting a defect scanning program in an electron beam scanner, assuming that at least one group of contact holes in the photoresist region and the N-type lightly doped ion implantation region is abnormal, and simulating a standard voltage contrast image of the monitoring structure by combining the type of the monitoring structure.
8. The monitoring method according to claim 6, wherein in the step S11, the data of the contact hole with the brightness change comprises position data and quantity data.
9. The monitoring method according to claim 6, wherein the photoresist region is disposed around the N-type lightly doped ion implantation region; the shape of the light resistance area is a regular polygon with a hollow inner part, and the graph of the hollow area is the graph of the N-type lightly doped ion implantation area.
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| CN107452639A (en) * | 2016-05-31 | 2017-12-08 | 中芯国际集成电路制造（天津）有限公司 | The method for detecting ion concentration |
| CN108010857A (en) * | 2016-11-01 | 2018-05-08 | 北大方正集团有限公司 | The method of inspection of ion implantation technology alignment quality |
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| US8531203B2 (en) * | 2010-06-11 | 2013-09-10 | International Business Machines Corporation | Mask alignment, rotation and bias monitor utilizing threshold voltage dependence |
| CN103021897B (en) * | 2012-11-12 | 2015-03-18 | 上海华力微电子有限公司 | Method for detecting semiconductor device electrical property failure |
| CN103346107A (en) * | 2013-06-27 | 2013-10-09 | 上海华力微电子有限公司 | Method for detecting alignment degree between polycrystalline silicon grid and contact hole |
| CN103489808B (en) * | 2013-09-22 | 2017-05-10 | 上海华力微电子有限公司 | Electron beam defect detection method capable of carrying out classification according to ion implantation areas |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107452639A (en) * | 2016-05-31 | 2017-12-08 | 中芯国际集成电路制造（天津）有限公司 | The method for detecting ion concentration |
| CN107452639B (en) * | 2016-05-31 | 2020-05-01 | 中芯国际集成电路制造（天津）有限公司 | Method for detecting ion concentration |
| CN108010857A (en) * | 2016-11-01 | 2018-05-08 | 北大方正集团有限公司 | The method of inspection of ion implantation technology alignment quality |
| CN108010857B (en) * | 2016-11-01 | 2020-12-29 | 北大方正集团有限公司 | Method for checking alignment quality of ion implantation process |
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