CN104124233A - Monitoring structure and method for N-type lightly-doped ion implantation registration - Google Patents
Monitoring structure and method for N-type lightly-doped ion implantation registration Download PDFInfo
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- CN104124233A CN104124233A CN201410357285.4A CN201410357285A CN104124233A CN 104124233 A CN104124233 A CN 104124233A CN 201410357285 A CN201410357285 A CN 201410357285A CN 104124233 A CN104124233 A CN 104124233A
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Abstract
The invention provides a monitoring structure and method for an N-type lightly-doped ion implantation registration. The monitoring structure comprises a photoresistance region and an N-type lightly-doped ion implantation region, the N-type lightly-doped ion implantation region is composed of an N-type trap-N-type lightly-doped ion trap structure which comprises N-type traps, N-type lightly-doped ion traps, gates, dielectric layers and contact holes corresponding to the N-type lightly-doped ion traps; the photoresistance region comprises an N-type trap-P-type lightly-doped ion trap structure which comprises N-type traps, P-type lightly-doped ion traps, gates, dielectric layers and contact holes corresponding to the P-type lightly-doped ion traps; negative potential electro beam scanning is utilized, brightness display differences of the contact holes corresponding to homojunctions and heterojunctions are utilized, the former displays dark holes, the latter display bright holes, the registration of the photoresistance region can be monitored according to the contact holes with brightness changes, accordingly real-time monitoring of the N-type lightly-doped ion implantation registration in the CMOS (complementary metal oxide semiconductor) can be achieved, the N-type lightly-doped ions can be prevented from being implanted into a PMOS (Positive Metal Oxide Semiconductor), and therefore electric leakage can be avoided.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of monitoring structure and method for supervising of monitoring N-type light dope Implantation Aligning degree in CMOS.
Background technology
Along with development and the critical size of integrated circuit technology are scaled, polytechnic process window is more and more less, cmos device becomes one of electronic component important in existing integrated circuit, in the preparation process of cmos device, requirement to various manufacturing process is more and more higher, such as source-drain electrode Implantation Aligning degree, light dope Implantation Aligning degree etc.; As shown in Figure 1, electric leakage defect schematic diagram for the PMOS that obtains through electron beam scanning, find after deliberation, it is when N-type light dope Implantation, to produce Aligning degree deviation that PMOS produces one of formation reason of electric leakage defect, thereby causing having injected N-type light dope ion in the light doping section in PMOS, in Fig. 1, should be bright hole for the position display in dark hole in dotted line frame, in this explanation PMOS, injected N-type light dope ion, that is to say that N-type light dope Implantation produces Aligning degree deviation.PMOS produces electric leakage defect will cause the even yield inefficacy of whole cmos device, thereby increase cost.Therefore it is very necessary, for this N-type light dope Implantation Aligning degree, monitoring.It is during due to N-type light dope Implantation that N-type light dope Implantation produces Aligning degree deviation after all, covers that the photoresistance generation Aligning degree deviation in PMOS region causes.Therefore, monitoring N-type light dope Implantation Aligning degree deviation can realize by the photoresistance Aligning degree deviation of monitoring in this N-type light dope ion implantation process.
As shown in Figure 2, during N-type light dope Implantation, photoresistance produces the various situation schematic diagrames of Aligning degree deviation, wherein, dotted line represents out-of-the way position, solid line represents normal position, can see, the situation of photoresistance generation deviation comprises: single direction offset-type (Fig. 2 (a)), excessive type (Fig. 2 (b)), interior receipts type (Fig. 2 (c)), rotary-type (Fig. 2 (d)), comprehensive (Fig. 2 (e)).Industry all adopts optical detection to monitor at present, but the complexity due to Aligning degree deviation in the restriction of resolution and actual photoresist process, thereby be difficult to be monitored accurately, the more important thing is, its testing result cannot be set up and directly contact with caused electric leakage problem.
Therefore, urgent need can be carried out test structure and the method for monitoring in real time exactly to N-type light dope Implantation Aligning degree in CMOS, thereby avoids the generation of PMOS device leak electricity and cause the problem of whole component failure to occur.
Summary of the invention
In order to overcome above problem, the present invention aims to provide monitoring structure and the method for supervising of N-type light dope Implantation Aligning degree in a kind of CMOS, the Aligning degree of the photoresistance adopting while utilizing N-type light dope Implantation, monitor N-type light dope Implantation Aligning degree, thereby realize, N-type light dope Implantation Aligning degree is carried out accurately and effectively monitoring in real time, avoid injecting N-type light dope ion in PMOS device and produce electric leakage.
The invention provides a kind of monitoring structure of N-type light dope Implantation Aligning degree, described monitoring structure is arranged in the non-functional area of Semiconductor substrate, wherein, described monitoring structure comprises N-type light dope ion implanted region and photoresistance district, and described photoresistance district is the region of carrying out P type light dope Implantation; Wherein,
Described N-type light dope ion implanted region consists of N-type trap-N-type light dope ion trap structure, comprise: the N-type trap arranging in nonfunctional area, the N-type light dope ion trap arranging in described N-type trap, grid between described N-type light dope ion trap, be positioned at the dielectric layer on surface, described nonfunctional area, and be arranged in described dielectric layer and corresponding to the contact hole of described N-type light dope ion trap;
Described photoresistance district consists of N-type trap-P type light dope ion trap structure, comprise: the N-type trap arranging in nonfunctional area, the P type light dope ion trap arranging in described N-type trap, grid between described P type light dope ion trap, be positioned at the dielectric layer on surface, nonfunctional area, and be arranged in described dielectric layer and corresponding to the contact hole of described P type light dope ion trap;
Wherein, in the voltage contrast striograph obtaining under negative potential electron beam scanning pattern, described N-type trap-N-type please contact hole corresponding to light dope ion trap structure be dark hole, and contact hole corresponding to described N-type trap-P type light dope ion trap structure is bright hole.
Preferably, described photoresistance district in described N-type light dope ion implanted region around around setting; The regular polygon that is shaped as inner hollow out in described photoresistance district, the figure of the profile in the hollow out region in described photoresistance district is the figure of described N-type light dope ion implanted region.
Preferably, the shape of the outline in described photoresistance district and the profile in described hollow out region is identical and have an identical geometric center; The figure in described photoresistance district comprises described outline and along described geometric center, described hollow out region is rotated to the figure obtaining.
Preferably, the N-type trap in described monitoring structure is some parallel row equidistantly arranges, and described grid is some parallel row and equidistantly arranges; And the orthogonal thereto distribution of row at the row at described grid place and described N-type trap place;
In described photoresistance district, in the N-type trap between described grid, be provided with P type light dope ion trap; In described N-type light dope ion implanted region, in the N-type trap between described grid, be provided with N-type light dope ion trap.
The present invention also provides a kind of method for supervising of N-type light dope Implantation Aligning degree, and it comprises preparation and two processes of electron beam scanning of monitoring structure, wherein,
The preparation of described monitoring structure comprises:
Step S01: the nonfunctional area of a Semiconductor substrate is provided, and N-type light dope ion implanted region and photoresistance district are set in described nonfunctional area;
Step S02: carry out successively the preparation of N-type trap and grid in described nonfunctional area;
Step S03: cover one deck N-type light dope Implantation photoresistance in described photoresistance district;
Step S04: carry out N-type light dope Implantation in the N-type trap of described N-type light dope ion implanted region, thereby form N-type light dope ion trap in this N-type trap;
Step S05: remove described N-type light dope Implantation photoresistance;
Step S06: adopt photoetching process to shelter from the region outside described photoresistance district, carry out P type light dope Implantation in the N-type trap in described photoresistance district, thereby form P type light dope ion trap in this N-type trap;
Step S07: form dielectric layer on surface, described nonfunctional area, form contact hole in described dielectric layer and above corresponding respectively to described N-type light dope ion trap and described P type light dope ion trap;
Described electron beam scanning process comprises:
Step S08: under negative potential scan pattern, adopt electron beam to scan described monitoring structure, obtain the virtual voltage contrast striograph of described test structure; Wherein, contact hole corresponding to described N-type trap-N-type light dope ion trap structure is shown as dark hole, and contact hole corresponding to described N-type trap-P type light dope ion trap structure is shown as bright hole;
Step S09: described monitoring structure is set at the normal voltage contrast striograph without in Aligning degree deviation situation; Wherein, contact hole corresponding to described N-type trap-N-type light dope ion trap structure is shown as dark hole, and contact hole corresponding to described N-type trap-P type light dope ion trap structure is shown as bright hole;
Step S10: described virtual voltage contrast striograph and described normal voltage contrast striograph are contrasted, find out the contact hole that brightness changes occurs: wherein, comprise in described N-type trap-N-type light dope ion trap structure and become in bright hole or described N-type trap-P type light dope ion trap structure and from bright hole, become the contact hole in dark hole from dark hole;
Step S11: the data of the described contact hole changing according to found out generation brightness obtain the Aligning degree deviation in described photoresistance district, that is to say described N-type light dope Implantation Aligning degree deviation.
Preferably, described step S09 specifically comprises: Defect Scanning formula is set in electron beam scanning instrument, described in supposing to have one group at least in described photoresistance district and described N-type light dope ion implanted region, contact hole occurs extremely, then in conjunction with the type simulation of described monitoring structure, goes out the normal voltage contrast striograph of described monitoring structure.
Preferably, in described step S11, the data of the contact hole that described generation brightness changes comprise position data and incremental data.
Preferably, described photoresistance district in described N-type light dope ion implanted region around around setting; The regular polygon that is shaped as inner hollow out in described photoresistance district, the figure in the region of described hollow out is the figure of described N-type light dope ion implanted region.
Monitoring structure and the method for N-type light dope Implantation Aligning degree in CMOS of the present invention, utilization is under negative potential electron beam scanning pattern, special-shaped NP knot conducting and homotype NN ties the principle of not conducting, the N-type light dope ion implanted region consisting of N-type trap-N-type light dope ion trap structure is set in monitoring structure, and the photoresistance district being formed by N-type trap-P type light dope ion trap structure, in the virtual voltage contrast striograph obtaining under negative potential electron beam scanning pattern, the former is shown as dead color by the contact hole of correspondence, contact hole corresponding to the latter is shown as light tone, therefore, once photoresistance district changes, to cause corresponding contact hole generation brightness to change, then according to the data that the contact hole that brightness changes occurs such as position data, quantity etc. obtains the Aligning degree deviation in photoresistance district, that is to say and obtain N-type light dope Implantation Aligning degree deviation, thereby realize the real-time monitoring to N-type light dope Implantation Aligning degree in CMOS, avoid the unnecessary waste of PMOS component failure and cost.
Accompanying drawing explanation
The electric leakage defect schematic diagram that Fig. 1 is the PMOS that obtains through electron beam scanning
When Fig. 2 is N-type light dope Implantation, photoresistance produces the various situation schematic diagrames of Aligning degree deviation
Fig. 3 is the schematic top plan view of the monitoring structure of N-type light dope Implantation Aligning degree in the CMOS of a preferred embodiment of the present invention
Fig. 4 is partial cross section's structural representation of the monitoring structure of N-type light dope Implantation Aligning degree in the CMOS of a preferred embodiment of the present invention
The schematic flow sheet of the method for supervising of N-type light dope Implantation Aligning degree in Fig. 5 CMOS of the present invention
Fig. 6-12 are the corresponding plan structure schematic diagram of each preparation process of the monitoring structure of a preferred embodiment of the present invention
Figure 13 is the cross section structure of monitoring structure and the voltage contrast image schematic diagram of contact hole thereof that contains N-type light dope ion implanted region and photoresistance district under the negative potential scan pattern of a preferred embodiment of the present invention
Figure 14 is the normal voltage contrast striograph of the monitoring structure of a preferred embodiment of the present invention
Figure 15 is the virtual voltage contrast image of formed monitoring structure and the contrast schematic diagram of normal voltage contrast image after electron beam scanning of carrying out of a preferred embodiment of the present invention
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art is also encompassed in protection scope of the present invention.
The principle of monitoring structure of the present invention and method for supervising is: according in electron beam scanning process, homologous structure N-type trap-N-type light dope ion trap structure, abnormally-structured N-type trap-P type light dope ion trap structure is different to the degree of absorption of the secondary electron in electron beam, thereby the color difference of the contact hole of the structural correspondence of above-mentioned two kinds obtaining judges, under negative potential condition, the contact hole of the former correspondence is shown as dark hole, and contact hole corresponding to the latter is shown as bright hole; While there is Aligning degree deviation in the position of the photoresistance in N-type light dope ion implantation process, the photoresistance district in monitoring structure also can change, the contact hole that originally should be shown as bright hole (or dark hole) is shown as dark hole (or bright hole), and the Aligning degree deviation that obtains photoresistance district according to the position of the contact hole changing is also the Aligning degree deviation of N-type light dope Implantation.
Why N-type trap-P type light dope ion trap structure is shown as bright hole, be due to: under negative potential condition, this structure conducting, the secondary electron major part of incident in electron beam is absorbed by this structure, by P type light dope ion trap, flow to N-type trap, thereby the contact hole of this structural correspondence is shown as bright hole; In like manner, N-type trap-N-type light dope ion trap structure is shown as dark hole, be due to: under negative potential condition, this not conducting of structure, the secondary electron major part of incident in electron beam is blocked in this body structure surface, thus the contact hole of this structural correspondence is shown as dark hole.
Below with reference to accompanying drawing 3-4 and specific embodiment, the monitoring structure of N-type light dope Implantation Aligning degree in CMOS is described in further detail.It should be noted that, accompanying drawing all adopts very the form simplified, uses non-ratio accurately, and only in order to object convenient, that clearly reach aid illustration the present embodiment.
Monitoring structure of the present invention, is arranged in Semiconductor substrate, and the Semiconductor substrate that the present invention adopts has functional areas and nonfunctional area, and nonfunctional area refers to can not affect the region of Semiconductor substrate function such as Cutting Road, virtual region etc.Semiconductor substrate can be, but not limited to as silicon substrate; Monitoring structure of the present invention is arranged in the non-functional area of Semiconductor substrate, and it includes N-type light dope ion implanted region and photoresistance district, and photoresistance district is the region of carrying out P type light dope Implantation.
This is because what one of reason of PMOS leaky adopted while being N-type light dope Implantation blocks without the photoresistance generation Aligning degree deviation of carrying out N-type light dope Implantation region, thereby causes having injected N-type light dope ion in the N-type trap of PMOS; Thus, monitoring N-type light dope Implantation Aligning degree can be realized by monitoring the Aligning degree of this photoresistance, and the Aligning degree of this photoresistance can utilize the Aligning degree in the photoresistance district in monitoring structure to monitor.Therefore, N-type light dope ion implanted region and photoresistance district are set in monitoring structure, N-type light dope ion implanted region is for injecting the region of N-type light dope ion, photoresistance district is for injecting the region of P type light dope ion, in the process of injecting N-type light dope ion, photoresistance is set for stopping that N-type light dope Implantation is to photoresistance district in photoresistance district, if there is Aligning degree deviation in photoresistance district, can cause N-type light dope Implantation generation Aligning degree deviation, therefore, by the Aligning degree deviation in monitoring photoresistance district, can find the Aligning degree deviation of N-type light dope Implantation.
In N-type light dope ion implanted region, by N-type trap-N-type light dope ion trap structure, formed, comprise: the N-type trap arranging in nonfunctional area, the N-type light dope ion trap arranging in N-type trap, grid between N-type light dope ion trap, be positioned at the dielectric layer on surface, nonfunctional area, and be arranged in dielectric layer and corresponding to the contact hole of N-type light dope ion trap.
Photoresistance district consists of N-type trap-P type light dope ion trap structure, comprise: the N-type trap arranging in nonfunctional area, the P type light dope ion trap arranging in N-type trap, grid between P type light dope ion trap, be positioned at the dielectric layer on surface, nonfunctional area, and be arranged in dielectric layer and corresponding to the contact hole of P type light dope ion trap; It should be noted that, photoresistance district should not block above the N-type trap of N-type light dope ion implanted region, and therefore, the outline line in photoresistance district can be above the region above grid or between N-type trap.
In the voltage contrast striograph obtaining under negative potential electron beam scanning pattern, contact hole corresponding to described N-type trap-N-type light dope ion trap structure is dark hole, and contact hole corresponding to described N-type trap-P type light dope ion trap structure is bright hole.
It should be noted that, in the present invention, in the dielectric layer above the grid in photoresistance district or N-type light dope ion implanted region, also can be provided with contact hole.
Referring to Fig. 3, is the schematic top plan view of the monitoring structure of N-type light dope Implantation Aligning degree in the CMOS of a preferred embodiment of the present invention; In the present embodiment, monitoring structure is arranged in the nonfunctional area 1 of Semiconductor substrate, and N-type trap 2 is arranged to some parallel row and is equidistantly arranged, and grid 3 is arranged to some parallel row and is equidistantly arranged, and arranges with N-type trap 2 is orthogonal thereto; The region of two dotted line frame formations is photoresistance district a, region in inner dotted line frame is N-type light dope ion implanted region b, photoresistance district a at N-type light dope ion implanted region b around around setting, the regular polygon that is shaped as inner hollow out in photoresistance district, and the shape of the outline of photoresistance district a and the interior profile in its inner hollow out region is identical and have an identical geometric center, such as, the figure in photoresistance district comprises outline and along geometric center, hollow out region is rotated to the figure that certain angle obtains such as 90 degree etc.; Why so designing the figure in photoresistance district, is because the photoresistance district with inside and outside two profiles is more responsive to the skew of photoresistance or rotation, is convenient to find and calculates Aligning degree more accurately.The figure of the profile in hollow out region is also the figure of N-type light dope ion implanted region b, can be regular polygon, can be, but not limited to as shapes such as rhombus, regular hexagon, equilateral triangle, squares; Because the length of side of regular polygon is identical and interior angle is known, be convenient to subsequent calculations Aligning degree deviation, so in the present embodiment preferably regular polygon as the outline figure of photoresistance district a and the figure in its inner hollow out region.In N-type trap 2 between grid 3, be provided with P type light dope ion trap 6; In N-type light dope ion implanted region b, in the N-type trap 2 between grid 3, be provided with N-type light dope ion trap 5; Between grid 3 and respectively, above P type light dope ion trap 6 and N-type light dope ion trap 5, be provided with contact hole 8; It should be noted that, for the ease of expressing, display dielectric layer not in accompanying drawing 3.
In the present invention, photoresistance district a can also have following characteristics: in the straight line that a each outline line in photoresistance district all can form at adjacent two contact holes, find parallel with it straight line.Like this, when skew occurs photoresistance district a, can guarantee that each contact hole generation brightness on straight line that each outline line parallels with it contact hole forms changes more consistent, thereby can effectively judge the direction that skew occurs photoresistance district a; Or when photoresistance district a rotates, situation about changing according to the brightness of the contact hole on the straight line paralleling with its outline line, also can effectively judge the data such as the anglec of rotation.That is to say that the profile paralleling with contact hole place straight line is all very responsive to the skew of photoresistance district a or rotation, thereby effectively detect the Aligning degree situation in photoresistance district.It should be noted that, no matter how the outline line of photoresistance district a arranges, and it all can not block the N-type trap top in N-type light dope ion implanted region, and this just requires the outline line of photoresistance district a above the region between N-type trap or above grid.
For the ease of clear complete expression monitoring structure of the present invention, refer to Fig. 4, listed the cross section structure schematic diagram that contains N-type light dope ion implanted region and photoresistance district of a preferred embodiment of the present invention; Wherein, dotted line Kuang Neiwei photoresistance district; N-type light dope ion implanted region consists of N-type trap-N-type light dope ion trap structure, comprise: the N-type trap 2 arranging in nonfunctional area 1, the N-type light dope ion trap 5 arranging in N-type trap 2, grid (not shown) between N-type light dope ion trap 5, be positioned at the dielectric layer 9 on 1 surface, nonfunctional area, and be arranged in dielectric layer 9 and corresponding to the contact hole 8 of N-type light dope ion trap 5.Photoresistance district consists of N-type trap-P type light dope ion trap structure, comprise: the N-type trap 2 arranging in nonfunctional area 1, the P type light dope ion trap 6 arranging in N-type trap 2, grid (not shown) between P type light dope ion trap 6, be positioned at the dielectric layer 9 on 1 surface, nonfunctional area, and be arranged in dielectric layer 9 and corresponding to the contact hole 8 of P type light dope ion trap 6.
Below with reference to accompanying drawing 5-15 and specific embodiment, the method for supervising of N-type light dope Implantation Aligning degree in CMOS is described in further detail.It should be noted that, accompanying drawing all adopts very the form simplified, uses non-ratio accurately, and only in order to object convenient, that clearly reach aid illustration the present embodiment.
Referring to Fig. 5, is the schematic flow sheet of the method for supervising of N-type light dope Implantation Aligning degree in CMOS of the present invention; In CMOS of the present invention, the method for supervising of N-type light dope Implantation Aligning degree comprises preparation and two processes of electron beam scanning of monitoring structure:
First, referring to Fig. 6-12, is the corresponding plan structure schematic diagram of each preparation process of the monitoring structure of a preferred embodiment of the present invention; The monitoring structure of the present embodiment adopts the monitoring structure in above-mentioned accompanying drawing 3 and accompanying drawing 4, and the method preparing and adopt the monitoring structure in electron beam scanning accompanying drawing 3 and accompanying drawing 4 of take describes as example; The preparation of the monitoring structure of the present embodiment comprises:
Step S01: refer to Fig. 6, the nonfunctional area 1 of a Semiconductor substrate is provided, and N-type light dope ion implanted region b and photoresistance district a are set in nonfunctional area 1;
Concrete, in the present invention, Semiconductor substrate comprises for the preparation of the functional areas of cmos device and for the preparation of the nonfunctional area of monitoring structure; Semiconductor substrate can be any Semiconductor substrate, and in the present embodiment, Semiconductor substrate is silicon substrate; For ease of describing, in Fig. 6-12, only show the monitoring structure schematic diagram of nonfunctional area 1, and the structure of cmos device in functional areas and be prepared as prior art does not repeat them here.Photoresistance district a is the region of carrying out P type light dope Implantation, as two regions that dotted line frame forms in Fig. 6; N-type light dope ion implanted region b is the region in inner dotted line frame.In the present embodiment, photoresistance district in N-type light dope ion implanted region around around setting; Photoresistance district a can be the regular polygon of inner hollow out, such as center hollow out, the figure in the region of hollow out is the figure of N-type light dope ion implanted region b, and the shape of the outline of photoresistance district a and the interior profile in its inner hollow out region is identical and have an identical geometric center, the figure of N-type light dope ion implanted region b can be, but not limited to as rhombus, all right regular hexagon, square, rectangle etc.Monitoring structure in this method adopts the structure shown in Fig. 3 in above-described embodiment, and its structure is repeated no more.
Step S02: refer to Fig. 7, carry out successively the preparation of N-type trap 2 and grid 3 in nonfunctional area 1;
Concrete, in the present embodiment, can adopt existing method in nonfunctional area 1, to carry out successively the preparation of N-type trap 2 and grid 3, the present invention repeats no more this; It should be noted that, in order to realize the real-time monitoring to the N-type light dope Implantation in CMOS preparation technology, in the process of the monitoring structure in preparation the present invention, in functional areas also at interlock system for cmos device, like this, once find that in monitoring structure Aligning degree deviation appears in photoresistance district, can know that Aligning degree deviation appears in the N-type light dope Implantation of nmos device, thereby can stop preparation, and make corresponding correction and eliminate N-type light dope Implantation Aligning degree deviation.N-type trap 2 is arranged to some parallel columns of equidistantly arranging, and grid 3 is arranged to some parallel row of equidistantly arranging, and arranges with N-type trap 2 is orthogonal thereto.
Step S03: refer to Fig. 8, cover one deck N-type light dope Implantation photoresistance 4 in photoresistance district;
Concrete, in the present embodiment, owing to all carrying out N-type light dope ion implantation process on the nonfunctional area 1 at whole silicon substrate, need to adopt photoresistance will carry out P type light dope Implantation region and shelter from; Here, in the preparation process of monitoring structure, the photoresistance adopting during N-type light dope Implantation is called N-type light dope Implantation photoresistance 4, the Ze Wei photoresistance district, region of N-type light dope Implantation photoresistance 4 correspondences; That is to say, photoresistance district is the region that need to carry out P type light dope Implantation, and the figure of N-type light dope Implantation photoresistance 4 is identical with the figure in photoresistance district.
Step S04: refer to Fig. 9, carry out N-type light dope Implantation in the N-type trap 2 in N-type light dope ion implanted region, thereby form N-type light dope ion trap 5 in this N-type trap;
Concrete, in the present embodiment, under the protection of N-type light dope Implantation photoresistance 4, the region outside Jin Dui photoresistance district need to carry out carrying out N-type light dope Implantation in the N-type trap 2 of N-type light dope Implantation; Each technological parameter of N-type light dope Implantation can require to set according to actual process, and the present invention is not restricted this.
Step S05: refer to Figure 10, remove N-type light dope Implantation photoresistance 4;
Concrete, in the present embodiment, after N-type light dope Implantation completes, can be, but not limited to wet etching and remove N-type light dope Implantation photoresistance 4.
Step S06: refer to Figure 11, adopt photoetching process to shelter from the region outside photoresistance district, carry out P type light dope Implantation in the N-type trap 2 in photoresistance district, thereby form P type light dope ion trap 6 in this N-type trap 2;
Concrete, in the present embodiment, can on the N-type light dope ion implanted region outside photoresistance district, cover one deck photoresistance 7 (as shown in Figure 11 a), then in the N-type trap in photoresistance district, carry out P type light dope Implantation, thereby in N-type trap 2, prepare P type light dope ion trap.The technological parameter of P type light dope Implantation can be set according to actual process condition, and the present invention is not restricted this.After P type light dope Implantation completes, can also adopt but be not limited to wet etching and remove photoresistance 7 (as shown in Figure 11 b).
Step S07: refer to Figure 12, form dielectric layer (in Figure 12 not display dielectric layer) on nonfunctional area surface, form contact hole 8 in dielectric layer and above corresponding respectively to N-type light dope ion trap 5 and P type light dope ion trap 6;
Concrete, in the present embodiment, can be, but not limited to adopt chemical vapour deposition technique metallization medium layer, the material of dielectric layer can but be not limited to for silica.
In the present embodiment, can adopt prior art to form contact hole, comprise and adopt photoetching and plasma dry etch process in dielectric layer, to form contact hole structure, then filled conductive material in contact hole structure, such as tungsten, thereby form the contact hole with conducting function.
So far, the monitoring structure in the present embodiment is just made complete, below in conjunction with accompanying drawing 13-15, the electron beam scanning process of embodiment is described further, and the electron beam scanning process of the present embodiment comprises the following steps:
Step S08: under negative potential electron beam scanning pattern, adopt electron beam to scan monitoring structure, obtain the virtual voltage contrast striograph of test structure;
Concrete, in the present embodiment, the parameter that electron beam scans monitoring structure can require to set according to actual process, preferably, can be: pixel is 30～80 nm, and landing energy is 1800～2500 eV, and electric current is 50～100 nA.The reaction of voltage contrast image is referred to as voltage contrast striograph in a picture; Under negative potential electron beam scanning pattern, contact hole in N-type light dope ion implanted region in monitoring structure is shown as dark hole, contact hole in photoresistance district is shown as bright hole, as shown in figure 13, the cross section structure of monitoring structure and the voltage contrast image schematic diagram of contact hole thereof that under negative potential scan pattern for a preferred embodiment of the present invention, contain N-type light dope ion implanted region and photoresistance district, wherein, two dotted line frame formations is photoresistance district; Contact hole shows that Huo An hole, bright hole is according to the corresponding structure of contact hole, the degree of absorption of the secondary electron in electron beam to be decided; Under negative potential electron beam scanning pattern, when the corresponding structure conducting of contact hole, absorb a large amount of secondary electrons, thereby contact hole is shown as bright hole, otherwise, be shown as dark hole; In the present embodiment, under negative potential electron beam scanning pattern, the abnormally-structured conducting state that is that N-type trap 2-P type light dope ion trap 6 forms, it can absorb a large amount of secondary electrons, the N-type trap 2 of secondary electron below P type light dope ion trap 6 flows to it, thus the contact hole of this structural correspondence 7 is shown as bright hole; And the homologous structure that N-type trap 2-N type light dope ion trap 5 forms is not on-state, a large amount of secondary electrons is gathered in N-type light dope ion trap 5 surfaces, thereby the contact hole of this structural correspondence 7 is shown as dark hole.
Step S09: monitoring structure is set at the normal voltage contrast striograph without in Aligning degree deviation situation;
Concrete, refer to Figure 14, be the normal voltage contrast striograph of the monitoring structure of a preferred embodiment of the present invention; The reaction of normal voltage contrast striograph is in normal voltage contrast striograph, according to aforementioned principles, without Aligning degree deviation in the situation that, in N-type light dope ion implanted region, the contact hole of N-type trap 2-N type light dope ion trap 5 structures is shown as dark hole, and the contact hole of N-type trap 2-P type light dope ion trap 6 structures in photoresistance district is shown as bright hole.Normal voltage contrast striograph is without the data in Aligning degree deviation situation, can related data input be obtained to normal voltage contrast striograph according to existing graphic simulation software.
Here, normal voltage contrast image can also obtain in the following manner: Defect Scanning formula is set in electron beam scanning instrument, setting at least one contact hole in monitoring structure of the present invention occurs extremely, to go out the normal voltage contrast striograph of monitoring structure according to the type simulation of monitoring structure.
Step S10: virtual voltage contrast striograph and normal voltage contrast striograph are contrasted, find out the contact hole that brightness changes; Wherein, comprise in N-type trap-N-type light dope ion trap structure and become in bright hole or N-type trap-P type light dope ion trap structure and from bright hole, become the contact hole in dark hole from dark hole;
Concrete, refer to Figure 15, the virtual voltage contrast image of formed monitoring structure and the contrast schematic diagram of normal voltage contrast image after electron beam scanning of carrying out for a preferred embodiment of the present invention, for the ease of expressing, P type light dope ion trap and the N-type light dope ion trap in display monitoring structure not in Figure 15, and the nonfunctional area of Semiconductor substrate.
Under virtual voltage contrast striograph and the contrast of normal voltage contrast striograph, there is Aligning degree deviation situation and can effectively detect in photoresistance district; When there is Aligning degree deviation in photoresistance district, that is to say that actual photoresistance district occurs in the situation of various misalignment, a certain contact hole in normal voltage contrast striograph in corresponding data and virtual voltage contrast striograph corresponding data there will be difference, this just shows that actual photoresistance district has produced Aligning degree deviation, and the data such as the position of these contact holes that generation image changes or quantity can reflect that the situation of deviation of the alignment occurs in photoresistance district.
In Figure 15, thick dashed line represents actual photoresistance district, fine dotted line represents not occur the photoresistance district of skew, there is overall offset downwards in actual photoresistance district, the contact hole that shows dark hole in normal voltage contrast striograph is shown as bright hole in virtual voltage contrast striograph, the contact hole that is shown as bright hole in normal voltage contrast striograph is shown as dark hole in virtual voltage contrast striograph, and this just shows that Aligning degree deviation has occurred in photoresistance district.
Step S11: the data of the contact hole changing according to found out generation brightness obtain the Aligning degree deviation in photoresistance district, that is to say N-type light dope Implantation Aligning degree deviation.
Concrete, refer to Figure 15, the position datas such as vertical range according to the data of the contact hole of generation image variation such as contact hole spacing, contact hole and photoresistance district, and the quantity of the contact hole of generation ANOMALOUS VARIATIONS etc., can calculate photoresistance district side-play amount, i.e. Aligning degree deviation; In Figure 15, photoresistance district is offset downwards, and side-play amount is the spacing of two contact holes adjacent on vertical direction, that is to say that N-type light dope ion trap ion injects Aligning degree deviation.In actual monitored process, may there is the situation of the integral multiple that is not contact hole spacing in photoresistance district side-play amount, when Ran Dang photoresistance district skew causes and has injected N-type light dope ion in the N-type well region in photoresistance district, this injection phase also can be shown as dark hole, this just causes the inaccuracy of the numerical value of the integral multiple of only getting contact hole spacing unavoidably, now, as long as make actual photoresistance district shelter from all N-type traps below it by adjustment.According to the contrast of virtual voltage contrast striograph and normal voltage contrast striograph, can adopt existing mathematical method to obtain the Aligning degree deviation in photoresistance district, the present invention is not restricted this.For example, set side-play amount within the scope of x～x+1, wherein x is nonnegative integer, adopt second iteration method or other iterative method, progressively choose side-play amount, and according to this side-play amount, adjust the position in photoresistance district, again prepare monitoring structure and electron beam scanning, until virtual voltage contrast striograph is identical with described normal voltage contrast striograph.
It should be noted that, in electron beam scanning process for CMOS, owing to there being dissimilar defect in cmos device, need to set up a plurality of dissimilar monitoring structures, the voltage contrast image that so how finds accurately needed monitoring structure during at electron beam scanning is also very important; Therefore,, in another preferred embodiment of the present invention, electron beam scanning process can also specifically comprise:
Steps A 01: utilize electron beam scanning instrument according to defects detection formula, monitoring structure to be scanned the striograph of the physical location that obtains the contact hole in monitoring structure; Here, the striograph of the physical location of contact hole can obtain by taking electronic scanning picture.
Concrete, in defects detection formula, set in dissimilar monitoring structure and have at least a contact hole to occur defect; Said defect is real defect not necessarily, is a kind of hypothesis; According to hypothesis, occur that the position of defect obtains the categorical data of monitoring structure, and contrast with the striograph of contact hole physical location, find the striograph of the contact hole physical location of the monitoring structure in the present invention.
Steps A 02: set up defects detection formula in electron beam scanning instrument, obtain the striograph of the normal place of the contact hole in monitoring structure according to defects detection formula; Here, the striograph of the normal place of contact hole can obtain by digital simulation program;
Steps A 03: contrast according to the striograph of the striograph of physical location and normal place, obtain the Aligning degree deviation profile data of the physical location of contact hole;
Steps A 04: the Aligning degree deviation that obtains photoresistance district according to above-mentioned Aligning degree deviation profile data.
In sum, monitoring structure and the method for supervising of N-type light dope Implantation Aligning degree in CMOS of the present invention, monitoring structure and the method for N-type light dope Implantation Aligning degree in CMOS of the present invention, utilization is under negative potential electron beam scanning pattern, special-shaped NP knot conducting and homotype NN ties the principle of not conducting, the N-type light dope ion implanted region consisting of N-type trap-N-type light dope ion trap structure is set in monitoring structure, and the photoresistance district being formed by N-type trap-P type light dope ion trap structure, in the virtual voltage contrast striograph obtaining under negative potential electron beam scanning pattern, the former is shown as dead color by the contact hole of correspondence, contact hole corresponding to the latter is shown as light tone, therefore, once photoresistance district changes, to cause corresponding contact hole generation brightness to change, then according to the data that the contact hole that brightness changes occurs such as position data, quantity etc. obtains the Aligning degree deviation in photoresistance district, that is to say and obtain N-type light dope Implantation Aligning degree deviation, thereby realize the real-time monitoring to N-type light dope Implantation Aligning degree in CMOS, avoid the unnecessary waste of PMOS component failure and cost.
Although the present invention discloses as above with preferred embodiment; right described embodiment only gives an example for convenience of explanation; not in order to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion with described in claims.
Claims (9)
1. the monitoring structure of a N-type light dope Implantation Aligning degree, described monitoring structure is arranged in the non-functional area of Semiconductor substrate, it is characterized in that, described monitoring structure comprises N-type light dope ion implanted region and photoresistance district, and described photoresistance district is the region of carrying out P type light dope Implantation; Wherein,
Described N-type light dope ion implanted region consists of N-type trap-N-type light dope ion trap structure, comprise: the N-type trap arranging in nonfunctional area, the N-type light dope ion trap arranging in described N-type trap, grid between described N-type light dope ion trap, be positioned at the dielectric layer on surface, described nonfunctional area, and be arranged in described dielectric layer and corresponding to the contact hole of described N-type light dope ion trap;
Described photoresistance district consists of N-type trap-P type light dope ion trap structure, comprise: the N-type trap arranging in nonfunctional area, the P type light dope ion trap arranging in described N-type trap, grid between described P type light dope ion trap, be positioned at the dielectric layer on surface, nonfunctional area, and be arranged in described dielectric layer and corresponding to the contact hole of described P type light dope ion trap;
Wherein, in the voltage contrast striograph obtaining under negative potential electron beam scanning pattern, described N-type trap-N-type please contact hole corresponding to light dope ion trap structure be dark hole, and contact hole corresponding to described N-type trap-P type light dope ion trap structure is bright hole.
2. monitoring structure according to claim 1, is characterized in that, described photoresistance district in described N-type light dope ion implanted region around around setting; The regular polygon that is shaped as inner hollow out in described photoresistance district, the figure of the profile in the hollow out region in described photoresistance district is the figure of described N-type light dope ion implanted region.
3. monitoring structure according to claim 2, is characterized in that, the shape of the outline in described photoresistance district and the profile in described hollow out region is identical and have an identical geometric center; The figure in described photoresistance district comprises described outline and along described geometric center, described hollow out region is rotated to the figure obtaining.
4. monitoring structure according to claim 1, is characterized in that, the N-type trap in described monitoring structure is some parallel row equidistantly arranges, and described grid is some parallel row and equidistantly arranges; And the orthogonal thereto distribution of row at the row at described grid place and described N-type trap place;
In described photoresistance district, in the N-type trap between described grid, be provided with P type light dope ion trap; In described N-type light dope ion implanted region, in the N-type trap between described grid, be provided with N-type light dope ion trap.
5. monitoring structure according to claim 1, is characterized in that, in the straight line that each outline line of described photoresistance district all can form at adjacent two described contact holes, finds parallel with it straight line.
6. a method for supervising for N-type light dope Implantation Aligning degree, is characterized in that, comprises preparation and two processes of electron beam scanning of monitoring structure, wherein,
The preparation of described monitoring structure comprises:
Step S01: the nonfunctional area of a Semiconductor substrate is provided, and N-type light dope ion implanted region and photoresistance district are set in described nonfunctional area;
Step S02: carry out successively the preparation of N-type trap and grid in described nonfunctional area;
Step S03: cover one deck N-type light dope Implantation photoresistance in described photoresistance district;
Step S04: carry out N-type light dope Implantation in the N-type trap of described N-type light dope ion implanted region, thereby form N-type light dope ion trap in this N-type trap;
Step S05: remove described N-type light dope Implantation photoresistance;
Step S06: adopt photoetching process to shelter from the region outside described photoresistance district, carry out P type light dope Implantation in the N-type trap in described photoresistance district, thereby form P type light dope ion trap in this N-type trap;
Step S07: form dielectric layer on surface, described nonfunctional area, form contact hole in described dielectric layer and above corresponding respectively to described N-type light dope ion trap and described P type light dope ion trap;
Described electron beam scanning process comprises:
Step S08: under negative potential scan pattern, adopt electron beam to scan described monitoring structure, obtain the virtual voltage contrast striograph of described test structure; Wherein, contact hole corresponding to described N-type trap-N-type light dope ion trap structure is shown as dark hole, and contact hole corresponding to described N-type trap-P type light dope ion trap structure is shown as bright hole;
Step S09: described monitoring structure is set at the normal voltage contrast striograph without in Aligning degree deviation situation; Wherein, contact hole corresponding to described N-type trap-N-type light dope ion trap structure is shown as dark hole, and contact hole corresponding to described N-type trap-P type light dope ion trap structure is shown as bright hole;
Step S10: described virtual voltage contrast striograph and described normal voltage contrast striograph are contrasted, find out the contact hole that brightness changes occurs: wherein, comprise in described N-type trap-N-type light dope ion trap structure and become in bright hole or described N-type trap-P type light dope ion trap structure and from bright hole, become the contact hole in dark hole from dark hole;
Step S11: the data of the described contact hole changing according to found out generation brightness obtain the Aligning degree deviation in described photoresistance district, that is to say described N-type light dope Implantation Aligning degree deviation.
7. method for supervising according to claim 6, it is characterized in that, described step S09 specifically comprises: Defect Scanning formula is set in electron beam scanning instrument, described in supposing to have one group at least in described photoresistance district and described N-type light dope ion implanted region, contact hole occurs extremely, then in conjunction with the type simulation of described monitoring structure, goes out the normal voltage contrast striograph of described monitoring structure.
8. method for supervising according to claim 6, is characterized in that, in described step S11, the data of the contact hole that described generation brightness changes comprise position data and incremental data.
9. method for supervising according to claim 6, is characterized in that, described photoresistance district in described N-type light dope ion implanted region around around setting; The regular polygon that is shaped as inner hollow out in described photoresistance district, the figure in the region of described hollow out is the figure of described N-type light dope ion implanted region.
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| CN107452639A (en) * | 2016-05-31 | 2017-12-08 | 中芯国际集成电路制造（天津）有限公司 | The method for detecting ion concentration |
| CN108010857A (en) * | 2016-11-01 | 2018-05-08 | 北大方正集团有限公司 | The method of inspection of ion implantation technology alignment quality |
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| US8531203B2 (en) * | 2010-06-11 | 2013-09-10 | International Business Machines Corporation | Mask alignment, rotation and bias monitor utilizing threshold voltage dependence |
| CN103021897B (en) * | 2012-11-12 | 2015-03-18 | 上海华力微电子有限公司 | Method for detecting semiconductor device electrical property failure |
| CN103346107A (en) * | 2013-06-27 | 2013-10-09 | 上海华力微电子有限公司 | Method for detecting alignment degree between polycrystalline silicon grid and contact hole |
| CN103489808B (en) * | 2013-09-22 | 2017-05-10 | 上海华力微电子有限公司 | Electron beam defect detection method capable of carrying out classification according to ion implantation areas |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107452639A (en) * | 2016-05-31 | 2017-12-08 | 中芯国际集成电路制造（天津）有限公司 | The method for detecting ion concentration |
| CN107452639B (en) * | 2016-05-31 | 2020-05-01 | 中芯国际集成电路制造（天津）有限公司 | Method for detecting ion concentration |
| CN108010857A (en) * | 2016-11-01 | 2018-05-08 | 北大方正集团有限公司 | The method of inspection of ion implantation technology alignment quality |
| CN108010857B (en) * | 2016-11-01 | 2020-12-29 | 北大方正集团有限公司 | Method for checking alignment quality of ion implantation process |
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