CN104078379A - Detection method for under-etching of through holes - Google Patents
Detection method for under-etching of through holes Download PDFInfo
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- CN104078379A CN104078379A CN201410357244.5A CN201410357244A CN104078379A CN 104078379 A CN104078379 A CN 104078379A CN 201410357244 A CN201410357244 A CN 201410357244A CN 104078379 A CN104078379 A CN 104078379A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
Abstract
The invention discloses a detection method for under-etching of through holes. The method comprises the following steps: a plurality of test modules are built on the substrate of a semiconductor, each test module simulates an SRAM device structure and comprises two simulation transmission gate transistors, two simulation pull-up transistors and two simulation pull-down transistors; the simulation transmission gate transistors, the simulation pull-up transistors and the simulation pull-down transistors are NMOS devices in a P trap, and a grid electrode is not formed in the active area of each simulation transmission gate transistor; a plurality of contact holes filled with metal are formed in each test module; the contact holes are connected with the position, corresponding to the grid electrode, of the active area of each simulation transmission gate transistor at least; metal interconnecting wires and conductive through holes are formed in the contact holes; test modules are scanned under the positive potential condition by an electron beam defect scanner, and the defect of under-etching of through holes of the test modules is detected according to image characteristic patterns obtained through scanning. The method provided by the invention can increase the capturing rate of the defect of under-etching.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly a kind of detection method of via etch deficiency.
Background technology
Along with development and the critical size of integrated circuit technology are scaled, in semiconductor device rear part processing procedure, the undercut of copper connecting through hole (as shown in Figure 1) and through hole disappearance defect more and more become one of bottleneck hindering integrated circuit development.Such as the hard mask of formerly etching (Hard Mask Etch) is again in the etch process processing procedure of etching vias (All in One Etch), undercut defect is often subject to the joint effect of cleaning and through hole etching itself and the etched photoetching process of through hole after hard mask etch, when wherein some process window is optimized not, defect just there will be, and becomes a large killer of restriction Yield lmproved.
To rear part through hole undercut defects detection, it is one of generally acknowledged difficult problem, the detection method of at present industry application is that applying electronic harness defects scanner checks after the cleaning after etching, but owing to there being the impact of Faraday cup, the effective quantity that high-aspect-ratio-Faraday cup can stop electronics in through hole to be overflowed, causes that the snatch rate of detection is lower and precision is not high.Another kind of detection method is after copper is filled planarization, to make electron beam Defect Scanning instrument to detect again.Fig. 2 a is depicted as the domain of the first metal layer M1, the first via layer Via1 and the second metal level M2, the complete SRAM device in dotted line frame of take is example, originally there are 3.5 copper connecting hole Via1, but transmission gate transistor (Pass Gate) polysilicon gate and not conducting of substrate due to SRAM device, in the image feature figure that contact hole on it obtains at electron beam Defect Scanning, be always dark, as the A place in Fig. 2 b, therefore cannot learn whether etching deficiency occurs.In addition, after copper is filled planarization, the through hole of mid portion is coupled together by copper cash, and as the B region in Fig. 2 b, the copper contact hole quantity that the not enough defect of via etch therefore finally can be detected is considerably less.
Therefore, all there is very large deficiency in the detection method of above-mentioned two kinds of via etch deficiencies, is difficult to online process window optimization effective reference is provided.
Summary of the invention
Main purpose of the present invention is intended to for the above-mentioned defect existing in prior art, and a kind of detection method with the via etch deficiency of high defects detection snatch rate is provided.
For reaching above-mentioned purpose, the invention provides a kind of detection method of via etch deficiency, comprise the following steps:
S1: set up a plurality of test modules in Semiconductor substrate, test module simulation SRAM device architecture described in each, it comprises two analog transmission gate transistors, two simulations pull up transistor and two simulation pull-down transistors, and wherein said analog transmission gate transistor, simulation pull up transistor and simulate pull-down transistor and be on nmos device in P trap and the transistorized active area of described analog transmission gate and do not form grid;
S2: form a plurality of contact holes on test module and fill metal described in each, described contact hole at least connects in the transistorized active area of described analog transmission gate the position corresponding to grid;
S3: form metal interconnecting wires and conductive through hole described in each on contact hole; And
S4: scan described test module and the image feature figure that obtains according to scanning detects the not enough defect of via etch of described test module by electron beam Defect Scanning instrument.
Preferably, step S3 further comprises:
S31: form successively the first metal layer, the first interlayer dielectric layer, the second interlayer dielectric layer and hard mask layer described in each on contact hole;
S32: described in chemical wet etching, described the second interlayer dielectric layer of hard mask layer and part forms a plurality of openings with the via regions corresponding to described test module;
S33: fill antireflection material to form a flat surfaces in described opening;
S34: antireflection material, described the first interlayer dielectric layer and described the second interlayer dielectric layer of part described in chemical wet etching, to form a through hole below opening described in each, the critical size of described through hole is less than described opening;
S35: the described hard mask layer of take connects described the first metal layer as etch mask continues to be etched to described via bottoms; And
S36: fill metal planarization in described opening and through hole.
Preferably, step S32 further comprises: on described hard mask layer, form successively Si oxide and anti-reflecting layer, the material of described anti-reflecting layer is identical with described antireflection material; On described anti-reflecting layer, apply the first photoresist layer, by exposure imaging, in described the first photoresist layer, define opening figure; Utilize described the first photoresist layer as hard mask layer described in hard mask etch light shield etching and described the second interlayer dielectric layer of part to form a plurality of described openings; And remove described the first photoresist layer.
Preferably, step S34 further comprises: on described anti-reflecting layer, apply the second photoresist layer, by exposure imaging, in the corresponding described antireflection material of described the second photoresist layer position, define via hole image, the critical size of described via hole image is less than described opening figure; Utilize described the second photoresist layer as antireflection material, the second interlayer dielectric layer and part the first interlayer dielectric layer described in through hole etching light shield etching to form a described through hole below opening described in each; And remove described the second photoresist layer, Si oxide and anti-reflecting layer.
Preferably, the center of described opening and the center superposition of described through hole.
Preferably, described contact hole includes source region contact hole, contact hole is shared in He Shan source, gate contact hole, and the transistorized gate contact of wherein said analog transmission gate hole is connected to the polysilicon gate region on its active area.
Preferably, step S1 comprises:
Step S11: the domain that designs test module described in each, wherein described in each the domain of test module comprise be isolated separate from a plurality of well regions, described simulation pulls up transistor and simulates and in the well region of pull-down transistor, includes source region and through the grid region of described active area, in the transistorized well region of described analog transmission gate, only include source region;
Step S12: well region described in each is carried out to P type Implantation, to form P trap;
Step S13: the grid that forms nmos pass transistor described in each on grid region; And
Step S14: N-type Implantation is carried out in active area described in each, to form the nmos device in described P trap.
Preferably, when described electron beam Defect Scanning instrument scans under positive potential condition, its landing energy adopting is 500～1300eV, and the electric current of employing is 20～110nA; When described electron beam Defect Scanning instrument scans under negative potential condition, its landing energy adopting is 1800～2500eV, and the electric current of employing is 20～110nA.
Preferably, the pixel that described electron beam Defect Scanning instrument adopts is 10nm-60nm.
The detection method of via etch deficiency proposed by the invention, by the gate contact hole of the transmission gate transistor of not conducting is originally designed to and substrate conducting, increase the number of openings that can be used in electron beam Defect Scanning after copper planarization, improved the snatch rate of defects detection.Further, the present invention more has the opening figure that critical size is larger than clear size of opening hard mask layer by usining etches through hole and metal connecting line figure as etch mask simultaneously, make copper fill and planarization after metal connecting line on each through hole be not all communicated with mutually, the etching deficiency of each through hole can be detected thus, further promoted monitoring sensitivity, for the optimization of process window provides data reference, and manufacture with Yield lmproved and provide safeguard for semiconductor is online.
Accompanying drawing explanation
Fig. 1 is the schematic diagram that is limited to the not enough defect of via etch in technology;
Fig. 2 a is the domain of SRAM device in prior art;
Fig. 2 b is the image feature figure that in prior art, electron beam scanning instrument scanning SRAM device obtains;
Fig. 3 is the flow chart of detection method of the via etch deficiency of one embodiment of the invention;
Fig. 4 is the schematic diagram of the test module of one embodiment of the invention;
Fig. 5 a～5g is the schematic diagram that one embodiment of the invention forms each step of conductive through hole and metal interconnecting wires;
The schematic diagram of the SRAM structure that Fig. 6 a and Fig. 6 b are prior art and test module of the present invention image feature figure under electron beam Defect Scanning instrument negative potential condition.
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art is also encompassed in protection scope of the present invention.
embodiment 1
The schematic flow sheet of the detection method of the via etch deficiency that Fig. 1 provides for the present embodiment.As shown in Figure 1, detection method comprises step:
Step S1: in Semiconductor substrate, set up a plurality of test modules, each test module simulation SRAM device architecture, wherein each transistor of test module is the nmos device in P trap, and does not form grid on the transistorized active area of analog transmission gate.
Concrete, due to a SRAM device architecture of each test module simulation, therefore each test module comprises 2 analog transmission gate transistors, two pull up transistor and two pull-down transistors, different from SRAM device architecture, these transistors in test module are the nmos device in P trap.In addition another difference of the present invention is that analog transmission gate transistor only has active area, and on active area, does not form grid.
The formation method of this test module is specific as follows:
First, design the domain of each test module, the domain of each test module comprise be isolated separate from a plurality of well regions, simulation pulls up transistor and simulates and in the well region of pull-down transistor, includes source region and through the grid region of active area, and only includes source region in the transistorized well region of analog transmission gate.Then, carry out well region N-type Implantation to form P trap, on each grid region, form grid polycrystalline silicon grid, and the step of active area N-type Implantation, thereby form, comprise transmission gate transistor, pull up transistor and a plurality of P trap nmos devices of pull-down transistor.Wherein test module is preferably based upon on the Cutting Road of wafer, does not take the position of effective chip unit on wafer, can not cause waste.When follow-up technique is cut wafer, test structure is destroyed.
Step S2: on each test module, form a plurality of contact holes and fill metal, wherein contact hole at least in the active area of connecting analog transmission gate transistor corresponding to the position of grid.
In this step, can first on test module, apply one deck dielectric layer, then through photoetching and etching, in dielectric layer, the vertical contact hole that forms is filled metal afterwards as tungsten in contact hole, adopts CMP technique to remove the metal of dielectric layer upper surface.It should be noted that contact hole is at least arranged in the transistorized active area of analog transmission gate corresponding to the position of grid.This be because, conventionally contact hole comprises Lou Shang active area, the source contact hole that is positioned at active area, contact hole is shared in the grid source that is positioned at the gate contact hole on grid and is positioned on grid and active area simultaneously, and for SRAM device, general gate contact hole is to be positioned on the grid of transmission gate transistor, even if therefore transmission gate transistor is designed to PMOS device, due to polysilicon gate all the time not with substrate conducting, the through hole that its top, gate contact hole forms image feature figure under the scanning of electron beam Defect Scanning instrument positive potential after filling metal and CMP is still dark all the time, also just cannot really detect the defect whether via etch etching deficiency occurs.And in the present invention, the grid of transmission gate transistor is omitted, make gate contact hole originally be directly connected to active area corresponding to the position of grid, thereby contact hole can with substrate conducting, when follow-up electron beam scanning, just can detect so the generation of the not enough defect of transmission gate transistor grid place via etch.And the formation position of other contact holes of test module is identical with the formation position in SRAM device contacts hole in prior art.
Step S3: form metal interconnecting wires and conductive through hole on each contact hole.
In this step, can adopt common process on contact hole, form metal interconnecting wires and with the supporting conductive through hole of metal interconnecting wires, concrete the first metal interconnecting wires M1, the first through hole Via1 and the second metal interconnecting wires of forming successively on contact hole.In the present embodiment, the second metal interconnecting wires is top-level metallic line.
Step S4: the not enough defect of via etch that detects test module by electron beam Defect Scanning instrument sweep test module the image feature figure that obtains according to scanning.
In this step, electron beam Defect Scanning instrument can be scanned under positive potential or negative potential condition.Take and work in negative potential condition as example, for NMOS pipe when electron beam Defect Scanning instrument is operated in positive potential condition, no matter the through hole of NMOS pipe is under normal circumstances or in the not enough situation of etching, the image feature figure of conductive through hole is all dark, cannot identify etching deficiency.When electron beam Defect Scanning instrument is operated in negative potential situation, the image feature figure of conductive through hole is dark under normal circumstances, if cause the contact hole conducting of conductive through hole Bu Yu lower floor but there is etching deficiency, the feature affects figure of conductive through hole is bright, also just can clearly tell the defect whether etching deficiency occurs.In addition, because all transistors of test module are all N-types, by electron beam Defect Scanning instrument, under positive potential condition, just can clearly detect whether etching defect occurs very fast, and can not cause obscuring of image feature figure because of transistor types difference.When electron beam Defect Scanning instrument is operated in negative potential condition lower time, need to open the ACC function of scanner, if the characteristic image figure obtaining is under normal circumstances bright, it is dark that the characteristic image figure that etching deficiency obtains occurs.
Preferably, when electron beam Defect Scanning instrument is worked under positive potential condition, positive potential landing energy is 500～1300eV, and the electric current of employing is 20～110nA, and the pixel of employing is 10～60nm.Positive potential landing energy 1800～2500eV when electron beam Defect Scanning instrument is worked under negative potential condition, the electric current of employing is 20～110nA, the pixel of employing is 10～60nm.
As known from the above, by being all fabricated to NMOS, the transistor in the test module of simulation SRAM device manages, the transistorized grid of analog transmission gate is removed and directly gate contact hole is connected on active area simultaneously, can increase the quantity of detectable through hole, be conducive to improve the snatch rate of the not enough defect of etching.
embodiment 2
Although above-described embodiment can increase the etching situation of the through hole (the A place in Fig. 2 b) of detection and the hole conducting of the transistorized gate contact of analog transmission gate, but for a plurality of through holes that connected by same metal interconnection line, as the B region in Fig. 2 b, if wherein some through hole exists etching deficiency, still cannot detect.Therefore,, for further increase can detect the quantity of through hole, the present embodiment is improved the formation method of through hole and metal interconnecting wires.
Please refer to Fig. 5 a to Fig. 5 g, it is depicted as the conductive through hole of the present embodiment and the schematic diagram of each step of metal interconnecting line forming method.In the present embodiment, set up test module, form a plurality of contact holes on each test module and fill the step of metal identical with the first embodiment, therefore not to repeat here.
Please refer to Fig. 5 a and Fig. 5 b, forming contact hole, filling after metal planarization, deposition one dielectric layer also forms the first metal interconnecting wires 501 being electrically connected to contact hole in this dielectric layer.Afterwards, on the first metal interconnecting wires 501, form successively barrier layer 502, the first interlayer dielectric layer 503, the second interlayer dielectric layers 504, hard mask layer 505.The second interlayer dielectric layer 504 of chemical wet etching hard mask layer 505 and part is to form a plurality of openings, and the position of these openings will form the region of through hole corresponding to test module.
Wherein, after forming hard mask layer, also can depositing silicon oxide 506 and anti-reflecting layer 507.The step of chemical wet etching hard mask layer 505 and part the second interlayer dielectric layer 504 is included in and on anti-reflecting layer 507, applies the first photoresist layer 508, by exposure imaging, in the first photoresist layer 508, define opening figure 509, then utilize patterned the first photoresist layer as hard mask etch light shield etching anti-reflecting layer 507, Si oxide 506, hard mask layer 505 and part the second interlayer dielectric layer 504.Etch step stops in the second inter-level dielectric, forms a plurality of openings.As shown in the figure, the critical size of these openings is CD1.
Please refer to Fig. 5 c, then remove the first photoresist layer, and in opening, fill antireflection material, to form smooth surface.Wherein, antireflection material can be identical with the material of anti-reflecting layer, forms thus the anti-reflecting layer 507 of one deck filling opening and surface smoothing.
Next, the second interlayer dielectric layer of chemical wet etching antireflection material, the first interlayer dielectric layer and part, to form a through hole below each opening, and the critical size of through hole is less than the critical size of opening.
Specifically, then please refer to Fig. 5 d, first on anti-reflecting layer 507, apply the second photoresist layer 510, by exposure imaging, in the second photoresist layer 510, define via hole image 511, the critical size of via hole image is CD2 as shown in the figure, and CD2 is less than the critical size CD1 of opening.Please refer to Fig. 5 e, then utilize patterned the second photoresist layer 510 as the first interlayer dielectric layer 503 of through hole etching light shield etching antireflection material, the second interlayer dielectric layer 504 and part.Etch step stops in the first interlayer dielectric layer 503, forms the through hole that a plurality of critical sizes are CD2.Remove afterwards described the second photoresist layer and anti-reflecting layer and be filled in the antireflection material in opening.Preferably, the center of via hole image 511 center and opening figure coincides.
Next, take hard mask layer 505 connects the first metal layer as etch mask continues to be etched to via bottoms.
As shown in Fig. 5 f, in mask layer 505, there is the opening figure that critical size is CD1, take this mask layer as etch mask continuation etching, the degree of depth of opening and through hole further increases, until barrier layer is carved to wear, makes via bottoms arrive the first metal interconnecting wires 501.In this step, need adjust OPC (Optical Proximity Correction, optics correction) to corresponding steps.
Finally, as shown in Fig. 5 g, after all etching completes, in the final opening forming and through hole, fill metal planarization, so far form conductive through hole 512 and the second metal interconnecting wires 513.
As known from the above, the present embodiment is by Twi-lithography etching, formation comprises the step-like etched hole of the opening that critical size is larger (being used to form the second metal interconnecting wires) and the through hole (being used to form conductive through hole) that below it, critical size is less, the hard mask of take again after chemical wet etching is for the first time that etch mask continues the degree of depth that etching increases opening and through hole, finally after metal filled and planarization, can make each conductive through hole independently be drawn by the second metal interconnecting wires above it, avoid the second metal interconnecting wires that a plurality of conductive through holes are coupled together.Thus, in the characteristic image figure finally obtaining, can clearly see that the light and shade of each conductive through hole changes, and then judge whether to occur etching deficiency.
Please refer to shown in Fig. 6 a and Fig. 6 b, no matter whether the characteristic image figure of the conductive through hole at the not enough A of etching, B place does not occur in prior art is all dark, the defect of etching deficiency is difficult to find from characteristic image figure, but utilize detection method of the present invention, the via etch deficiency at A, B place can find fast by characteristic image figure in the drawings, both avoided the impact of Faraday cup in detecting after etching, overcome simultaneously and after metal planarization, detected via count quantitative limitation, finally improved the snatch rate of defects detection.This provides data reference for process window optimization, for semiconductor is online, manufactures with Yield lmproved and provides safeguard.
Although the present invention discloses as above with preferred embodiment; so described many embodiment only give an example for convenience of explanation; not in order to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion with described in claims.
Claims (9)
1. a detection method for via etch deficiency, is characterized in that, comprises the following steps:
S1: set up a plurality of test modules in Semiconductor substrate, test module simulation SRAM device architecture described in each, it comprises two analog transmission gate transistors, two simulations pull up transistor and two simulation pull-down transistors, and wherein said analog transmission gate transistor, simulation pull up transistor and simulate pull-down transistor and be on nmos device in P trap and the transistorized active area of described analog transmission gate and do not form grid;
S2: form a plurality of contact holes on test module and fill metal described in each, described contact hole at least connects in the transistorized active area of described analog transmission gate the position corresponding to grid;
S3: form metal interconnecting wires and conductive through hole described in each on contact hole; And
S4: scan described test module and the image feature figure that obtains according to scanning detects the not enough defect of via etch of described test module by electron beam Defect Scanning instrument.
2. the detection method of via etch deficiency according to claim 1, is characterized in that, step S3 further comprises:
S31: form successively the first metal layer, the first interlayer dielectric layer, the second interlayer dielectric layer and hard mask layer described in each on contact hole;
S32: described in chemical wet etching, described the second interlayer dielectric layer of hard mask layer and part forms a plurality of openings with the via regions corresponding to described test module;
S33: fill antireflection material to form a flat surfaces in described opening;
S34: antireflection material, described the first interlayer dielectric layer and described the second interlayer dielectric layer of part described in chemical wet etching, to form a through hole below opening described in each, the critical size of described through hole is less than described opening;
S35: the described hard mask layer of take connects described the first metal layer as etch mask continues to be etched to described via bottoms; And
S36: fill metal planarization in described opening and through hole.
3. the detection method of via etch deficiency according to claim 2, is characterized in that, step S32 further comprises:
On described hard mask layer, form successively Si oxide and anti-reflecting layer, the material of described anti-reflecting layer is identical with described antireflection material;
On described anti-reflecting layer, apply the first photoresist layer, by exposure imaging, in described the first photoresist layer, define opening figure;
Utilize described the first photoresist layer as hard mask layer described in hard mask etch light shield etching and described the second interlayer dielectric layer of part to form a plurality of described openings; And
Remove described the first photoresist layer.
4. the detection method of via etch deficiency according to claim 1, is characterized in that, step S34 further comprises:
On described anti-reflecting layer, apply the second photoresist layer, by exposure imaging, in the corresponding described antireflection material of described the second photoresist layer position, define via hole image, the critical size of described via hole image is less than described opening figure;
Utilize described the second photoresist layer as antireflection material, the second interlayer dielectric layer and part the first interlayer dielectric layer described in through hole etching light shield etching to form a described through hole below opening described in each; And
Remove described the second photoresist layer, Si oxide and anti-reflecting layer.
5. the detection method of via etch deficiency according to claim 2, is characterized in that, the center of described opening and the center superposition of described through hole.
6. the detection method of via etch deficiency according to claim 1, it is characterized in that, described contact hole includes source region contact hole, contact hole is shared in He Shan source, gate contact hole, and the transistorized gate contact of wherein said analog transmission gate hole is connected to the polysilicon gate region on its active area.
7. the detection method of via etch deficiency according to claim 1, is characterized in that, step S1 comprises:
Step S11: the domain that designs test module described in each, wherein described in each the domain of test module comprise be isolated separate from a plurality of well regions, described simulation pulls up transistor and simulates and in the well region of pull-down transistor, includes source region and through the grid region of described active area, in the transistorized well region of described analog transmission gate, only include source region;
Step S12: well region described in each is carried out to P type Implantation, to form P trap;
Step S13: the grid that forms nmos pass transistor described in each on grid region; And
Step S14: N-type Implantation is carried out in active area described in each, to form the nmos device in described P trap.
8. the detection method of via etch deficiency according to claim 1, is characterized in that, when described electron beam Defect Scanning instrument scans under positive potential condition, its landing energy adopting is 500～1300eV, and the electric current of employing is 20～110nA; When described electron beam Defect Scanning instrument scans under negative potential condition, its landing energy adopting is 1800～2500eV, and the electric current of employing is 20～110nA.
9. the detection method of via etch deficiency according to claim 1, is characterized in that, the pixel that described electron beam Defect Scanning instrument adopts is 10～60nm.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106206354A (en) * | 2016-08-30 | 2016-12-07 | 上海华力微电子有限公司 | The method of detection first floor metal etch deficiency defect |
| CN106298572A (en) * | 2016-09-06 | 2017-01-04 | 上海华力微电子有限公司 | A kind of method detecting the not enough defect of first floor metal derby etching connecting grid |
| CN107507787A (en) * | 2017-08-31 | 2017-12-22 | 长江存储科技有限责任公司 | A kind of detection method in raceway groove hole |
| CN110854092A (en) * | 2019-11-13 | 2020-02-28 | 上海华力集成电路制造有限公司 | Shared contact hole and etching defect detection method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102982847B (en) * | 2012-11-29 | 2017-07-25 | 上海集成电路研发中心有限公司 | A kind of test system and method for the parasitic parameter of SRAM |
| CN103367192B (en) * | 2013-07-09 | 2015-12-09 | 上海华力微电子有限公司 | Detect the method for through hole undercut and through hole disappearance defect |
| CN103645211B (en) * | 2013-11-29 | 2015-09-09 | 上海华力微电子有限公司 | The method of monitoring electron beam flaw scanner sensitivity |
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2014
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106206354A (en) * | 2016-08-30 | 2016-12-07 | 上海华力微电子有限公司 | The method of detection first floor metal etch deficiency defect |
| CN106298572A (en) * | 2016-09-06 | 2017-01-04 | 上海华力微电子有限公司 | A kind of method detecting the not enough defect of first floor metal derby etching connecting grid |
| CN107507787A (en) * | 2017-08-31 | 2017-12-22 | 长江存储科技有限责任公司 | A kind of detection method in raceway groove hole |
| CN110854092A (en) * | 2019-11-13 | 2020-02-28 | 上海华力集成电路制造有限公司 | Shared contact hole and etching defect detection method thereof |
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