CN104123923A - Display driving circuit and display driving method for liquid crystal display - Google Patents
Display driving circuit and display driving method for liquid crystal display Download PDFInfo
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- CN104123923A CN104123923A CN201410356258.5A CN201410356258A CN104123923A CN 104123923 A CN104123923 A CN 104123923A CN 201410356258 A CN201410356258 A CN 201410356258A CN 104123923 A CN104123923 A CN 104123923A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
Abstract
A display driving method for a liquid crystal display comprises providing a first clock signal and a second clock signal, wherein phases of the first clock signal and the second clock signal are opposite and the pulse width is half of a clock period; providing a first data signal to an odd number line matrix unit and a second data signal to an even number line unit according to image data, wherein the second data signal delays a half clock period relative to the first data signal; providing a scanning signal to a matrix unit of any odd number line matrix according to the first clock signal to enable the matrix unit to be started to be charged by the first data, wherein the pulse width of the scanning signal is two thirds of the clock period; providing a scanning signal for a next even number line matrix unit which is adjacent to the odd number line according to the second clock signal to enable the matric unit to be started and be charged by the second clock signal.
Description
[technical field]
The invention relates to a kind of lcd technology, particularly relevant for a kind of display driver circuit and display drive method thereof that promotes the charging ability of high-resolution liquid crystal display.
[background technology]
Along with constantly popularizing of flat-panel screens, the display performance of flat-panel screens has been proposed to very high requirement, no matter be active matrix organic light emitting diode display or Thin Film Transistor-LCD, all require higher resolution and refresh rate (sweep frequency).For now, the display that possesses 4K (general reference lateral resolution be about 4000 pixels) resolution and 120Hz sweep frequency has progressed into main flow consumption market.
Yet along with the demand of resolution with sweep frequency improves, thin film transistor (TFT) can make because sweep frequency is too high its duration of charging to pixel not enough, causes the charge rate of pixel to be subject to serious impact; The raising of sweep frequency simultaneously also can improve the inversion frequency of pixel voltage polarity, and the driving voltage polarity conversion of pixel is more frequent, and the power consumption of the data drive circuit that data line connects is also just larger.Because being subject to the electron mobility of amorphous silicon semiconductor and the characteristic limitations of aluminum metal impedance, traditional Thin Film Transistor-LCD cannot in charge efficiency, promote to some extent, new high mobility semiconductor material and low-resistance metal material are sought by Sui You manufacturer, for example, adopt low temperature polycrystalline silicon (LTPS) as the semiconductor material of thin film transistor (TFT).But because the application technology of new material is still not mature enough at present, therefore can't be widely applied in flat pannel display.
Also therefore,, when the application technology of new material is not yet tending towards improving at present, be still necessary to improve for existing display drive method of liquid crystal display or circuit, to solve the existing problem of prior art.
[summary of the invention]
Because the shortcoming of prior art, fundamental purpose of the present invention is to provide a kind of liquid crystal display display driver circuit, to improve the charging ability of pixel cell, realizes high-quality and low-power consumption demonstration image quality.
For reaching aforementioned object of the present invention, the invention provides a kind of liquid crystal display display driver circuit, described liquid crystal display display driver circuit comprises: a plurality of pixel cells, be arranged in array, wherein the pixel cell with a line is connected to same sweep trace; The pixel cell of same row is between two adjacent the first data lines and the second data line, and wherein the pixel cell of odd-numbered line connects described the first adjacent data line, and the pixel cell of even number line connects described the second adjacent data line; Time schedule controller, provides the first clock signal and the second clock signal of single spin-echo each other, and the pulse width of described the first clock signal and second clock signal was 1/2nd clock period; One scan driver, to the sweep trace of odd-numbered line, provide sweep signal to open the pixel cell of odd-numbered line in order according to described the first clock signal, and according to described second clock signal in order the sweep trace of dual numbers row provide identical sweep signal to open the pixel cell of even number line; The pulse width of wherein said sweep signal was 3/2nds clock period; An and data driver, the first data line this pixel column being connected according to the image data of each pixel column provides one first data-signal with the odd-numbered line pixel cell charging to opening, and providing one second data-signal of these first data-signal, 1/2nd clock period of delay relatively to charge with the even number line pixel cell to opening to the second data line of this pixel column connection, the pulse width of wherein said the first data-signal and the second data-signal was greater than for 1/2nd clock period.
In one embodiment of this invention, according to the rising edge of described the first clock signal, to provide described pulse width in order to the sweep trace of odd-numbered line be the sweep signal of 3/2nds clock period for described scanner driver; Described scanner driver and according to the rising edge of described second clock signal in order the sweep trace of dual numbers row described pulse width is provided is the sweep signal of 3/2nds clock period, make the pulse width of sweep signal of the sweep trace of the even number line that the pulse width of sweep signal of the sweep trace of arbitrary odd-numbered line is adjacent time of 2/3rds that overlaps each other.
In one embodiment of this invention, the pulse width of described the first clock signal and second clock signal is that the frame frequency of a liquid crystal display and the product of line frequency are reciprocal.
In one embodiment of this invention, described the first data-signal is contrary with the polarity of voltage of described the second data-signal.
In one embodiment of this invention, described the first data-signal and described the second data-signal are low level pulse, and dutycycle is greater than 90%.
The present invention separately provides a kind of display drive method of liquid crystal display, comprise the following steps: to provide the first clock signal and the second clock signal of single spin-echo each other, the pulse width of wherein said the first clock signal and second clock signal was 1/2nd clock period; In the pixel cell of a pixel column, according to the image data to should pixel column, provide a pulse width to be greater than the first data-signal of 1/2nd clock period to the pixel cell of odd-numbered line, and a pulse width be greater than 1/2nd clock period and relatively this first data-signal postpone the second data-signal of 1/2nd clock period to the pixel cell of even number line; According to described the first clock signal, to the pixel cell of arbitrary odd-numbered line, to provide a pulse width be the sweep signal of 3/2nds clock period, and the pixel cell that makes this odd-numbered line is opened and is subject to described the first data-signal charging; And providing described sweep signal according to the pixel cell of described second clock signal pair next even number line adjacent with the pixel cell of described odd-numbered line, the pixel cell that makes this even number line is opened and is subject to described the second data-signal and charges.
In one embodiment of this invention, in the pixel cell of a pixel column, the pixel cell of odd-numbered line connects one first data line to receive described the first data-signal, and the pixel cell of even number line connects the second data line of a correspondence to receive described the second data-signal.
The pulse width of the sweep signal of the sweep trace of the even number line that in one embodiment of this invention, the pulse width of the sweep signal of the sweep trace of arbitrary odd-numbered line is adjacent time of 2/3rds that overlaps each other.
In one embodiment of this invention, the pulse width of described the first clock signal and second clock signal is that the frame frequency of a liquid crystal display and the product of line frequency are reciprocal.
In one embodiment of this invention, described the first data-signal is contrary with the polarity of voltage of described the second data-signal; Described the first data-signal and described the second data-signal are low level pulse, and dutycycle is greater than 90%.
[accompanying drawing explanation]
Fig. 1 is the structural representation of liquid crystal display display driver circuit one preferred embodiment of the present invention.
Fig. 2 is liquid crystal display display driver circuit one preferred embodiment output scanning signal of the present invention and the sequential chart that drives signal.
Fig. 3 is data line D in prior art
1with sweep trace G
1～G
3output signal sequential chart.
Fig. 4 is the process flow diagram of a preferred embodiment of display drive method of liquid crystal display of the present invention.
[embodiment]
For allowing above-mentioned purpose of the present invention, feature and advantage become apparent, preferred embodiment of the present invention cited below particularly, and coordinate accompanying drawing, be described in detail below.Moreover, the direction term that the present invention mentions, such as " on ", D score, 'fornt', 'back', " left side ", " right side ", " interior ", " outward ", " side " etc., be only the direction with reference to annexed drawings.Therefore, the direction term of use is in order to illustrate and to understand the present invention, but not in order to limit the present invention.
Please refer to shown in Fig. 1, Fig. 1 is the structural representation of liquid crystal display display driver circuit one preferred embodiment of the present invention.Liquid crystal display display driver circuit of the present invention is mainly used in a Thin Film Transistor-LCD, particularly can make it be applicable to require the liquid crystal display of high resolving power and high refresh rate by promoting the charging ability of pixel cell.
As shown in Figure 1, described liquid crystal display display driver circuit mainly comprises multi-strip scanning line G
1, G
2～G
2N, many first data line D
1with many second data line D
2, a plurality of pixel cell P
1～P
2N, time schedule controller 10, one scan driver 20 and a data driver 30.
Described sweep trace G
1, G
2～G
2Nparallel to each other and along line direction horizontal-extending.
Described the first data line D
1with described the second data line D
2alternately be arranged in parallel, and along column direction (longitudinal) vertically extend and with described sweep trace G
1, G
2～G
2Nmutually insulated is staggered.
Described pixel cell P
1～P
2Nbe arranged in array, be wherein positioned at same row (longitudinal's) pixel cell P
1～P
2Nbe called pixel column.As shown in Figure 1, for example, with the pixel cell of a line (P
1) be connected to same sweep trace (G for example
1); The pixel cell P of same row
1～P
2Nbe positioned at two the first adjacent data line D
1with the second data line D
2between, wherein it should be noted that the pixel cell of odd-numbered line connects described the first adjacent data line D
1, the pixel cell of even number line connects described the second adjacent data line D
2.For example, be positioned at the first data line D
1with the second data line D
2between pixel column in, the first data line D
1connect odd-numbered scan lines G
1, G
3..., G
2N-1the pixel cell P connecting
1, P
3..., P
2N-1; The second data line D
2connect even-line interlace line G
2, G
4..., G
2Nthe pixel cell P connecting
2, P
4..., P
2N.Compared to traditional liquid crystal display, first liquid crystal display display driver circuit of the present invention doubles the number of data line, and then the output frequency of each data line is reduced by half, to reduce power consumption.
Shown in Fig. 2, Fig. 2 is liquid crystal display display driver circuit one preferred embodiment output scanning signal of the present invention and the sequential chart that drives signal.Described time schedule controller 10 provides the first clock signal clk1 and the second clock signal clk2 of single spin-echo each other, it is T that described the first clock signal clk1 and second clock signal clk2 have a clock period, its pulse width is 1/2nd clock period (1/2T), that is dutycycle is 50%.In the present embodiment, the pulse width of described the first clock signal clk1 and second clock signal clk2 is the frame frequency of a liquid crystal display and the product of line frequency inverse preferably, for example the frame frequency when liquid crystal display is set as 120Hz, line frequency is set as 270KHz (vertical resolution is 2160 pixels), and the pulse width of described the first clock signal clk1 and second clock signal clk2 is about 0.03 microsecond.
Described scanner driver 20 connects described time schedule controller 10, and described the first clock signal clk1 of its foundation is the sweep trace G to odd-numbered line in order
1, G
3..., G
2N-1provide sweep signal to open the pixel cell P of odd-numbered line
1, P
3..., P
2N-1, and according to the described second clock signal clk2 sweep trace G of dual numbers row in order
2, G
4..., G
2Nprovide identical sweep signal to open the pixel cell P of even number line
2, P
4..., P
2N; Wherein as shown in Figure 2, the pulse width of described sweep signal is 3/2nds clock period (3/2T).In more detail, as shown in Figure 2, in the present embodiment, the rising edge of described the first clock signal clk1 of described scanner driver 20 foundation is the sweep trace G to odd-numbered line in order
1, G
3..., G
2N-1it is the sweep signal of 3/2nds clock period (3/2T) that described pulse width is provided; Simultaneously described scanner driver 20 is also according to the rising edge of the described second clock signal clk2 sweep trace G of dual numbers row in order
2, G
4..., G
2Nit is the sweep signal of 3/2nds clock period (3/2T) that described pulse width is provided, thus, the pulse width of sweep signal that can find out the sweep trace (for example G2) of the even number line that the pulse width of sweep signal of the sweep trace (for example G1) of arbitrary odd-numbered line is adjacent from sequential chart can overlap each other 2/3rds time that is an overlapping clock period (T).
Described data driver 30 connects described time schedule controller 10, the first data line D that it connects this pixel column according to the image data of each pixel column
1provide one first data-signal TP1 with the odd-numbered line pixel cell P to opening
1, P
3..., P
2N-1charging, and the second data line D that this pixel column is connected
2provide the one second data-signal TP2 that this first data-signal TP1 postpones 1/2nd clock period (1/2T) relatively, with the even number line pixel cell P to opening
2, P
4..., P
2Ncharging; Wherein in the present embodiment, the pulse width of described the first data-signal TP1 and the second data-signal TP2 is greater than 1/2nd clock period (1/2T).The image data of aforesaid each pixel column refers to first pixel cell P determining in one group of pixel column
1to 2N pixel cell P
2Nthe pixel voltage of inputting.For reaching the reversal of poles effect of a conversion, in the present embodiment, described the first data-signal TP1 is contrary with the polarity of voltage of described the second data-signal TP2, thus, and the odd-numbered line pixel cell P in same row
1, P
3..., P
2N-1the even number line pixel cell P being adjacent
2, P
4..., P
2Nthe polarity of the pixel voltage receiving just can be contrary.Moreover, in the present embodiment, described the first data-signal TP1 and described the second data-signal TP2 be low level pulse preferably, and dutycycle is greater than 90%, that is to say, described the first data-signal TP1 can overlapping 1/2nd time nearly with the pulse width that postpones described the second data-signal TP2 of 1/2nd clock period (1/2T).
As shown in Figure 2, the pulse width of the sweep signal of adjacent scanning lines time of 2/3rds that can overlap each other, and adjacent " odd-numbered line " sweep trace (G for example
1and G
3) the pulse width of sweep signal time of 1/3rd that can overlap each other, due to two adjacent odd-numbered line pixel cell P
1and P
3to connect same data line D
1and receive described the first data-signal TP1, according to the first clock signal clk1, second clock signal clk2, sweep trace G
1, sweep trace G
3sequential chart can find out, from trigger transmitting sweep trace G
3on the rising edge of the first clock signal clk1 of sweep signal to (that is t2 period) during this section between the rising edge of nearest second clock signal clk2, connect sweep trace G
1and G
3odd-numbered line as counting unit P
1and P
3in opening, data driver 30 is with the pixel cell P of the first row simultaneously
1the pixel cell P of corresponding pixel voltage to the first row
1carry out actual charging, simultaneously the pixel cell P of the same pixel voltage of data driver 30 to the third line
3carry out precharge.
In other words, concerning two adjacent odd-numbered line pixel cells, data driver 30 is carrying out in the process of actual charging last odd-numbered line pixel cell, can when remaining 1/3rd clock period (1/3T) in duration of charging, to next odd-numbered line pixel cell, carry out precharge.In like manner, concerning two adjacent even number line pixel cells, data driver 30 is carrying out in the process of actual charging last even number line pixel cell, can when remaining 1/3rd clock period (1/3T) in duration of charging, to next even number line pixel cell, carry out precharge.Because scanner driver 20 provides the sweep signal that pulse width is 3/2nds clock period (3/2T), the opening time that is to say each pixel cell is 3/2nds clock period (3/2T), and the duration of charging of each pixel cell will comprise the precharge period of 1/2nd clock period (1/2T) and the actual charging period of a clock period T.
Please refer to shown in Fig. 3, Fig. 3 is data line D in prior art
1with sweep trace G
1～G
3output signal sequential chart, wherein sweep trace is to provide in order the scanning signal of 1/1st clock period (1/2T) to give the corresponding pixel cell connecting, with on-pixel unit; Pixel voltage is by same data line D
1the scanning signal of corresponding each pixel cell offers the pixel cell of unlatching in corresponding sequential, the pixel cell that makes the to open show image that charged.Comparison diagram 2 and Fig. 3 can find out, display driver mode compared to Fig. 2, each pixel cell of display driver circuit of the present invention is except obtaining the duration of charging doubling, also further obtain the precharge time of 1/2nd clock period (1/2T), and then improved the charge rate of the pel array of liquid crystal panel.
In sum, shown in figure 4, the driving display packing of liquid crystal display of the present invention mainly comprises the following step:
100: it is the first clock signal and the second clock signal of 1/2nd clock period that single spin-echo and pulse width are provided; That is dutycycle is provided is the first clock signal of 50% and the second clock signal of single spin-echo with it;
101: the pixel cell of the first data-signal to odd-numbered line and the second data-signal pixel cell to even number line is provided; More specifically, in the pixel cell of a pixel column, according to the image data to should pixel column, provide a pulse width to be greater than the first data-signal of 1/2nd clock period to the pixel cell of odd-numbered line, and a pulse width be greater than 1/2nd clock period and relatively this first data-signal postpone the second data-signal of 1/2nd clock period to the pixel cell of even number line;
102: according to the first clock signal, to the pixel cell of odd-numbered line, providing pulse width is the sweep signal of 3/2nds clock period; In the present embodiment, this step be the rising edge according to described the first clock signal to the pixel cell of arbitrary odd-numbered line, to provide a pulse width be the sweep signal of 3/2nds clock period, the pixel cell that makes this odd-numbered line is opened and is subject to described the first data-signal charging; And
103: according to second clock signal, the pixel cell of next even number line is provided the sweep signal of same pulse width; In the present embodiment, this step is that the pixel cell according to rising edge pair next even number line adjacent with the pixel cell of described odd-numbered line of described second clock signal provides described sweep signal, and the pixel cell that makes this even number line is opened and is subject to described the second data-signal and charges.
As shown in the above description, the present invention sees through Double Data line to provide respectively the pixel voltage of opposed polarity to odd-numbered line pixel cell and even number line pixel cell, except reaching the effect of reversal of poles, also can reduce the output frequency of data line to lower power consumption; In addition, with respect to prior art the present invention, also provide the sweep time of three double-lengths, so that one period of precharge time of each pixel cell and the duration of charging doubling to be provided, and then improved the charge rate of pel array.Also therefore, the present invention goes for requiring higher resolution and the liquid crystal display of refresh rate.
The present invention is described by above-mentioned related embodiment, yet above-described embodiment is only for implementing example of the present invention.Must be pointed out that, published embodiment does not limit the scope of the invention.On the contrary, be contained in the spirit of claims and the modification of scope and impartial setting is included in scope of the present invention.
Claims (10)
1. a liquid crystal display display driver circuit, is characterized in that, comprising:
A plurality of pixel cells, are arranged in array, and wherein the pixel cell with a line is connected to same sweep trace; The pixel cell of same row is between two adjacent the first data lines and the second data line, and wherein the pixel cell of odd-numbered line connects described the first adjacent data line, and the pixel cell of even number line connects described the second adjacent data line;
Time schedule controller, provides the first clock signal and the second clock signal of single spin-echo each other, and the pulse width of described the first clock signal and second clock signal was 1/2nd clock period;
One scan driver, to the sweep trace of odd-numbered line, provide sweep signal to open the pixel cell of odd-numbered line in order according to described the first clock signal, and according to described second clock signal in order the sweep trace of dual numbers row provide identical sweep signal to open the pixel cell of even number line; The pulse width of wherein said sweep signal was 3/2nds clock period; And
One data driver, the first data line this pixel column being connected according to the image data of each pixel column provides one first data-signal with the odd-numbered line pixel cell charging to opening, and providing one second data-signal of these first data-signal, 1/2nd clock period of delay relatively to charge with the even number line pixel cell to opening to the second data line of this pixel column connection, the pulse width of wherein said the first data-signal and the second data-signal was greater than for 1/2nd clock period.
2. liquid crystal display display driver circuit as claimed in claim 1, is characterized in that: described scanner driver provides the sweep signal of described 3/2nds clock period of pulse width in order according to the rising edge of described the first clock signal to the sweep trace of odd-numbered line; Described scanner driver and according to the rising edge of described second clock signal in order the sweep trace of dual numbers row the sweep signals of described 3/2nds clock period of pulse width is provided, make the pulse width of sweep signal of the sweep trace of the even number line that the pulse width of sweep signal of the sweep trace of arbitrary odd-numbered line is adjacent time of 2/3rds that overlaps each other.
3. liquid crystal display display driver circuit as claimed in claim 2, is characterized in that: the pulse width of described the first clock signal and second clock signal is that the frame frequency of a liquid crystal display and the product of line frequency are reciprocal.
4. liquid crystal display display driver circuit as claimed in claim 1, is characterized in that: described the first data-signal is contrary with the polarity of voltage of described the second data-signal.
5. liquid crystal display display driver circuit as claimed in claim 1, is characterized in that: described the first data-signal and described the second data-signal are low level pulse, and dutycycle is greater than 90%.
6. a display drive method of liquid crystal display, is characterized in that: described display drive method comprises the following steps:
The first clock signal and the second clock signal of single spin-echo are each other provided, and the pulse width of wherein said the first clock signal and second clock signal was 1/2nd clock period;
In the pixel cell of a pixel column, according to the image data to should pixel column, provide a pulse width to be greater than the first data-signal of 1/2nd clock period to the pixel cell of odd-numbered line, and a pulse width be greater than 1/2nd clock period and relatively this first data-signal postpone the second data-signal of 1/2nd clock period to the pixel cell of even number line;
According to described the first clock signal, to the pixel cell of arbitrary odd-numbered line, to provide a pulse width be the sweep signal of 3/2nds clock period, and the pixel cell that makes this odd-numbered line is opened and is subject to described the first data-signal charging; And
Pixel cell according to described second clock signal pair next even number line adjacent with the pixel cell of described odd-numbered line provides described sweep signal, and the pixel cell that makes this even number line is opened and is subject to described the second data-signal and charges.
7. display drive method of liquid crystal display as claimed in claim 6, it is characterized in that: in the pixel cell of a pixel column, the pixel cell of odd-numbered line connects one first data line to receive described the first data-signal, and the pixel cell of even number line connects the second data line of a correspondence to receive described the second data-signal.
8. display drive method of liquid crystal display as claimed in claim 6, is characterized in that: the pulse width of the sweep signal of the sweep trace of the even number line that the pulse width of the sweep signal of the sweep trace of arbitrary odd-numbered line is adjacent time of 2/3rds that overlaps each other.
9. display drive method of liquid crystal display as claimed in claim 6, is characterized in that: the pulse width of described the first clock signal and second clock signal is that the frame frequency of a liquid crystal display and the product of line frequency are reciprocal.
10. display drive method of liquid crystal display as claimed in claim 6, is characterized in that: described the first data-signal is contrary with the polarity of voltage of described the second data-signal; Described the first data-signal and described the second data-signal are low level pulse, and dutycycle is greater than 90%.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410356258.5A CN104123923A (en) | 2014-07-24 | 2014-07-24 | Display driving circuit and display driving method for liquid crystal display |
| PCT/CN2014/084396 WO2016011684A1 (en) | 2014-07-24 | 2014-08-14 | Display driving circuit and display driving method for liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410356258.5A CN104123923A (en) | 2014-07-24 | 2014-07-24 | Display driving circuit and display driving method for liquid crystal display |
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|---|---|
| CN104123923A true CN104123923A (en) | 2014-10-29 |
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| CN201410356258.5A Pending CN104123923A (en) | 2014-07-24 | 2014-07-24 | Display driving circuit and display driving method for liquid crystal display |
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| WO (1) | WO2016011684A1 (en) |
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