WO2016011684A1 - Display driving circuit and display driving method for liquid crystal display - Google Patents
Display driving circuit and display driving method for liquid crystal display Download PDFInfo
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- WO2016011684A1 WO2016011684A1 PCT/CN2014/084396 CN2014084396W WO2016011684A1 WO 2016011684 A1 WO2016011684 A1 WO 2016011684A1 CN 2014084396 W CN2014084396 W CN 2014084396W WO 2016011684 A1 WO2016011684 A1 WO 2016011684A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
Definitions
- the scan driver sequentially supplies the scan signal having the pulse width of three-thirds of a clock period to the scan lines of the odd-numbered rows according to the rising edge of the first clock signal;
- the driver further supplies the scan signal having the pulse width of three-thirds of a clock period to the scan lines of the even-numbered rows in order according to the rising edge of the second clock signal, so that the pulse width of the scan signal of the scan line of any odd-numbered row
- the pulse widths of the scanning signals of the scanning lines of the even-numbered rows adjacent thereto overlap each other by two-thirds of the time.
- the voltages of the first data signal and the second data signal are opposite in polarity; the first data signal and the second data signal are low-level pulses, and the duty ratio is More than 90%.
- the liquid crystal display display driving circuit of the present invention improves the charging rate of the pixel array, and can be applied to a liquid crystal display requiring higher resolution and refresh rate, and can realize the beneficial effects of high quality and low power consumption display quality.
- FIG. 1 is a schematic view showing the structure of a display driving circuit of a liquid crystal display according to a preferred embodiment of the present invention.
- the image data of each of the pixel columns described above is a pixel voltage that is input from the first pixel unit P1 to the second N pixel unit P2N of one of the pixel columns.
- the voltage polarities of the first data signal TP1 and the second data signal TP2 are opposite, such that odd rows of pixels in the same column
- the polarities of the pixel voltages received by the cells P1, P3, ..., P2N-1 and their adjacent even-line pixel cells P2, P4, ..., P2N are reversed.
Abstract
A display driving method for a liquid crystal display comprises: providing a first clock signal (clk1) and a second clock signal (clk2) that have opposite phases and the pulse width being half of a clock period (1/2T); providing, according to image data, a first data signal (TP1) to odd-numbered lines of pixel units (P1, P3, …, P2N-1) and a second data signal (TP2) to even-numbered lines of pixel units (P2, P4, …, P2N), wherein the second data signal (TP2) delays half of the clock period (1/2T) relative to the first data signal (TP1); providing a scanning signal to any odd-numbered line of pixel units (P1, P3, …, P2N-1) according to the first clock signal (clk1) so that the pixel unit is started and charged by the first data signal (TP1), wherein the pulse width of the scanning signal is three-seconds of the clock period (3/2T); and providing, according to the second clock signal (clk2), the scanning signal to a next even-numbered line of pixel units (P2, P4, …, P2N) that is adjacent to the odd-numbered line of pixel units (P1, P3, …, P2N-1) so that the pixel unit is started and charged by the second data signal (TP2).
Description
本发明是有关于一种液晶显示技术,特别是有关于一种可提升高分辨率液晶显示器的充电能力的显示驱动电路及其显示驱动方法。The present invention relates to a liquid crystal display technology, and more particularly to a display driving circuit capable of improving the charging capability of a high resolution liquid crystal display and a display driving method thereof.
随着平面显示器的不断推广和普及,对平面显示器的显示性能提出了很高的要求,无论是有源矩阵有机发光二极管显示器或是薄膜晶体管液晶显示器,都要求更高的分辨率与刷新率(扫描频率)。就目前而言,具备4K(泛指横向分辨率约为4000像素)分辨率与120Hz扫描频率的显示器已逐渐进入主流消费市场。With the continuous popularization and popularization of flat panel displays, high requirements are placed on the display performance of flat panel displays. Both active matrix OLED displays and thin film transistor liquid crystal displays require higher resolution and refresh rate ( scanning frequency). For the time being, displays with 4K (probably horizontal resolution of about 4000 pixels) and 120Hz scanning frequency have gradually entered the mainstream consumer market.
然而,随着分辨率跟扫描频率的需求提高,薄膜晶体管会因为扫描频率过高而使其对像素的充电时间不足,导致像素的充电率受到严重的影响;同时扫描频率的提高也会提高像素电压极性的转换频率,像素的驱动电压极性转换越频繁,数据线连接的数据驱动电路的功率消耗也就越大。由于传统的薄膜晶体管液晶显示器受非晶硅半导体的电子迁移率和铝金属阻抗的特性限制而无法在充电效率上有所提升,遂有制造商寻求新的高迁移率半导体材料和低电阻金属材料,例如采用低温多晶硅(LTPS)作为薄膜晶体管的半导体材料。但是由于新材料的应用技术目前尚不够成熟,因此还不能被广泛应用到平板显示中。However, as the resolution and scanning frequency increase, the thin film transistor will have insufficient charging time for the pixel due to the high scanning frequency, which will cause the charging rate of the pixel to be seriously affected. At the same time, the scanning frequency will increase the pixel. The switching frequency of the voltage polarity, the more frequently the polarity of the driving voltage of the pixel is converted, and the greater the power consumption of the data driving circuit connected to the data line. Since the conventional thin film transistor liquid crystal display cannot be improved in charging efficiency due to the electron mobility of the amorphous silicon semiconductor and the characteristics of the aluminum metal impedance, some manufacturers have sought new high mobility semiconductor materials and low resistance metal materials. For example, low temperature polysilicon (LTPS) is used as a semiconductor material of a thin film transistor. However, since the application technology of new materials is not mature enough, it cannot be widely applied to flat panel displays.
也因此,在目前新材料的应用技术尚未趋于完善之际,仍有必要针对现有的液晶显示器显示驱动方法或电路进行改良,以解决现有技术所存在的问题。Therefore, when the application technology of the new material has not been perfected, it is still necessary to improve the existing liquid crystal display display driving method or circuit to solve the problems existing in the prior art.
有鉴于现有技术的缺点,本发明的主要目的在于提供一种液晶显示器显示驱动电路,以解决现有液晶显示器因高扫描频率而导致对像素的充电时间不足的技术问题。In view of the shortcomings of the prior art, the main object of the present invention is to provide a liquid crystal display display driving circuit to solve the technical problem that the current liquid crystal display has insufficient charging time for pixels due to high scanning frequency.
为达成本发明的前述目的,本发明提供一种液晶显示器显示驱动电路,所述液晶显示器显示驱动电路包括:多个像素单元,排列成阵列,其中同一行的像素单元连接至同一扫描线;同一列的像素单元位于两相邻的第一数据线和第二数据线之间,其中奇数行的像素单元连接所述相邻的第一数据线,偶数行的像素单元连接所述相邻的第二数据线;一时序控制器,提供彼此相位相反的第一时钟信号与第二时钟信号,所述第一时钟信号与第二时钟信号的脉冲宽度为二分之一时钟周期;一扫描驱动器,依据所述第一时钟信号按顺序对奇数行的扫描线提供扫描信号以打开奇数行的像素单元,并依据所述第二时钟信号按顺序对偶数行的扫描线提供相同的扫描信号以打开偶数行的像素单元;其中所述扫描信号的脉冲宽度为二分之三时钟周期;以及一数据驱动器,根据各像素列的影像数据对该像素列连接的第一数据线提供一第一数据信号以对打开的奇数行像素单元充电,并对该像素列连接的第二数据线提供相对该第一数据信号延迟二分之一时钟周期的一第二数据信号以对打开的偶数行像素单元充电,其中所述第一数据信号与第二数据信号的脉冲宽度大于二分之一时钟周期。In order to achieve the foregoing object of the present invention, the present invention provides a liquid crystal display display driving circuit, the liquid crystal display display driving circuit comprising: a plurality of pixel units arranged in an array, wherein pixel units of the same row are connected to the same scan line; a pixel unit of the column is located between two adjacent first data lines and a second data line, wherein pixel units of odd rows are connected to the adjacent first data lines, and pixel units of even rows are connected to the adjacent first a second data line; a timing controller, providing a first clock signal and a second clock signal opposite to each other, the first clock signal and the second clock signal having a pulse width of one-half clock cycle; a scan driver, And supplying scan signals to the scan lines of the odd rows in order to open the pixel units of the odd rows according to the first clock signal, and sequentially providing the same scan signals to the scan lines of the even rows according to the second clock signal to turn on the even numbers a pixel unit of the row; wherein the scan signal has a pulse width of three-thirds of a clock period; and a data driver, the root The image data of each pixel column provides a first data signal to the first data line connected to the pixel column to charge the opened odd-numbered pixel unit, and provides a second data line connected to the pixel column with respect to the first data signal. A second data signal delayed by one-half clock cycle to charge the open even-numbered row of pixel cells, wherein the first data signal and the second data signal have a pulse width greater than one-half of a clock cycle.
在本发明的一实施例中,所述扫描驱动器依据所述第一时钟信号的上升沿按顺序对奇数行的扫描线提供所述脉冲宽度为二分之三时钟周期的扫描信号;所述扫描驱动器并依据所述第二时钟信号的上升沿按顺序对偶数行的扫描线提供所述脉冲宽度为二分之三时钟周期的扫描信号,使得任一奇数行的扫描线的扫描信号的脉冲宽度与其相邻的偶数行的扫描线的扫描信号的脉冲宽度彼此重叠三分之二的时间。In an embodiment of the invention, the scan driver sequentially supplies the scan signal having the pulse width of three-thirds of a clock period to the scan lines of the odd-numbered rows according to the rising edge of the first clock signal; The driver further supplies the scan signal having the pulse width of three-thirds of a clock period to the scan lines of the even-numbered rows in order according to the rising edge of the second clock signal, so that the pulse width of the scan signal of the scan line of any odd-numbered row The pulse widths of the scanning signals of the scanning lines of the even-numbered rows adjacent thereto overlap each other by two-thirds of the time.
在本发明的一实施例中,所述第一时钟信号与第二时钟信号的脉冲宽度为一液晶显示器的帧频与行频的乘积倒数。In an embodiment of the invention, the pulse width of the first clock signal and the second clock signal is a reciprocal of the product of the frame rate and the line frequency of the liquid crystal display.
在本发明的一实施例中,所述第一数据信号与所述第二数据信号的电压极性相反。In an embodiment of the invention, the voltages of the first data signal and the second data signal are opposite in polarity.
在本发明的一实施例中,所述第一数据信号与所述第二数据信号为低电平脉冲,占空比大于90%。In an embodiment of the invention, the first data signal and the second data signal are low level pulses, and the duty ratio is greater than 90%.
本发明另提供一种液晶显示器显示驱动方法,包括下列步骤:提供彼此相位相反的第一时钟信号与第二时钟信号,其中所述第一时钟信号与第二时钟信号的脉冲宽度为二分之一时钟周期;在一像素列的像素单元中,根据对应该像素列的影像数据提供一脉冲宽度大于二分之一时钟周期的第一数据信号给奇数行的像素单元,以及一脉冲宽度大于二分之一时钟周期且相对该第一数据信号延迟二分之一时钟周期的第二数据信号给偶数行的像素单元;依据所述第一时钟信号对任一奇数行的像素单元提供一脉冲宽度为二分之三时钟周期的扫描信号,使该奇数行的像素单元开启而受到所述第一数据信号充电;以及依据所述第二时钟信号对与所述奇数行的像素单元相邻的下一偶数行的像素单元提供所述扫描信号,使该偶数行的像素单元开启而受到所述第二数据信号充电。The present invention further provides a liquid crystal display display driving method, comprising the steps of: providing a first clock signal and a second clock signal that are opposite in phase with each other, wherein a pulse width of the first clock signal and the second clock signal is two-half a clock period; in a pixel unit of a pixel column, providing a first data signal having a pulse width greater than one-half clock period to an odd-numbered pixel unit according to image data corresponding to the pixel column, and a pulse width greater than two And dividing a second data signal of one-half clock period with respect to the first data signal into pixel units of even rows; providing a pulse width to pixel units of any odd row according to the first clock signal a scanning signal of three-thirds of a clock period, causing the pixel unit of the odd-numbered row to be turned on to be charged by the first data signal; and adjacent to the pixel unit of the odd-numbered row according to the second clock signal An even number of rows of pixel units provide the scan signal such that the pixel units of the even row are turned on and subjected to the second data signal Electricity.
在本发明的一实施例中,在一像素列的像素单元中,奇数行的像素单元连接一第一数据线以接收所述第一数据信号,偶数行的像素单元连接一对应的第二数据线以接收所述第二数据信号。In an embodiment of the present invention, in a pixel unit of a pixel column, pixel units of odd rows are connected to a first data line to receive the first data signal, and pixel units of even rows are connected to a corresponding second data. A line to receive the second data signal.
在本发明的一实施例中,任一奇数行的扫描线的扫描信号的脉冲宽度与其相邻的偶数行的扫描线的扫描信号的脉冲宽度彼此重叠三分之二的时间。In an embodiment of the invention, the pulse width of the scan signal of the scan line of any odd row overlaps the pulse width of the scan signal of the scan line of the adjacent even row by two thirds of each other.
在本发明的一实施例中,所述第一时钟信号与第二时钟信号的脉冲宽度为一液晶显示器的帧频与行频的乘积倒数。In an embodiment of the invention, the pulse width of the first clock signal and the second clock signal is a reciprocal of the product of the frame rate and the line frequency of the liquid crystal display.
在本发明的一实施例中,所述第一数据信号与所述第二数据信号的电压极性相反;所述第一数据信号与所述第二数据信号为低电平脉冲,占空比大于90%。In an embodiment of the invention, the voltages of the first data signal and the second data signal are opposite in polarity; the first data signal and the second data signal are low-level pulses, and the duty ratio is More than 90%.
上述本发明的液晶显示器显示驱动电路提高了像素阵列的充电速率,可以适用于要求更高的分辨率与刷新率的液晶显示器,能够实现高品质与低功耗显示画质的有益效果。The liquid crystal display display driving circuit of the present invention improves the charging rate of the pixel array, and can be applied to a liquid crystal display requiring higher resolution and refresh rate, and can realize the beneficial effects of high quality and low power consumption display quality.
图1是本发明液晶显示器显示驱动电路一较佳实施例的结构示意图。1 is a schematic view showing the structure of a display driving circuit of a liquid crystal display according to a preferred embodiment of the present invention.
图2是本发明液晶显示器显示驱动电路一较佳实施例输出扫描信号与驱动信号的时序图。2 is a timing chart of outputting a scan signal and a drive signal in a preferred embodiment of the display driving circuit of the liquid crystal display of the present invention.
图3是现有技术中数据线D1与扫描线G1~G3的输出讯号时序图。3 is a timing diagram of output signals of the data line D1 and the scan lines G1 G G3 in the prior art.
图4是本发明液晶显示器显示驱动方法的一较佳实施例的流程图。4 is a flow chart of a preferred embodiment of a display driving method of a liquid crystal display according to the present invention.
为让本发明上述目的、特征及优点更明显易懂,下文特举本发明较佳实施例,并配合附图,作详细说明如下。再者,本发明所提到的方向用语,例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本发明,而非用以限制本发明。The above described objects, features, and advantages of the present invention will become more apparent from the aspects of the invention. Furthermore, the directional terms mentioned in the present invention, such as "upper", "lower", "before", "after", "left", "right", "inside", "outside", "side", etc. Just refer to the direction of the additional schema. Therefore, the directional terminology used is for the purpose of illustration and understanding of the invention.
请参考图1所示,图1是本发明液晶显示器显示驱动电路一较佳实施例的结构示意图。本发明的液晶显示器显示驱动电路主要用于一薄膜晶体管液晶显示器,特别是能通过提升像素单元的充电能力而使其适用于要求高分辨率与高刷新率的液晶显示器。Please refer to FIG. 1. FIG. 1 is a schematic structural view of a display driving circuit of a liquid crystal display according to a preferred embodiment of the present invention. The liquid crystal display display driving circuit of the invention is mainly used for a thin film transistor liquid crystal display, and particularly can be applied to a liquid crystal display requiring high resolution and high refresh rate by improving the charging capability of the pixel unit.
如图1所示,所述液晶显示器显示驱动电路主要包括多条扫描线G1、G2~G2N、多条第一数据线D1和多条第二数据线D2、多个像素单元P1~P2N、一时序控制器10、一扫描驱动器20以及一数据驱动器30。As shown in FIG. 1 , the liquid crystal display display driving circuit mainly includes a plurality of scan lines G1, G2 G G2N, a plurality of first data lines D1 and a plurality of second data lines D2, and a plurality of pixel units P1 PP2N, one. The timing controller 10, a scan driver 20, and a data driver 30.
所述扫描线G1、G2~G2N彼此平行且沿着行方向水平延伸。The scanning lines G1, G2 to G2N are parallel to each other and horizontally extend in the row direction.
所述第一数据线D1与所述第二数据线D2交替平行排列,并且沿着列方向(即纵向)垂直延伸而与所述扫描线G1、G2~G2N相互绝缘交错。The first data line D1 and the second data line D2 are alternately arranged in parallel, and extend vertically along the column direction (ie, the vertical direction) to be insulated from the scan lines G1, G2 G G2N.
所述像素单元P1~P2N排列成阵列,其中位于同一列(即纵向)的像素单元P1~P2N称为像素列。如图1所示,同一行的像素单元(例如P1)连接至同一扫描线(例如G1);同一列的像素单元P1~P2N则位于两相邻的第一数据线D1和第二数据线D2之间,其中值得注意的是,奇数行的像素单元连接所述相邻的第一数据线D1,偶数行的像素单元连接所述相邻的第二数据线D2。例如,在位于第一数据线D1和第二数据线D2之间的像素列中,第一数据线D1连接奇数扫描线G1、G3、...、G2N-1所连接的像素单元P1、P3、...、P2N-1;第二数据线D2连接偶数扫描线G2、G4、...、G2N所连接的像素单元P2、P4、...、P2N。相较于传统的液晶显示器,本发明液晶显示器显示驱动电路首先将数据线的数目增加一倍,进而将每个数据线的输出频率得以减半,以降低功耗。The pixel units P1 to P2N are arranged in an array, and the pixel units P1 to P2N located in the same column (ie, the vertical direction) are referred to as pixel columns. As shown in FIG. 1, pixel units (for example, P1) of the same row are connected to the same scan line (for example, G1); and pixel units P1 to P2N of the same column are located at two adjacent first data lines D1 and second data lines D2. Between these, it is worth noting that the pixel units of the odd rows are connected to the adjacent first data lines D1, and the pixel units of the even rows are connected to the adjacent second data lines D2. For example, in the pixel column located between the first data line D1 and the second data line D2, the first data line D1 is connected to the pixel units P1 and P3 connected to the odd scan lines G1, G3, . . . , G2N-1. The second data line D2 is connected to the pixel units P2, P4, ..., P2N to which the even scan lines G2, G4, ..., G2N are connected. Compared with the conventional liquid crystal display, the liquid crystal display display driving circuit of the present invention first doubles the number of data lines, thereby halving the output frequency of each data line to reduce power consumption.
请进一步参考图2所示,图2是本发明液晶显示器显示驱动电路一较佳实施例输出扫描信号与驱动信号的时序图。所述时序控制器10提供彼此相位相反的第一时钟信号clk1与第二时钟信号clk2,所述第一时钟信号clk1与第二时钟信号clk2具有一时钟周期为T,其脉冲宽度为二分之一时钟周期(1/2T),亦即占空比为50%。在本实施例中,所述第一时钟信号clk1与第二时钟信号clk2的脉冲宽度优选是一液晶显示器的帧频与行频的乘积倒数,例如当液晶显示器的帧频设定为120Hz,行频设定为270KHz(垂直分辨率为2160像素),则所述第一时钟信号clk1与第二时钟信号clk2的脉冲宽度约为0.03微秒。Please refer to FIG. 2 further. FIG. 2 is a timing diagram of a scan signal and a driving signal outputted by a preferred embodiment of the liquid crystal display display driving circuit of the present invention. The timing controller 10 provides a first clock signal clk1 and a second clock signal clk2 that are opposite in phase with each other, and the first clock signal clk1 and the second clock signal clk2 have a clock period of T and a pulse width of two. One clock cycle (1/2T), that is, the duty cycle is 50%. In this embodiment, the pulse width of the first clock signal clk1 and the second clock signal clk2 is preferably a reciprocal of the product of the frame rate and the horizontal frequency of the liquid crystal display, for example, when the frame rate of the liquid crystal display is set to 120 Hz, The frequency is set to 270 kHz (the vertical resolution is 2160 pixels), and the pulse width of the first clock signal clk1 and the second clock signal clk2 is about 0.03 microseconds.
所述扫描驱动器20连接所述时序控制器10,其依据所述第一时钟信号clk1按顺序对奇数行的扫描线G1、G3、...、G2N-1提供扫描信号以打开奇数行的像素单元P1、P3、...、P2N-1,并依据所述第二时钟信号clk2按顺序对偶数行的扫描线G2、G4、...、G2N提供相同的扫描信号以打开偶数行的像素单元P2、P4、...、P2N;其中如图2所示,所述扫描信号的脉冲宽度为二分之三时钟周期(3/2T)。更详细来说,如图2所示,在本实施例中,所述扫描驱动器20依据所述第一时钟信号clk1的上升沿按顺序对奇数行的扫描线G1、G3、...、G2N-1提供所述脉冲宽度为二分之三时钟周期(3/2T)的扫描信号;同时所述扫描驱动器20也依据所述第二时钟信号clk2的上升沿按顺序对偶数行的扫描线G2、G4、...、G2N提供所述脉冲宽度为二分之三时钟周期(3/2T)的扫描信号,如此一来,从时序图可看出任一奇数行的扫描线(例如G1)的扫描信号的脉冲宽度与其相邻的偶数行的扫描线(例如G2)的扫描信号的脉冲宽度会彼此重叠三分之二的时间,亦即重叠一个时钟周期(T)。The scan driver 20 is connected to the timing controller 10, which sequentially supplies scan signals of odd-row scan lines G1, G3, . . . , G2N-1 according to the first clock signal clk1 to open pixels of odd rows. Units P1, P3, ..., P2N-1, and sequentially providing the same scan signal to the even-numbered rows of scan lines G2, G4, ..., G2N in accordance with the second clock signal clk2 to turn on even-numbered rows of pixels The cells P2, P4, ..., P2N; wherein, as shown in Fig. 2, the pulse width of the scan signal is three-thirds of a clock cycle (3/2T). In more detail, as shown in FIG. 2, in the embodiment, the scan driver 20 sequentially scans the odd-numbered rows of scan lines G1, G3, ..., G2N according to the rising edge of the first clock signal clk1. -1 providing a scan signal having a pulse width of three-thirds of a clock period (3/2T); and the scan driver 20 also sequentially scanning the even-numbered rows of G2 in accordance with the rising edge of the second clock signal clk2 , G4, ..., G2N provide the scan signal with a pulse width of three-thirds of a clock period (3/2T), so that any odd-numbered scan lines (for example, G1) can be seen from the timing diagram. The pulse width of the scan signal and the pulse width of the scan signal of the adjacent even-line scan lines (for example, G2) overlap each other by two-thirds of the time, that is, one clock period (T).
所述数据驱动器30连接所述时序控制器10,其根据各像素列的影像数据对该像素列连接的第一数据线D1提供一第一数据信号TP1以对打开的奇数行像素单元P1、P3、...、P2N-1充电,并对该像素列连接的第二数据线D2提供相对该第一数据信号TP1延迟二分之一时钟周期(1/2T)的一第二数据信号TP2,以对打开的偶数行像素单元P2、P4、...、P2N充电;其中在本实施例中,所述第一数据信号TP1与第二数据信号TP2的脉冲宽度大于二分之一时钟周期(1/2T)。前述的各像素列的影像数据是指决定一组像素列中的第一个像素单元P1到第2N个像素单元P2N所输入的像素电压。为达到点转换的极性反转效果,本实施例中,所述第一数据信号TP1与所述第二数据信号TP2的电压极性是相反的,如此一来,同一列中的奇数行像素单元P1、P3、...、P2N-1与其相邻的偶数行像素单元P2、P4、...、P2N所接收的像素电压的极性便会相反。再者,在本实施例中,所述第一数据信号TP1与所述第二数据信号TP2优选是低电平脉冲,且占空比大于90%,也就是说,所述第一数据信号TP1与延迟二分之一时钟周期(1/2T)的所述第二数据信号TP2的脉冲宽度会重叠将近二分之一的时间。The data driver 30 is connected to the timing controller 10, and provides a first data signal TP1 to the first data line D1 connected to the pixel column according to the image data of each pixel column to open the odd-numbered pixel units P1 and P3. And charging P2N-1, and providing a second data signal TP2 delayed by one-half clock period (1/2T) relative to the first data signal TP1 to the second data line D2 connected to the pixel column, Charging the even-numbered row of pixel units P2, P4, . . . , P2N; wherein in the embodiment, the pulse widths of the first data signal TP1 and the second data signal TP2 are greater than one-half clock cycle ( 1/2T). The image data of each of the pixel columns described above is a pixel voltage that is input from the first pixel unit P1 to the second N pixel unit P2N of one of the pixel columns. In order to achieve the polarity inversion effect of the point conversion, in this embodiment, the voltage polarities of the first data signal TP1 and the second data signal TP2 are opposite, such that odd rows of pixels in the same column The polarities of the pixel voltages received by the cells P1, P3, ..., P2N-1 and their adjacent even-line pixel cells P2, P4, ..., P2N are reversed. Furthermore, in the embodiment, the first data signal TP1 and the second data signal TP2 are preferably low-level pulses, and the duty ratio is greater than 90%, that is, the first data signal TP1 The pulse width of the second data signal TP2 delayed by one-half clock period (1/2T) overlaps by approximately one-half of the time.
如图2所示,相邻扫描线的扫描信号的脉冲宽度会彼此重叠三分之二的时间,而相邻的“奇数行”扫描线(例如G1和G3)的扫描信号的脉冲宽度会彼此重叠三分之一的时间,由于两相邻的奇数行像素单元P1和P3是连接同一数据线D1而接收所述第一数据信号TP1,根据第一时钟信号clk1、第二时钟信号clk2、扫描线G1、扫描线G3的时序图可看出,从触发传送扫描线G3上的扫描信号的第一时钟信号clk1的上升沿到最近的第二时钟信号clk2的上升沿之间的这段期间(亦即t2时段),连接扫描线G1和G3的奇数行像数单元P1和P3同时处于开启状态,数据驱动器30以第一行的像素单元P1对应的像素电压对第一行的像素单元P1进行实际充电,同时数据驱动器30同样的像素电压对第三行的像素单元P3进行预充电。As shown in FIG. 2, the pulse widths of the scan signals of adjacent scan lines overlap each other by two-thirds of the time, and the pulse widths of the scan signals of adjacent "odd row" scan lines (eg, G1 and G3) are mutually Overlapping one-third of the time, since the two adjacent odd-line pixel units P1 and P3 are connected to the same data line D1, the first data signal TP1 is received, and is scanned according to the first clock signal clk1 and the second clock signal clk2. The timing chart of the line G1 and the scanning line G3 can be seen from the period between the rising edge of the first clock signal clk1 that triggers the scanning signal on the transmission scanning line G3 to the rising edge of the nearest second clock signal clk2 ( That is, the t2 period), the odd-line pixel units P1 and P3 connecting the scan lines G1 and G3 are simultaneously turned on, and the data driver 30 performs the pixel unit P1 of the first row with the pixel voltage corresponding to the pixel unit P1 of the first row. Actual charging, while the same pixel voltage of the data driver 30 precharges the pixel unit P3 of the third row.
换句话说,对两相邻的奇数行像素单元来说,数据驱动器30在对前一奇数行像素单元进行实际充电的过程中,会在充电时间剩下三分之一时钟周期(1/3T)时对下一奇数行像素单元进行预充电。同理,对两相邻的偶数行像素单元来说,数据驱动器30在对前一偶数行像素单元进行实际充电的过程中,会在充电时间剩下三分之一时钟周期(1/3T)时对下一偶数行像素单元进行预充电。由于扫描驱动器20提供的是脉冲宽度为二分之三时钟周期(3/2T)的扫描信号,也就是说每个像素单元的开启时间为二分之三时钟周期(3/2T),每个像素单元的充电时间将会包含二分之一时钟周期(1/2T)的预充电时段和一个时钟周期T的实际充电时段。In other words, for two adjacent odd-line pixel units, the data driver 30 will charge one-third of the clock period (1/3T) during the charging process for the actual charging of the previous odd-numbered row of pixel units. The next odd row of pixel cells is precharged. Similarly, for two adjacent even-numbered rows of pixel units, the data driver 30 will charge one-third of the clock period (1/3T) during the charging process for the actual charging of the previous even-numbered rows of pixel units. The next even row of pixel cells is precharged. Since the scan driver 20 provides a scan signal having a pulse width of three-thirds of a clock period (3/2T), that is, the turn-on time of each pixel unit is three-thirds of a clock period (3/2T), each The charging time of the pixel unit will include a pre-charging period of one-half clock period (1/2T) and an actual charging period of one clock period T.
请参考图3所示,图3是现有技术中数据线D1与扫描线G1~G3的输出讯号时序图,其中扫描线是按顺序提供一二分之一时钟周期(1/2T)的扫描讯号给对应连接的像素单元,以开启像素单元;像素电压则由同一数据线D1对应各像素单元的扫描讯号在对应的时序提供给开启的像素单元,使开启的像素单元得以充电显示影像。比较图2和图3可看出,相较于图2的显示驱动方式,本发明的显示驱动电路的每个像素单元除了可以获得加倍的充电时间外,还进一步获得二分之一时钟周期(1/2T)的预充电时间,进而提高了液晶面板的像素阵列的充电速率。Please refer to FIG. 3. FIG. 3 is a timing diagram of output signals of the data line D1 and the scan lines G1 G G3 in the prior art, wherein the scan lines are sequentially provided for one-half clock cycle (1/2T) scanning. The signal is sent to the corresponding connected pixel unit to turn on the pixel unit; the pixel voltage is supplied to the turned-on pixel unit by the scan signal corresponding to each pixel unit of the same data line D1 at the corresponding timing, so that the turned-on pixel unit can be charged to display the image. Comparing FIG. 2 and FIG. 3, it can be seen that, compared to the display driving mode of FIG. 2, each pixel unit of the display driving circuit of the present invention further obtains one-half clock cycle in addition to doubling the charging time ( The precharge time of 1/2T) further increases the charging rate of the pixel array of the liquid crystal panel.
综上所述,参考图4所示,本发明液晶显示器的驱动显示方法主要包含下列步骤:In summary, referring to FIG. 4, the driving display method of the liquid crystal display of the present invention mainly comprises the following steps:
100:提供相位相反且脉冲宽度为二分之一时钟周期的第一时钟信号与第二时钟信号;亦即提供占空比为50%的第一时钟信号和与之相位相反的第二时钟信号;100: providing a first clock signal and a second clock signal with opposite phases and a pulse width of one-half clock cycle; that is, providing a first clock signal with a duty ratio of 50% and a second clock signal having a phase opposite thereto ;
101:提供第一数据信号给奇数行的像素单元和第二数据信号给偶数行的像素单元;更详细而言,是在一像素列的像素单元中,根据对应该像素列的影像数据提供一脉冲宽度大于二分之一时钟周期的第一数据信号给奇数行的像素单元,以及一脉冲宽度大于二分之一时钟周期且相对该第一数据信号延迟二分之一时钟周期的第二数据信号给偶数行的像素单元;101: providing a first data signal to the pixel unit of the odd row and the second data signal to the pixel unit of the even row; in more detail, in the pixel unit of the pixel column, providing one image data corresponding to the pixel column a first data signal having a pulse width greater than one-half clock period to an odd-numbered row of pixel cells, and a second data having a pulse width greater than one-half clock cycle and delayed by one-half clock cycle relative to the first data signal Signaling to pixel units of even rows;
102:依据第一时钟信号对奇数行的像素单元提供脉冲宽度为二分之三时钟周期的扫描信号;在本实施例中,该步骤是依据所述第一时钟信号的上升沿对任一奇数行的像素单元提供一脉冲宽度为二分之三时钟周期的扫描信号,使该奇数行的像素单元开启而受到所述第一数据信号充电;以及Step 102: Supply, to the pixel unit of the odd row, a scan signal having a pulse width of three-thirds of a clock period according to the first clock signal; in this embodiment, the step is based on the rising edge of the first clock signal to any odd number The pixel unit of the row provides a scan signal having a pulse width of three-thirds of a clock period, causing the pixel unit of the odd-numbered row to be turned on to be charged by the first data signal;
103:依据第二时钟信号对下一偶数行的像素单元提供相同脉冲宽度的扫描信号;在本实施例中,该步骤是依据所述第二时钟信号的上升沿对与所述奇数行的像素单元相邻的下一偶数行的像素单元提供所述扫描信号,使该偶数行的像素单元开启而受到所述第二数据信号充电。103: The scan signal of the same pulse width is provided to the pixel unit of the next even row according to the second clock signal; in this embodiment, the step is based on the rising edge of the second clock signal and the pixel of the odd row. The pixel unit of the next even row adjacent to the cell provides the scan signal such that the pixel cell of the even row is turned on and charged by the second data signal.
由上述说明可知,本发明主要是透过双数据线来分别提供不同极性的像素电压给奇数行像素单元与偶数行像素单元,除了达到极性反转的效果之外,还可降低数据线的输出频率以减低功耗;此外,相对于现有技术本发明还提供三倍长的扫描时间,以提供每一像素单元一段预充电时间以及加倍的充电时间,进而提高了像素阵列的充电速率。也因此,本发明可以适用于要求更高的分辨率与刷新率的液晶显示器。As can be seen from the above description, the present invention mainly provides pixel voltages of different polarities to odd-numbered rows of pixel cells and even-numbered rows of pixel cells through double data lines, in addition to the effect of polarity inversion, the data lines can be reduced. The output frequency is reduced to reduce power consumption; in addition, the present invention provides three times longer scan time than the prior art to provide a precharge time per pixel unit and double the charging time, thereby increasing the charging rate of the pixel array. . Therefore, the present invention can be applied to a liquid crystal display requiring higher resolution and refresh rate.
本发明已由上述相关实施例加以描述,然而上述实施例仅为实施本发明的范例。必需指出的是,已公开的实施例并未限制本发明的范围。相反地,包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。The present invention has been described by the above related embodiments, but the above embodiments are merely examples for implementing the present invention. It must be noted that the disclosed embodiments do not limit the scope of the invention. Rather, modifications and equivalent arrangements are intended to be included within the scope of the invention.
Claims (10)
- 一种液晶显示器显示驱动电路,其包括:A liquid crystal display display driving circuit comprising:多个像素单元,排列成阵列,其中同一行的像素单元连接至同一扫描线;同一列的像素单元位于两相邻的第一数据线和第二数据线之间,其中奇数行的像素单元连接所述相邻的第一数据线,偶数行的像素单元连接所述相邻的第二数据线;a plurality of pixel units arranged in an array, wherein pixel units of the same row are connected to the same scan line; pixel units of the same column are located between two adjacent first data lines and second data lines, wherein pixel rows of odd rows are connected The adjacent first data line, the pixel unit of the even row is connected to the adjacent second data line;一时序控制器,提供彼此相位相反的第一时钟信号与第二时钟信号,所述第一时钟信号与第二时钟信号的脉冲宽度为二分之一时钟周期;a timing controller that provides a first clock signal and a second clock signal that are opposite in phase with each other, and a pulse width of the first clock signal and the second clock signal is one-half clock cycle;一扫描驱动器,依据所述第一时钟信号按顺序对奇数行的扫描线提供扫描信号以打开奇数行的像素单元,并依据所述第二时钟信号按顺序对偶数行的扫描线提供相同的扫描信号以打开偶数行的像素单元;其中所述扫描信号的脉冲宽度为二分之三时钟周期;以及a scan driver for sequentially supplying scan signals to odd-numbered rows of scan lines in accordance with the first clock signal to turn on odd-numbered rows of pixel cells, and sequentially providing the same scan for even-numbered rows of scan lines in accordance with the second clock signal Signaling to turn on pixel cells of even rows; wherein the scan signal has a pulse width of three-thirds of a clock cycle;一数据驱动器,根据各像素列的影像数据对该像素列连接的第一数据线提供一第一数据信号以对打开的奇数行像素单元充电,并对该像素列连接的第二数据线提供相对该第一数据信号延迟二分之一时钟周期的一第二数据信号以对打开的偶数行像素单元充电,其中所述第一数据信号与第二数据信号的脉冲宽度大于二分之一时钟周期。a data driver, configured to provide a first data signal to the first data line connected to the pixel column according to the image data of each pixel column to charge the opened odd-numbered pixel unit, and provide a relative data to the second data line connected to the pixel column The first data signal is delayed by a second data signal of one-half clock cycle to charge the open even-numbered row of pixel units, wherein the first data signal and the second data signal have a pulse width greater than one-half clock cycle .
- 如权利要求1所述的液晶显示器显示驱动电路,其中,所述扫描驱动器依据所述第一时钟信号的上升沿按顺序对奇数行的扫描线提供所述脉冲宽度二分之三时钟周期的扫描信号;所述扫描驱动器并依据所述第二时钟信号的上升沿按顺序对偶数行的扫描线提供所述脉冲宽度二分之三时钟周期的扫描信号,使得任一奇数行的扫描线的扫描信号的脉冲宽度与其相邻的偶数行的扫描线的扫描信号的脉冲宽度彼此重叠三分之二的时间。The liquid crystal display display driving circuit according to claim 1, wherein said scan driver supplies said pulse width three-thirds of a clock cycle to said scan lines of odd rows in order according to a rising edge of said first clock signal And the scan driver provides the scan signal of the pulse width of three-thirds of a clock period to the scan lines of the even-numbered rows in sequence according to the rising edge of the second clock signal, so that the scan lines of any odd-numbered rows are scanned. The pulse width of the signal overlaps with the pulse width of the scanning signal of the scanning line of the adjacent even-numbered rows by two-thirds of each other.
- 如权利要求2所述的液晶显示器显示驱动电路,其中,所述第一时钟信号与第二时钟信号的脉冲宽度为一液晶显示器的帧频与行频的乘积倒数。The liquid crystal display display driving circuit according to claim 2, wherein a pulse width of said first clock signal and said second clock signal is a reciprocal of a product of a frame rate and a horizontal frequency of a liquid crystal display.
- 如权利要求1所述的液晶显示器显示驱动电路,其中,所述第一数据信号与所述第二数据信号的电压极性相反。A liquid crystal display display driving circuit according to claim 1, wherein said first data signal and said second data signal have opposite voltage polarities.
- 如权利要求1所述的液晶显示器显示驱动电路,其中,所述第一数据信号与所述第二数据信号为低电平脉冲,占空比大于90%。The liquid crystal display display driving circuit according to claim 1, wherein the first data signal and the second data signal are low-level pulses, and the duty ratio is greater than 90%.
- 一种液晶显示器显示驱动方法,其包括下列步骤:A liquid crystal display display driving method includes the following steps:提供彼此相位相反的第一时钟信号与第二时钟信号,其中所述第一时钟信号与第二时钟信号的脉冲宽度为二分之一时钟周期;Providing a first clock signal and a second clock signal that are opposite in phase with each other, wherein a pulse width of the first clock signal and the second clock signal is one-half clock cycle;在一像素列的像素单元中,根据对应该像素列的影像数据提供一脉冲宽度大于二分之一时钟周期的第一数据信号给奇数行的像素单元,以及一脉冲宽度大于二分之一时钟周期且相对该第一数据信号延迟二分之一时钟周期的第二数据信号给偶数行的像素单元;In a pixel unit of a pixel column, a first data signal having a pulse width greater than one-half clock period is supplied to an odd-numbered pixel unit according to image data corresponding to the pixel column, and a pulse width greater than one-half clock And delaying, by the second data signal, one-half clock period from the first data signal to the pixel unit of the even-numbered row;依据所述第一时钟信号对任一奇数行的像素单元提供一脉冲宽度为二分之三时钟周期的扫描信号,使该奇数行的像素单元开启而受到所述第一数据信号充电;以及Providing, according to the first clock signal, a scan signal having a pulse width of three-thirds of a clock period to pixel units of any odd-numbered rows, causing the pixel units of the odd-numbered rows to be turned on to be charged by the first data signal;依据所述第二时钟信号对与所述奇数行的像素单元相邻的下一偶数行的像素单元提供所述扫描信号,使该偶数行的像素单元开启而受到所述第二数据信号充电。And supplying the scan signal to the pixel unit of the next even row adjacent to the pixel unit of the odd row according to the second clock signal, so that the pixel unit of the even row is turned on and charged by the second data signal.
- 如权利要求6所述的液晶显示器显示驱动方法,其中,在一像素列的像素单元中,奇数行的像素单元连接一第一数据线以接收所述第一数据信号,偶数行的像素单元连接一对应的第二数据线以接收所述第二数据信号。The liquid crystal display display driving method according to claim 6, wherein in the pixel unit of one pixel column, the odd-numbered rows of pixel units are connected to a first data line to receive the first data signal, and the even-numbered rows of pixel units are connected. a corresponding second data line to receive the second data signal.
- 如权利要求6所述的液晶显示器显示驱动方法,其中,任一奇数行的扫描线的扫描信号的脉冲宽度与其相邻的偶数行的扫描线的扫描信号的脉冲宽度彼此重叠三分之二的时间。The liquid crystal display display driving method according to claim 6, wherein a pulse width of a scan signal of any odd-numbered row of scan lines and a pulse width of a scan signal of an adjacent even-numbered row of scan lines overlap each other by two-thirds time.
- 如权利要求6所述的液晶显示器显示驱动方法,其中,所述第一时钟信号与第二时钟信号的脉冲宽度为一液晶显示器的帧频与行频的乘积倒数。The liquid crystal display display driving method according to claim 6, wherein a pulse width of the first clock signal and the second clock signal is a reciprocal of a product of a frame rate and a horizontal frequency of the liquid crystal display.
- 如权利要求6所述的液晶显示器显示驱动方法,其中,所述第一数据信号与所述第二数据信号的电压极性相反;所述第一数据信号与所述第二数据信号为低电平脉冲,占空比大于90%。 The liquid crystal display display driving method according to claim 6, wherein said first data signal and said second data signal have opposite voltage polarities; said first data signal and said second data signal are low voltage Flat pulse, duty cycle greater than 90%.
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