CN104112789B - Solar cell and manufacture method thereof - Google Patents
Solar cell and manufacture method thereof Download PDFInfo
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- CN104112789B CN104112789B CN201310133205.2A CN201310133205A CN104112789B CN 104112789 B CN104112789 B CN 104112789B CN 201310133205 A CN201310133205 A CN 201310133205A CN 104112789 B CN104112789 B CN 104112789B
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- 238000000034 method Methods 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 193
- 239000010410 layer Substances 0.000 claims abstract description 129
- 238000002161 passivation Methods 0.000 claims abstract description 48
- 230000002262 irrigation Effects 0.000 claims abstract description 33
- 238000003973 irrigation Methods 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000011241 protective layer Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 30
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 15
- 239000000377 silicon dioxide Substances 0.000 claims description 15
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 10
- 239000004411 aluminium Substances 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 238000010422 painting Methods 0.000 claims description 10
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 10
- 238000007747 plating Methods 0.000 claims description 10
- 229910052709 silver Inorganic materials 0.000 claims description 10
- 239000004332 silver Substances 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000001704 evaporation Methods 0.000 claims description 6
- 230000008020 evaporation Effects 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 239000010941 cobalt Substances 0.000 claims description 5
- 229910017052 cobalt Inorganic materials 0.000 claims description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 238000005868 electrolysis reaction Methods 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 10
- 150000004706 metal oxides Chemical class 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 7
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000002834 transmittance Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention provides a kind of solar cell and manufacture method thereof, wherein said manufacture method comprises the following steps: on the first surface of substrate, form protective layer; The second surface of substrate forms passivation layer; Form at least one first type semiconductor pattern and at least one Second-Type semiconductor pattern over the passivation layer, wherein the first type semiconductor pattern and Second-Type semiconductor pattern copline and adjacent to each other; Form irrigation canals and ditches at the intersection of the first type semiconductor pattern and Second-Type semiconductor pattern, be electrically insulated each other to make the first type semiconductor pattern and Second-Type semiconductor pattern; First type semiconductor pattern and Second-Type semiconductor pattern form Seed Layer, and the conductance of Seed Layer is greater than 9 × 10
5s/m; Form electrode layer on the seed layer.
Description
Technical field
The invention relates to semiconductor technology, and relate to a kind of solar cell and manufacture method thereof especially.
Background technology
In recent years, along with environmental consciousness come back and the whole world face energy crisis, fossil energy pollution with shortage etc. problem, how to develop energy-saving and environmental protection and the alternative energy source of sustainable use become each advanced country science and technology research and development primary goal.Among the scheme of numerous alternative energy source, the occupation rate of solar cell in renewable energy resources emerging market reaches more than 23%, and it is present stage topmost alternative energy source, is also the very promising energy technology of tool.
At present in various types of solar cell, be mainly the main flow of technology with silica-based solar cell.But, the development of current silica-based solar cell is still subject to the restriction of photoelectric conversion efficiency, wherein affect the rete of photoelectric conversion efficiency except anti-reflecting layer (anti-reflectionlayer) and passivation layer, the good corrupt of window layers (windowlayer) is also one of important key determining photoelectric conversion efficiency.
Fig. 1 is the schematic diagram of a kind of silica-based solar cell of prior art.Please refer to Fig. 1, silica-based solar cell 100 comprises silicon substrate 110, passivation layer 120a, 120b, the first type semiconductor layer 130, Second-Type semiconductor layer 140, window layers 150a, 150b and electrode 160a, 160b.First type semiconductor layer 130 and Second-Type semiconductor layer 140 are configured at the relative both sides of silicon substrate 110, and passivation layer 120a is configured between the first type semiconductor layer 130 and silicon substrate 110, and passivation layer 120b is configured between Second-Type semiconductor layer 140 and silicon substrate 110.Window layers 150a, 150b are covered on the first type semiconductor layer 130 and Second-Type semiconductor layer 140 respectively, and electrode 160a, 160b then lay respectively on window layers 150a, 150b.
Because window layers 150a is configured at the sensitive surface (namely towards extraneous light) of silica-based solar cell 100, therefore, under the considering of light transmittance, silica-based solar cell 100 is main using transparent metal oxide as the material of window layers 150a, wherein transparent metal oxide again with indium tin oxide (indiumtinoxide, ITO) for main flow.But indium expensive and indium tin oxide needs vacuum (vacuum) processing procedure, thus causes the increase of processing procedure cost and time, and reduces the competitiveness of product.In addition, in the deposition process of indium tin oxide, plasma in physical vapour deposition (PVD) (physicalvapordeposition) processing procedure easily damages the rete in silica-based solar cell 100, and then affects the element characteristic of silica-based solar cell 100.
Summary of the invention
The invention provides a kind of manufacture method of solar cell, it has relatively low processing procedure cost and time.
The invention provides a kind of solar cell, it has good element characteristic.
The manufacture method of a kind of solar cell of the present invention, comprises the following steps.The first surface of substrate forms protective layer; The second surface of substrate forms passivation layer; Form at least one first type semiconductor pattern and at least one Second-Type semiconductor pattern over the passivation layer, wherein the first type semiconductor pattern and Second-Type semiconductor pattern copline and adjacent to each other; Form irrigation canals and ditches at the intersection of the first type semiconductor pattern and Second-Type semiconductor pattern, be electrically insulated each other to make the first type semiconductor pattern and Second-Type semiconductor pattern; First type semiconductor pattern and Second-Type semiconductor pattern form Seed Layer, and the conductance of Seed Layer is greater than 9 × 10
5s/m; Form electrode layer on the seed layer.
In one embodiment of this invention, above-mentioned first surface is relative to second surface.
In one embodiment of this invention, above-mentioned before formation protective layer, also comprise and surface-texturing processing procedure is carried out to first surface.
In one embodiment of this invention, the material of above-mentioned protective layer comprise silicon nitride, silica and aluminium oxide wherein at least one.
In one embodiment of this invention; the method of above-mentioned formation protective layer comprises plasma enhanced chemical vapor deposition (PlasmaEnhancedChemicalVaporDeposition; PECVD), aumospheric pressure cvd (atmosphericpressurechemicalvapordeposition; or ald (atomiclayerdeposition, ALD) APCVD).
In one embodiment of this invention, the above-mentioned method forming the first type semiconductor pattern and Second-Type semiconductor pattern over the passivation layer comprises the following steps.First shade is set over the passivation layer, and the first shade exposes the first area of passivation layer; Form the first type semiconductor pattern on the first region; Second shade is set over the passivation layer, and the second shade covers the first type semiconductor pattern and exposes the second area beyond the first type semiconductor pattern; Form Second-Type semiconductor pattern on the second region.
In one embodiment of this invention, the first above-mentioned type semiconductor pattern and Second-Type semiconductor pattern one of them be N type semiconductor pattern, and the first type semiconductor pattern and Second-Type semiconductor pattern wherein another is P type semiconductor pattern.
In one embodiment of this invention, the manufacture method of above-mentioned irrigation canals and ditches comprise with laser drill or Wet-type etching remove the first type semiconductor pattern of the intersection being positioned at the first type semiconductor pattern and Second-Type semiconductor pattern and Second-Type semiconductor pattern wherein at least one, and irrigation canals and ditches expose the passivation layer of a part.
In one embodiment of this invention, above-mentioned irrigation canals and ditches were formed before Seed Layer and electrode layer, and the degree of depth of irrigation canals and ditches equals the thickness of the first type semiconductor pattern or Second-Type semiconductor pattern, and irrigation canals and ditches also expose a part of passivation layer.
In one embodiment of this invention, the method for above-mentioned formation Seed Layer or the method for formation electrode layer comprise screen painting or plating, and this Seed Layer and this electrode layer expose this passivation layer of this part.
In one embodiment of this invention, above-mentioned irrigation canals and ditches are formed after electrode layer, and the degree of depth of irrigation canals and ditches equals the summation of the thickness of the first type semiconductor pattern, Seed Layer and electrode layer, or equaling the summation of thickness of Second-Type semiconductor pattern, Seed Layer and electrode layer, irrigation canals and ditches also expose the passivation layer of a part.
In one embodiment of this invention, the method of above-mentioned formation Seed Layer comprises and being covered in all sidedly on the first type semiconductor pattern and Second-Type semiconductor pattern by the material of Seed Layer in the mode of screen painting, plating or hot evaporation, and the method forming electrode layer comprises and being covered in all sidedly in Seed Layer by the material of electrode layer in the mode of screen painting, plating, hot evaporation, electrolysis or chemical vapour deposition (CVD).
In one embodiment of this invention, the material of above-mentioned Seed Layer comprises nickel, titanium, silver, aluminium or cobalt.
In one embodiment of this invention, the thickness of above-mentioned Seed Layer is less than 20 nanometers.
In one embodiment of this invention, the material of above-mentioned electrode layer comprises silver, aluminium or copper.
A kind of solar cell of the present invention comprises substrate, protective layer, passivation layer, at least one first type semiconductor pattern, at least one Second-Type semiconductor pattern, Seed Layer and electrode layer; Substrate has relative first surface and second surface; Protective layer is configured on first surface; Passivation layer is configured on second surface; First type semiconductor pattern and Second-Type semiconductor pattern are configured on passivation layer, wherein the first type semiconductor pattern and Second-Type semiconductor pattern copline and be electrically insulated each other; Seed Layer is configured on the first type semiconductor pattern and Second-Type semiconductor pattern, and the conductance of Seed Layer is greater than 9 × 10
5s/m; Electrode layer is configured in Seed Layer.
In one embodiment of this invention, above-mentioned first surface is texturing (textured) surface.
In one embodiment of this invention, the material of above-mentioned protective layer comprise silicon nitride, silica and aluminium oxide wherein at least one.
In one embodiment of this invention, the first above-mentioned type semiconductor pattern and Second-Type semiconductor pattern one of them be N type semiconductor pattern, and the first type semiconductor pattern and Second-Type semiconductor pattern wherein another is P type semiconductor pattern.
In one embodiment of this invention, the passivation layer of an above-mentioned part is not covered by the first type semiconductor pattern and Second-Type semiconductor pattern, and the Seed Layer be positioned on the first type semiconductor pattern and Second-Type semiconductor pattern and electrode layer also expose the passivation layer of described part.
In one embodiment of this invention, the material of above-mentioned Seed Layer comprises nickel, titanium, silver, aluminium or cobalt.
In one embodiment of this invention, the thickness of above-mentioned Seed Layer is less than 20 nanometers.
In one embodiment of this invention, the material of above-mentioned electrode layer comprises silver, aluminium or copper.
Based on above-mentioned, the first type semiconductor pattern and Second-Type semiconductor pattern are configured at (namely back to the second surface of extraneous light) on the non-sensitive surface of substrate by the present invention jointly.Thus, except the electrode layer of shading can be produced on substrate non-sensitive surface on also can remove from form window layers on sensitive surface, and then effectively promote the light transmittance of sensitive surface.In addition, the present invention replaces with the relatively high Seed Layer of conductance the window layers that prior art take transparent metal oxide as material, therefore, except the photoelectric conversion efficiency that effectively can promote solar cell and activity coefficient (fillfactor), also can remove the making of indium tin oxide from, and then effectively reduce processing procedure cost and time, and other rete of damaging in solar cell because making transparent metal oxide can be avoided, and then solar cell of the present invention is made to have good element characteristic.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of a kind of silica-based solar cell of prior art;
Fig. 2 A to Fig. 2 I is the generalized section of the Making programme of solar cell according to one embodiment of the invention;
Fig. 3 A to Fig. 3 C is the generalized section of the Making programme of solar cell according to another embodiment of the present invention.
Description of reference numerals:
100: silica-based solar cell;
110: silicon substrate;
120a, 120b, 230: passivation layer;
130: the first type semiconductor layer;
140: Second-Type semiconductor layer;
150a, 150b: window layers;
160a, 160b: electrode;
200,300: solar cell;
210: substrate;
220: protective layer;
230: passivation layer;
240A: the first shade;
240B: the second shade;
250a, 250b: the first type semiconductor pattern;
260a, 260b: Second-Type semiconductor pattern;
270a, 270b: Seed Layer;
280a, 280b: electrode layer;
A1: first area;
A2: second area;
S1a, S1b: first surface;
S2: second surface;
D1, D2: the degree of depth;
T: thickness;
WA, WB: opening;
TC1, TC2: irrigation canals and ditches;
I1, I2: island structure;
S100, S200: plasma enhanced chemical vapor deposition processing procedure.
Embodiment
Fig. 2 A to Fig. 2 I is the generalized section of the Making programme of solar cell according to one embodiment of the invention.Please refer to Fig. 2 A, provide substrate 210, wherein substrate 210 has relative first surface S1a and second surface S2.First surface S1a is such as sensitive surface, that is to say, such as, towards extraneous light (not shown, sunlight) with the surface of absorb photons, and second surface S2 is such as non-sensitive surface, that is to say the surface back to extraneous light.The material of substrate 210 comprises silicon.For example, substrate 210 is such as P-type silicon substrate or N-type silicon substrate.
Please refer to Fig. 2 B, in order to improve the ability of absorb photons, and reduce the reflection of extraneous light, the present embodiment optionally carries out surface-texturing processing procedure to first surface S1a (i.e. sensitive surface), and form textured surfaces (i.e. textured first surface S1b), as shown in the hackly surface in Fig. 2 B.Surface-texturing processing procedure such as, but is not limited to, and uses potassium hydroxide (KOH) solution to carry out.
Please refer to Fig. 2 C, first surface S1b is formed protective layer 220.In the present embodiment; protective layer 220 can be have high energy gap to reduce the passivation layer of carrier in the probability of surface recombination; its material is such as amorphous silicon (amorphous-silicon), and is such as make with the method for plasma enhanced chemical vapor deposition.On the other hand; protective layer 220 also can be the anti-reflecting layer reducing ambient light line reflection; its material be such as silicon nitride, silica and aluminium oxide wherein at least one, and be such as make with the method for plasma enhanced chemical vapor deposition, aumospheric pressure cvd or ald.Thus, protective layer 220, except can be used as use (being such as used to avoid solar cell scratch or make moist) of protection solar cell, also can have minimizing carrier concurrently in the probability of surface recombination and/or the effect of reflection reducing extraneous light.
Please refer to Fig. 2 D, the second surface S2 of substrate 210 forms passivation layer 230.The material of passivation layer 230 is such as amorphous silicon, and passivation layer 230 is such as make with the method for plasma enhanced chemical vapor deposition.
Please refer to Fig. 2 E, passivation layer 230 arranges the first shade 240A, wherein the first shade 240A has the first area A1 that opening WA exposes passivation layer 230, and covers the region (i.e. second area A2) beyond the A1 of first area.
Then, first area A1 forms the first type semiconductor pattern 250a, wherein, the material of the first type semiconductor pattern 250a is such as amorphous silicon, and formation the first type semiconductor pattern 250a carries out plasma enhanced chemical vapor deposition processing procedure S100.
Please refer to Fig. 2 F, passivation layer 230 arranges the second shade 240B, wherein the second shade 240B covers the first area A1 at the first type semiconductor pattern 250a place, and the second shade 240B has opening WB exposes second area A2 beyond the first type semiconductor pattern 250a.
Then, second area A2 is formed Second-Type semiconductor pattern 260a, wherein, the material of Second-Type semiconductor pattern 260a is such as amorphous silicon, and the method forming Second-Type semiconductor pattern 260a comprises and carries out plasma enhanced chemical vapor deposition processing procedure S200.
First type semiconductor pattern 250a and Second-Type semiconductor pattern 260a copline and adjacent to each other.In addition, the first type semiconductor pattern 250a and Second-Type semiconductor pattern 260a one of them be N type semiconductor pattern, and the first type semiconductor pattern 250a and Second-Type semiconductor pattern 260a wherein another is P type semiconductor pattern.
It should be noted that herein, though the present embodiment is alternately arranged with each other to be provided as with 2 the first type semiconductor pattern 250a and 2 Second-Type semiconductor pattern 260a and illustrates, but the quantity of the first type semiconductor pattern 250a and Second-Type semiconductor pattern 260a or the relation that arranges are when being determined by practical application, and therefore the present invention is not limited to this.
Please refer to Fig. 2 G, form irrigation canals and ditches TC1 at the intersection (i.e. the intersection of first area A1 and second area A2) of the first type semiconductor pattern and Second-Type semiconductor pattern.In detail, the manufacture method of irrigation canals and ditches TC1 be such as with laser drill or Wet-type etching remove the first type semiconductor pattern 250a of the intersection being positioned at the first type semiconductor pattern 250a and Second-Type semiconductor pattern 260a and Second-Type semiconductor pattern 260a wherein at least one, and form the first type semiconductor pattern 250b separated from one another and Second-Type semiconductor pattern 260b, wherein irrigation canals and ditches TC1 exposes the passivation layer 230 of a part.In addition, after irrigation canals and ditches TC1 is formed, the first type semiconductor pattern 250b and Second-Type semiconductor pattern 260b is electrically insulated each other.
Furthermore, the degree of depth D1 of the irrigation canals and ditches TC1 of the present embodiment such as approximates the thickness T of the first type semiconductor pattern 250b or Second-Type semiconductor pattern 260b.That is to say, the degree of depth of the first type semiconductor pattern 250a that the present embodiment removes with laser drill or Wet-type etching and/or Second-Type semiconductor pattern 260a approximates both respective thickness.
Please refer to Fig. 2 H, the first type semiconductor pattern 250b and Second-Type semiconductor pattern 260 form Seed Layer 270a.In the present embodiment, Seed Layer 270a is such as the island conductive structure that multiple separated from one another and corresponding first type semiconductor pattern 250b and Second-Type semiconductor pattern 260b is arranged, and Seed Layer 270a also exposes the passivation layer 230 of the part that irrigation canals and ditches TC1 exposes.
In addition, the material of Seed Layer 270a is such as nickel, titanium, silver, aluminium, cobalt or it is laminated, and the method forming Seed Layer 270a can be screen painting or plating.In the present embodiment, the thickness of Seed Layer 270a is less than 20 nanometers, and conductance is greater than 9 × 10
5s/m, and conductance is preferably between 10
6to 10
8between S/m.
The present embodiment replaces prior art with the Seed Layer 270a that conductance is relatively high, and with transparent metal oxide, (conductance is less than 5 × 10
5s/m) be the window layers of material, therefore, the present embodiment is except the photoelectric conversion efficiency that can effectively promote solar cell and activity coefficient, also can remove the making of indium tin oxide from, and then effectively reduce processing procedure cost and time, and other rete of damaging in solar cell because making transparent metal oxide can be avoided, and then the solar cell of the present embodiment is made to have good element characteristic.
Please refer to Fig. 2 I, Seed Layer 270a is formed electrode layer 280a.At this, then tentatively complete the making of the solar cell 200 of the present embodiment.In the present embodiment, electrode layer 280a is such as the island conductive structure that multiple separated from one another and corresponding first type semiconductor pattern 250b and Second-Type semiconductor pattern 260b is arranged, and electrode layer 280a also exposes the passivation layer 230 of the part that irrigation canals and ditches TC1 exposes.
In addition, the material of electrode layer 280a such as silver, aluminium, copper or it is laminated, and the method forming electrode layer 280a can be screen painting or plating.
In the present embodiment, the first type semiconductor pattern 250b and Second-Type semiconductor pattern 260b is configured on the non-sensitive surface (namely back to the second surface S2 of extraneous light) of substrate 210 jointly.Therefore, the present embodiment is except being produced on the electrode layer 280a of shading on the non-sensitive surface (namely back to the second surface S2 of extraneous light) of substrate 210, also can remove from the upper window layers (being configured between substrate and the first type semiconductor pattern or between Second-Type semiconductor pattern) forming prior art of sensitive surface (i.e. first surface S1b), and then effectively promote the light transmittance of sensitive surface (i.e. first surface S1b).
In the aforementioned embodiment, irrigation canals and ditches TC1 (being electrically insulated in order to make the first type semiconductor pattern 250b and Second-Type semiconductor pattern 260b) was formed before Seed Layer 270a and electrode layer 280a, but the present invention is not as limit.
In another embodiment of the invention, irrigation canals and ditches also can be formed after electrode layer.Fig. 3 A to Fig. 3 C is the generalized section of the Making programme of solar cell according to another embodiment of the present invention.The solar cell 300 (with reference to Fig. 3 C) of the present embodiment has similar structure and similar Making programme (the leading portion Making programme of solar cell 300 can refer to Fig. 2 A to Fig. 2 F) to the solar cell 200 of Fig. 2 I.After both difference is in solar cell 300 in the present embodiment step at earlier figures 2F, first type semiconductor pattern 250a and Second-Type semiconductor pattern 260a are one after the other formed Seed Layer 270b (as shown in Figure 3A) and electrode layer 280b (as shown in Figure 3 B), but not makes irrigation canals and ditches TC1 (with reference to Fig. 2 G).
In addition, the present embodiment forms the method for Seed Layer 270b is be covered in all sidedly on the first type semiconductor pattern 250a and Second-Type semiconductor pattern 260a by the material of Seed Layer 270b in the mode of screen painting, plating or hot evaporation.In addition, the method forming electrode layer 280b is covered in all sidedly on Seed Layer 270b by the material of electrode layer 280b in the mode of screen painting, plating, hot evaporation, electrolysis or chemical vapour deposition (CVD).
After Seed Layer 270b and electrode layer 280b is formed, then just irrigation canals and ditches TC2 is formed at the intersection of the first type semiconductor pattern 250a and Second-Type semiconductor pattern 260a, to make the first type semiconductor pattern 250b and Second-Type semiconductor pattern 260b separated from one another and to be electrically insulated.
Due to before formation irrigation canals and ditches TC2, Seed Layer 270b and electrode layer 280b is covered on the first type semiconductor pattern 250a and Second-Type semiconductor pattern 260a all sidedly, therefore, the present embodiment removes the first type semiconductor pattern 250a and/or the Second-Type semiconductor pattern 260a of the intersection being positioned at the first type semiconductor pattern 250a and Second-Type semiconductor pattern 260a during with laser drill or Wet-type etching, together with time remove the Seed Layer 270b and electrode layer 280b that are located thereon, and form multiple Seed Layer 270a and the electrode layer 280a with island structure, wherein Seed Layer 270a and electrode layer 280a can have similar profile to the first type semiconductor pattern 250a or Second-Type semiconductor pattern 260a.
In addition, the island structure I1 be made up of the first type semiconductor pattern 250b, Seed Layer 270a and electrode layer 280a and the island structure I2 be made up of Second-Type semiconductor pattern 260b, Seed Layer 270a and electrode layer 280a can expose the passivation layer 230 of part.In other words, the degree of depth D2 of irrigation canals and ditches TC2 approximate the first type semiconductor pattern 250b, Seed Layer 270a and electrode layer 280a thickness summation (i.e. the thickness of island structure I1) or equal the summation (i.e. the thickness of island structure I2) of thickness of Second-Type semiconductor pattern 260b, Seed Layer 270a and electrode layer 280a.
With solar cell 200 similarly, the first type semiconductor pattern 250b and Second-Type semiconductor pattern 260b is configured at (namely back to the second surface S2 of extraneous light) on the non-sensitive surface of substrate 210 by the solar cell 300 of the present embodiment jointly.Thus, except the sensitive surface (namely towards the first surface S1b of extraneous light) can avoiding the electrode layer 280a of shading to be produced on substrate 210 is upper, also can remove the window layers forming prior art on sensitive surface from, and then effectively promote the light transmittance of sensitive surface.In addition, the solar cell 300 of the present embodiment also replaces with the Seed Layer 270a that conductance is relatively high the window layers that prior art take transparent metal oxide as material, therefore, except the photoelectric conversion efficiency that can effectively promote solar cell 300 and activity coefficient, also can remove the making of indium tin oxide from, and then effectively reduce processing procedure cost and time, and other rete of damaging in solar cell because making transparent metal oxide can be avoided, and then the solar cell 300 of the present embodiment is made to have good element characteristic.
In sum, the first type semiconductor pattern and Second-Type semiconductor pattern are configured at (namely back to the second surface of extraneous light) on the non-sensitive surface of substrate by the present invention jointly.Thus, except the electrode layer of shading can be produced on substrate non-sensitive surface on also can remove from form window layers on sensitive surface, and then effectively promote the light transmittance of sensitive surface.In addition, the present invention replaces with the relatively high Seed Layer of conductance the window layers that prior art take transparent metal oxide as material, therefore, except the photoelectric conversion efficiency that effectively can promote solar cell and activity coefficient (fillfactor), also can remove the making of indium tin oxide from, and then effectively reduce processing procedure cost and time, and other rete of damaging in solar cell because making transparent metal oxide can be avoided, and then solar cell of the present invention is made to have good element characteristic.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (23)
1. a manufacture method for solar cell, is characterized in that, comprising:
A first surface of a substrate forms a protective layer;
A second surface of this substrate forms a passivation layer;
This passivation layer forms at least one first type semiconductor pattern and at least one Second-Type semiconductor pattern, wherein this first type semiconductor pattern and this Second-Type semiconductor pattern copline and adjacent to each other;
Form irrigation canals and ditches at the intersection of this first type semiconductor pattern and this Second-Type semiconductor pattern, be electrically insulated each other to make this first type semiconductor pattern and this Second-Type semiconductor pattern;
This first type semiconductor pattern and this Second-Type semiconductor pattern form a Seed Layer, and the conductance of this Seed Layer is greater than 9 × 10
5s/m; And
This Seed Layer is formed an electrode layer.
2. the manufacture method of solar cell according to claim 1, is characterized in that, this first surface is relative to this second surface.
3. the manufacture method of solar cell according to claim 1, is characterized in that, before this protective layer of formation, also comprises:
One surface-texturing processing procedure is carried out to this first surface.
4. the manufacture method of solar cell according to claim 1, is characterized in that, the material of this protective layer comprise silicon nitride, silica and aluminium oxide wherein at least one.
5. the manufacture method of solar cell according to claim 1, is characterized in that, the method forming this protective layer comprises plasma enhanced chemical vapor deposition, aumospheric pressure cvd or ald.
6. the manufacture method of solar cell according to claim 1, is characterized in that, the method that this passivation layer is formed this first type semiconductor pattern and this Second-Type semiconductor pattern comprises:
This passivation layer arranges one first shade, and this first shade exposes a first area of this passivation layer;
This first area is formed this first type semiconductor pattern;
This passivation layer arranges one second shade, and this second shade covers this first type semiconductor pattern and exposes the second area beyond this first type semiconductor pattern; And
Form this Second-Type semiconductor pattern on the first region.
7. the manufacture method of solar cell according to claim 1, it is characterized in that, this the first type semiconductor pattern and this Second-Type semiconductor pattern one of them be N type semiconductor pattern, and this first type semiconductor pattern and this Second-Type semiconductor pattern wherein another is P type semiconductor pattern.
8. the manufacture method of solar cell according to claim 1, is characterized in that, the manufacture method of these irrigation canals and ditches comprises:
Remove with laser drill or Wet-type etching this first type semiconductor pattern of the intersection being positioned at this first type semiconductor pattern and this Second-Type semiconductor pattern and this Second-Type semiconductor pattern wherein at least one, and these irrigation canals and ditches expose this passivation layer of a part.
9. the manufacture method of solar cell according to claim 1, it is characterized in that, these irrigation canals and ditches were formed before this Seed Layer and this electrode layer, and the degree of depth of these irrigation canals and ditches equals the thickness of this first type semiconductor pattern or this Second-Type semiconductor pattern, these irrigation canals and ditches also expose this part of passivation layer.
10. the manufacture method of solar cell according to claim 9, is characterized in that, the method forming this Seed Layer or the method forming this electrode layer comprise screen painting or plating, and this Seed Layer and this electrode layer expose this passivation layer of this part.
The manufacture method of 11. solar cells according to claim 1, it is characterized in that, these irrigation canals and ditches are formed after this electrode layer, and the degree of depth of these irrigation canals and ditches equals the summation of the thickness of this first type semiconductor pattern, this Seed Layer and this electrode layer, or equaling the summation of thickness of this Second-Type semiconductor pattern, this Seed Layer and this electrode layer, these irrigation canals and ditches also expose this passivation layer of a part.
The manufacture method of 12. solar cells according to claim 11, it is characterized in that, the method forming this Seed Layer comprises and being covered in all sidedly on this first type semiconductor pattern and this Second-Type semiconductor pattern by the material of this Seed Layer in the mode of screen painting, plating or hot evaporation, and the method forming this electrode layer comprises and being covered in all sidedly in this Seed Layer by the material of this electrode layer in the mode of screen painting, plating, hot evaporation, electrolysis or chemical vapour deposition (CVD).
The manufacture method of 13. solar cells according to claim 1, is characterized in that, the material of this Seed Layer comprises nickel, titanium, silver, aluminium or cobalt.
The manufacture method of 14. solar cells according to claim 1, is characterized in that, the thickness of this Seed Layer is less than 20 nanometers.
The manufacture method of 15. solar cells according to claim 1, is characterized in that, the material of this electrode layer comprises silver, aluminium or copper.
16. 1 kinds of solar cells, is characterized in that, comprising:
One substrate, has a relative first surface and a second surface;
One protective layer, is configured on this first surface;
One passivation layer, is configured on this second surface;
At least one first type semiconductor pattern and at least one Second-Type semiconductor pattern are configured on this passivation layer, wherein this first type semiconductor pattern and this Second-Type semiconductor pattern copline and be electrically insulated each other;
One Seed Layer, be configured on this first type semiconductor pattern and this Second-Type semiconductor pattern, and the conductance of this Seed Layer is greater than 9 × 10
5s/m; And
One electrode layer, is configured in this Seed Layer.
17. solar cells according to claim 16, is characterized in that, this first surface is a textured first surface.
18. solar cells according to claim 16, is characterized in that, the material of this protective layer comprise silicon nitride, silica and aluminium oxide wherein at least one.
19. solar cells according to claim 16, it is characterized in that, this the first type semiconductor pattern and this Second-Type semiconductor pattern one of them be N type semiconductor pattern, and this first type semiconductor pattern and this Second-Type semiconductor pattern wherein another is P type semiconductor pattern.
20. solar cells according to claim 16, it is characterized in that, this passivation layer of a part is not covered by this first type semiconductor pattern and this Second-Type semiconductor pattern, and this Seed Layer be positioned on this first type semiconductor pattern and this Second-Type semiconductor pattern and this electrode layer also expose this passivation layer of this part.
21. solar cells according to claim 16, is characterized in that, the material of this Seed Layer comprises nickel, titanium, silver, aluminium or cobalt.
22. solar cells according to claim 16, is characterized in that, the thickness of this Seed Layer is less than 20 nanometers.
23. solar cells according to claim 16, is characterized in that, the material of this electrode layer comprises silver, aluminium or copper.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1538532A (en) * | 2003-04-17 | 2004-10-20 | 中国科学院微电子中心 | Low noise dipole photo-sensitive field effect transistor and its manufacturing method |
| CN1592972A (en) * | 2001-11-26 | 2005-03-09 | 壳牌阳光有限公司 | Manufacturing a solar cell with backside contacts |
| CN102369601A (en) * | 2009-03-30 | 2012-03-07 | 三洋电机株式会社 | Solar cell |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1592972A (en) * | 2001-11-26 | 2005-03-09 | 壳牌阳光有限公司 | Manufacturing a solar cell with backside contacts |
| CN1538532A (en) * | 2003-04-17 | 2004-10-20 | 中国科学院微电子中心 | Low noise dipole photo-sensitive field effect transistor and its manufacturing method |
| CN102369601A (en) * | 2009-03-30 | 2012-03-07 | 三洋电机株式会社 | Solar cell |
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