CN104112735B - High-kappa metal gate device metal resistor structure and fabrication method thereof - Google Patents
High-kappa metal gate device metal resistor structure and fabrication method thereof Download PDFInfo
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- CN104112735B CN104112735B CN201310136100.2A CN201310136100A CN104112735B CN 104112735 B CN104112735 B CN 104112735B CN 201310136100 A CN201310136100 A CN 201310136100A CN 104112735 B CN104112735 B CN 104112735B
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Abstract
The invention provides a high-kappa metal gate device metal resistor structure and a fabrication method thereof. The fabrication method comprises the following steps: 1) a doped polycrystalline silicon layer is deposited on the surface of a shallow trench isolation region of which the surface is provided with a high-kappa dielectric layer or a high-kappa dielectric layer /metal protective layer; 2) partial doped polycrystalline silicon is removed on two ends of the doped polycrystalline silicon layer, and then metal electrodes are formed on the two ends; 3) a metal layer is formed on surfaces of the doped polycrystalline silicon layer and the metal electrodes through the selective deposition process; 4) and an insulating layer is formed on the surface of the metal layer, and contact holes are fabricated in the insulating layer to be connected with the metal electrode and through hole electrodes are formed in the contact holes. According to the invention, by forming a layer of metal layer resistor on the surface of the doped polycrystalline silicon layer or forming a parallel resistor through the metal layer of the surface of the adopted polycrystalline silicon and the metal protective layer of the high-kappa dielectric layer, the overall resistance of the metal resistor structure can be greatly reduced, and by adjusting the material type and thickness of the added metal layer, the overall resistance is adjustable.
Description
Technical field
The present invention relates to a kind of semiconductor device structure and preparation method thereof, more particularly to a kind of high-k/metal gate device
Metallic resistance structure and preparation method thereof.
Background technology
According to international technology roadmap for semiconductors (international technology roadmap for
Semiconductor, ITRS), CMOS technology will enter 32nm technology nodes in 2009.However, CMOS logic device from
45nm to 32nm nodes it is scaled during but encounter many difficult problems.In order to brought across size reduction these
Obstacle, it is desirable to which state-of-the-art Technology is incorporated in manufacture course of products.According to existing development trend, may be introduced into
To the new technology application of 32nm nodes, it is related to following aspects：The elongation technology of immersion lithography, Enhanced mobility substrate
Technology, metal gate/high-dielectric-coefficient grid medium (metal/high-k, MHK) grid structure, ultra-shallow junctions (ultra-shallow
Junction, USJ) and other enhanced strain engineerings method, including stress kindred effect (stress proximity
Effect, SPT), dual stressed liner technology (dualstress liner, DSL), strain memory technique (stress
Memorization technique, SMT), the high-aspect-ratio technique of STI and PMD (high aspect ratio process,
HARP the embedded SiGe (pFET) and SiC of (selective epitaxial growth, SEG)), are grown using selective epitaxy
(nFET) in source and drain technology, middle-end (middle of line, MOL) and backend process (back-end of line, BEOL)
Metallization and ultra-low k dielectric (ultra low-k, ULK) are integrated etc..
In recent years, metal-insulator-metal type (MIM) electric capacity and metal resistor receive publicity, and it is in high speed circuit
Using especially prominent.
A kind of design of existing metallic resistance structure for high-k/metal gate technique is as shown in Figure 1.It includes a shallow ridges
Road isolation area 101；It is incorporated into shallow trench isolation regions surface high-k dielectric layer 103 and TiN layer 104；It is incorporated into the TiN layer
The doped polysilicon layer 108 on surface, positioned at the metal level 105 of the doped polysilicon layer both sides, and covers said structure
Insulating barrier 106, has contact hole in insulating barrier, the contact hole is filled with metal electrode 107.
In this type of design, the demand of device can not be met because relatively thin TiN layer increases can resistance, but, such as
Fruit increases the thickness of TiN layer in order to reduce resistance, and blocked up TiN layer can then affect the function and equipment performance of transistor.
Therefore it provides a kind of method that can improve metallic insulator performance is necessary.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of high-k/metal gate device metal
The manufacture method of electric resistance structure, to improve metallic insulator performance.
For achieving the above object and other related purposes, the present invention provides a kind of high-k/metal gate device metal electric resistance structure
Manufacture method, at least comprise the following steps：
1) there is the shallow trench isolation regions surface deposition doping of high-k dielectric layer or high-k dielectric layer/coat of metal in surface
Polysilicon layer；
2) DOPOS doped polycrystalline silicon of part is removed in the two ends of the doped polysilicon layer, then metal electricity is formed in the two ends
Pole；
3) metal level is formed in the doped polysilicon layer and surface of metal electrode using selective deposition technique；
4) insulating barrier is formed in the layer on surface of metal, contact hole is made in the insulating barrier and in the contact hole
Form through hole electrode.
As a kind of preferred version of the manufacture method of the high-k/metal gate device metal electric resistance structure of the present invention, step 1)
Described coat of metal is TiN layer or TaN layers.
As a kind of preferred version of the manufacture method of the high-k/metal gate device metal electric resistance structure of the present invention, step 2)
The DOPOS doped polycrystalline silicon is removed using dry etching method or wet etching method.
As a kind of preferred version of the manufacture method of the high-k/metal gate device metal electric resistance structure of the present invention, step 2)
Described DOPOS doped polycrystalline silicon removes technique and removes technique while carrying out with the polycrystalline silicon dummy gate in high-k/metal gate technique.
As a kind of preferred version of the manufacture method of the high-k/metal gate device metal electric resistance structure of the present invention, step 3)
Selective deposition technique be electrochemical deposition process.
As a kind of preferred version of the manufacture method of the high-k/metal gate device metal electric resistance structure of the present invention, the gold
Category layer is CoWP layers or CoMoP layers.
The present invention also provides a kind of high-k/metal gate device metal electric resistance structure, at least includes：
Shallow trench isolation regions；
High-k dielectric layer or high-k dielectric layer/coat of metal, are incorporated into the shallow trench isolation regions surface；
Doped polysilicon layer, is incorporated into the high-k dielectric layer or high-k dielectric layer/metal coating layer surface；
Metal electrode, is incorporated into the high-k dielectric layer or high-k dielectric layer/metal coating layer surface and positioned at the doping
Polysilicon layer two ends；
Metal level, is incorporated into the doped polysilicon layer and surface of metal electrode；
Insulating barrier, is incorporated into the layer on surface of metal, and it has contact hole；
Through hole electrode；It is filled in the contact hole to be connected with the metal level.
As a kind of preferred version of the high-k/metal gate device metal electric resistance structure of the present invention, described coat of metal
For TiN layer or TaN layers.
Used as a kind of preferred version of the high-k/metal gate device metal electric resistance structure of the present invention, the metal level is CoWP
Layer or CoMoP layers.
As described above, the present invention provides a kind of high-k/metal gate device metal electric resistance structure and preparation method thereof, the making
Method includes step：1) in surface there is the shallow trench isolation regions surface of high-k dielectric layer or high-k dielectric layer/coat of metal to sink
Product doped polysilicon layer；2) DOPOS doped polycrystalline silicon of part is removed in the two ends of the doped polysilicon layer, then in the two ends shape
Into metal electrode；3) metal level is formed in the doped polysilicon layer and surface of metal electrode using selective deposition technique；4)
Insulating barrier is formed in the layer on surface of metal, contact hole is made in the insulating barrier and is connected with metal electrode and in the contact
Through hole electrode is formed in hole.The present invention in DOPOS doped polycrystalline silicon layer surface by forming layer of metal layer resistance or makes DOPOS doped polycrystalline silicon
The metal level on surface forms parallel resistance with the coat of metal of high-k dielectric layer, greatly reduces the whole of metallic resistance structure
Bulk resistor, and it is capable of achieving the adjustable of overall electrical resistance by adjusting the material category and thickness of increased metal level；Work of the present invention
Skill is simple, it is adaptable to commercial production.
Description of the drawings
Fig. 1 is shown as a kind of structural representation of high-k/metal gate device metal electric resistance structure of the prior art.
Fig. 2～Fig. 3 is shown as the manufacture method step of the high-k/metal gate device metal electric resistance structure in the embodiment of the present invention 1
The rapid structural representation for 1) being presented.
Fig. 4～Fig. 5 is shown as the manufacture method step of the high-k/metal gate device metal electric resistance structure in the embodiment of the present invention 1
The rapid structural representation for 2) being presented.
Fig. 6 is shown as the manufacture method step 3 of the high-k/metal gate device metal electric resistance structure in the embodiment of the present invention 1) institute
The structural representation of presentation.
Fig. 7～Fig. 8 is shown as the manufacture method step of the high-k/metal gate device metal electric resistance structure in the embodiment of the present invention 1
The rapid structural representation for 4) being presented.
Fig. 9 is shown as the equivalent resistance schematic diagram of the high-k/metal gate device metal electric resistance structure in the embodiment of the present invention 1.
Figure 10 is shown as the structural representation of the high-k/metal gate device metal electric resistance structure in the embodiment of the present invention 2.
Figure 11 is shown as the equivalent resistance schematic diagram of the high-k/metal gate device metal electric resistance structure in the embodiment of the present invention 2.
Component label instructions
201 shallow trench isolation regions
203 high-k dielectric layer
204 coat of metals
205 doped polysilicon layers
206 metal electrodes
207 metal levels
208 insulating barriers
209 through hole electrodes
Specific embodiment
Embodiments of the present invention are illustrated below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands easily other advantages and effect of the present invention.The present invention can also pass through concrete realities different in addition
The mode of applying is carried out or applies, the every details in this specification can also based on different viewpoints with application, without departing from
Various modifications and changes are carried out under the spirit of the present invention.
Refer to Fig. 2～Figure 11.It should be noted that the diagram provided in the present embodiment only illustrates in a schematic way this
The basic conception of invention, only shows with relevant component in the present invention rather than according to package count during actual enforcement in schema then
Mesh, shape and size are drawn, and the kenel of each component, quantity and ratio can be a kind of random change during its actual enforcement, and its
Assembly layout kenel is likely to increasingly complex.
Embodiment 1
As shown in Fig. 2～Fig. 9, the present embodiment provides a kind of manufacture method of high-k/metal gate device metal electric resistance structure, extremely
Comprise the following steps less：
As shown in Figure 2 to 3, step 1 is carried out first), there is high-k dielectric layer/coat of metal 203～204 in surface
The surface depositing doped polysilicon layer 205 of shallow trench isolation regions 201.
As an example, described coat of metal 204 is TiN layer or TaN layers.
As an example, the high-k gate dielectric and metal of the high-k dielectric layer/coat of metal and the high-k/metal gate device
Protective layer is formed simultaneously, and does not need additional process step.
As an example, the doped polysilicon layer 205 is the doped polysilicon layer of doping, can be the doping of p-type doping
The doped polysilicon layer of polysilicon layer, or n-type doping, can be determined according to type of device.
As shown in Fig. 4～Fig. 5, step 2 is then carried out), remove mixing for part in the two ends of the doped polysilicon layer 205
Miscellaneous polysilicon, then forms metal electrode 206 in the two ends.
As an example, photoetching offset plate figure is formed prior to the surface of the doped polysilicon layer 205, then using dry etching method
Or wet etching method removes the DOPOS doped polycrystalline silicon.
As an example, described DOPOS doped polycrystalline silicon removes technique and removes work with the polycrystalline silicon dummy gate in high-k/metal gate technique
Skill is carried out simultaneously, and does not need additional process step.
As an example, first in the two ends of the doped polysilicon layer 205 and the surface deposited metal electricity of doped polysilicon layer 205
Pole 206, is then polished to using chemical mechanical polishing method and exposes the doped polysilicon layer 205.The material of the metal electrode 206
Material species can be determined according to the type of device, can apply to the metal or the gold suitable for P-type device of N-type device
Category.
As shown in fig. 6, then carrying out step 3), using selective deposition technique in the doped polysilicon layer 205 and gold
The category forming metal layer on surface 207 of electrode 206.
As an example, selected in the doped polysilicon layer 205 and the surface of metal electrode 206 using electrochemical deposition process
Property formed metal level 207.Concrete principle is that electrochemical deposition process has higher sedimentation rate to conductive surface, therefore, can
Other knots of device are not affected so that doped polysilicon layer 205 described in very fast DIYU and the table of metal electrode 206 form metal level 207
Structure.
As an example, the metal level 207 is CoWP layers or CoMoP layers.
As an example, the direct phase of final resistance value of the material and thickness of the metal level 207 and the metallic resistance structure
Close, the material and thickness for adjusting the metal level 207 can be passed through, so as to realize the controllability of metallic resistance structural resistance value.
As shown in Fig. 7～Fig. 9, step 4 is finally carried out), insulating barrier 208 is formed in the surface of the metal level 207, in described
Contact hole is made in insulating barrier 208 and through hole electrode 209 is formed in the contact hole.
As an example, the material of the insulating barrier 208 is silicon dioxide, is formed by chemical vapor deposition method.
Fig. 9 is shown as the equivalent resistance figure of the metallic resistance structure of the present embodiment, it can be seen that increased metal level 207
Afterwards, resistance R of the metallic resistance structure equivalent to coat of metal 2041And the resistance R of metal level 2072Parallel resistance, therefore,
The resistance R corresponding to adjustment metal level 207 can be passed through2To adjust the overall electrical resistance of metallic resistance structure.
The present embodiment also provides a kind of high-k/metal gate device metal electric resistance structure, at least includes：
Shallow trench isolation regions 201；
High-k dielectric layer/coat of metal 203～204, is incorporated into the surface of the shallow trench isolation regions 201；
Doped polysilicon layer 205, is incorporated into the surface of high-k dielectric layer/coat of metal 203～204；
Metal electrode 206, is incorporated into the surface of high-k dielectric layer/coat of metal 203～204 and positioned at the doping
The two ends of polysilicon layer 205；
Metal level 207, is incorporated into the doped polysilicon layer 205 and the surface of metal electrode 206；
Insulating barrier 208, is incorporated into the surface of the metal level 207, and it has contact hole；
Through hole electrode 209；It is filled in the contact hole to be connected with the metal level 207.
As an example, described coat of metal 204 is TiN layer or TaN layers.
As an example, the metal level 207 is CoWP layers or CoMoP layers.
Embodiment 2
As shown in Figure 10～Figure 11, the present embodiment provides a kind of making side of high-k/metal gate device metal electric resistance structure
Method, its basic step such as embodiment 1, wherein described high-k dielectric layer/coat of metal 203～204 replaces with the high k of monolayer
Dielectric layer 203.
As shown in figure 11, the equivalent resistance of the metallic resistance structure is decided by corresponding resistance value R of the metal level 2071,
Therefore, again may be by adjusting the resistance R corresponding to metal level 2071To adjust the overall electrical resistance of metallic resistance structure.
As described in Figure 10, the present embodiment also provides a kind of high-k/metal gate device metal electric resistance structure, and its basic structure is strictly according to the facts
Example 1 is applied, wherein, described high-k dielectric layer/coat of metal 203～204 replaces with the high-k dielectric layer 203 of monolayer.
In sum, the present invention provides a kind of high-k/metal gate device metal electric resistance structure and preparation method thereof, the making
Method includes step：1) in surface there is the shallow trench isolation regions surface of high-k dielectric layer or high-k dielectric layer/coat of metal to sink
Product doped polysilicon layer；2) DOPOS doped polycrystalline silicon of part is removed in the two ends of the doped polysilicon layer, then in the two ends shape
Into metal electrode；3) metal level is formed in the doped polysilicon layer and surface of metal electrode using selective deposition technique；4)
Insulating barrier is formed in the layer on surface of metal, contact hole is made in the insulating barrier and is connected with metal electrode and in the contact
Through hole electrode is formed in hole.The present invention in DOPOS doped polycrystalline silicon layer surface by forming layer of metal layer resistance or makes DOPOS doped polycrystalline silicon
The metal level on surface forms parallel resistance with the coat of metal of high-k dielectric layer, greatly reduces the whole of metallic resistance structure
Bulk resistor, and it is capable of achieving the adjustable of overall electrical resistance by adjusting the material category and thickness of increased metal level；Work of the present invention
Skill is simple, it is adaptable to commercial production.So, the present invention effectively overcomes various shortcoming of the prior art and has high industrial profit
With value.
The principle and its effect of above-described embodiment only illustrative present invention, it is of the invention not for limiting.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and the scope without prejudice to the present invention to above-described embodiment.Cause
This, such as those of ordinary skill in the art is complete with institute under technological thought without departing from disclosed spirit
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (9)
1. a kind of manufacture method of high-k/metal gate device metal electric resistance structure, it is characterised in that at least comprise the following steps：
1）There is the shallow trench isolation regions surface deposition doped polycrystalline of high-k dielectric layer or high-k dielectric layer/coat of metal in surface
Silicon layer；
2）The DOPOS doped polycrystalline silicon of part is removed in the two ends of the doped polysilicon layer, then metal electrode is formed in the two ends；
3）Metal level is formed in the doped polysilicon layer and surface of metal electrode using selective deposition technique；
4）Insulating barrier is formed in the layer on surface of metal, contact hole is made in the insulating barrier and is formed in the contact hole
Through hole electrode.
2. the manufacture method of high-k/metal gate device metal electric resistance structure according to claim 1, it is characterised in that：Step
1）Described coat of metal is TiN layer or TaN layers.
3. the manufacture method of high-k/metal gate device metal electric resistance structure according to claim 1, it is characterised in that：Step
2）The DOPOS doped polycrystalline silicon is removed using dry etching method or wet etching method.
4. the manufacture method of high-k/metal gate device metal electric resistance structure according to claim 1, it is characterised in that：Step
2）Described DOPOS doped polycrystalline silicon removes technique and removes technique while carrying out with the polycrystalline silicon dummy gate in high-k/metal gate technique.
5. the manufacture method of high-k/metal gate device metal electric resistance structure according to claim 1, it is characterised in that：Step
3）Selective deposition technique be electrochemical deposition process.
6. the manufacture method of high-k/metal gate device metal electric resistance structure according to claim 1, it is characterised in that：It is described
Metal level is CoWP layers or CoMoP layers.
7. a kind of high-k/metal gate device metal electric resistance structure, it is characterised in that at least include：
Shallow trench isolation regions；
High-k dielectric layer or high-k dielectric layer/coat of metal, are incorporated into the shallow trench isolation regions surface；
Doped polysilicon layer, is incorporated into the high-k dielectric layer or high-k dielectric layer/metal coating layer surface；
Metal electrode, is incorporated into the high-k dielectric layer or high-k dielectric layer/metal coating layer surface and positioned at the doped polycrystalline
Silicon layer two ends；
Metal level, is incorporated into the doped polysilicon layer and surface of metal electrode；
Insulating barrier, is incorporated into the layer on surface of metal, and it has contact hole；
Through hole electrode；It is filled in the contact hole to be connected with the metal level.
8. high-k/metal gate device metal electric resistance structure according to claim 7, it is characterised in that：Described metal coating
Layer is TiN layer or TaN layers.
9. high-k/metal gate device metal electric resistance structure according to claim 7, it is characterised in that：The metal level is
CoWP layers or CoMoP layers.
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| CN201310136100.2A CN104112735B (en) | 2013-04-18 | 2013-04-18 | High-kappa metal gate device metal resistor structure and fabrication method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310136100.2A CN104112735B (en) | 2013-04-18 | 2013-04-18 | High-kappa metal gate device metal resistor structure and fabrication method thereof |
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| CN104112735A CN104112735A (en) | 2014-10-22 |
| CN104112735B true CN104112735B (en) | 2017-04-26 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6313516B1 (en) * | 1999-06-14 | 2001-11-06 | Taiwan Semiconductor Manufacturing Company | Method for making high-sheet-resistance polysilicon resistors for integrated circuits |
| CN102013424A (en) * | 2009-09-04 | 2011-04-13 | 台湾积体电路制造股份有限公司 | Integrated circuit and manufacturing method thereof |
| CN201886234U (en) * | 2010-11-29 | 2011-06-29 | 北京京东方光电科技有限公司 | Liquid crystal display base plate and liquid crystal display (LCD) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7749822B2 (en) * | 2007-10-09 | 2010-07-06 | International Business Machines Corporation | Method of forming a resistor and an FET from the metal portion of a MOSFET metal gate stack |
| JP2010283310A (en) * | 2009-06-08 | 2010-12-16 | Panasonic Corp | Semiconductor device and manufacturing method thereof |
-
2013
- 2013-04-18 CN CN201310136100.2A patent/CN104112735B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6313516B1 (en) * | 1999-06-14 | 2001-11-06 | Taiwan Semiconductor Manufacturing Company | Method for making high-sheet-resistance polysilicon resistors for integrated circuits |
| CN102013424A (en) * | 2009-09-04 | 2011-04-13 | 台湾积体电路制造股份有限公司 | Integrated circuit and manufacturing method thereof |
| CN201886234U (en) * | 2010-11-29 | 2011-06-29 | 北京京东方光电科技有限公司 | Liquid crystal display base plate and liquid crystal display (LCD) |
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