US20110175148A1 - Methods of Forming Conductive Features and Structures Thereof - Google Patents
Methods of Forming Conductive Features and Structures Thereof Download PDFInfo
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- US20110175148A1 US20110175148A1 US13/074,888 US201113074888A US2011175148A1 US 20110175148 A1 US20110175148 A1 US 20110175148A1 US 201113074888 A US201113074888 A US 201113074888A US 2011175148 A1 US2011175148 A1 US 2011175148A1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- CD critical dimension
- the workpiece 102 may be lightly doped with a dopant species to form lightly doped regions (not shown) in a top surface of the workpiece 102 proximate the gate 108 and gate dielectric 106 , after the patterning of the optional hard mask, gate 108 , and the gate dielectric 106 .
- Other implantation processes e.g., pocket implants, halo implants, or double-diffused regions
- the second material 132 is patterned with a second pattern 134 a, 134 b, and 134 c for an upper portion of the at least one feature 140 a, 140 b, and 140 c, as shown in FIG. 6 .
- the sacrificial material 126 is removed.
- the first and second patterns 124 a, 124 b, 124 c, 134 a, 134 b , and 134 c are then filled with a third material 140 , as shown in FIG. 7 , forming at least one feature 140 a, 140 b, and 140 c in the first material 116 / 122 and the second material 132 .
- the features 140 a, 140 b, and 140 c are coupled to the active areas of the transistor 120 and/or the isolation region 104 , as shown.
- the stress-inducing material 116 may comprise a material adapted to induce a stress on the transistor 120 , e.g., on the channel region 114 .
- the stress-inducing material 116 may comprise a nitride material such as silicon nitride, although alternatively, other materials may be used for the stress-inducing material 116 .
- the stress-inducing material 116 may comprise a thickness of about 100 nm or less, for example, although alternatively, the stress-inducing material 116 may comprise other dimensions.
- the stress-inducing material 116 may be adapted to cause a compressive or tensile stress, depending on the type of transistor 120 , for example.
- the stress-inducing material 116 may be substantially conformal as deposited, for example.
- the stress-inducing material 116 may not be included in the structure in some embodiments, not shown.
- the first material 116 / 122 may only comprise a first insulating material 122 , for example.
- a first insulating material 122 is deposited or formed over the stress-inducing material 116 , as shown in FIG. 2 , or over the workpiece 102 , the isolation regions 104 , and the transistor 120 , if the stress-inducing material 116 is not included.
- the first insulating material 112 may comprise silicon dioxide, silicon nitride, a low dielectric constant (k) material having a dielectric constant of less than about 3.9, other insulating materials, or combinations or multiple layers thereof, for example.
- the thickness or dimension d 1 of the first insulating material 122 may comprise several hundred nm, for example, although alternatively, dimension d 1 may comprise other values.
- the thickness or dimension d 1 of the first insulating material 122 may comprise about 200 nm in some embodiments, for example, and may comprise about 100 nm or greater in some applications.
- the first insulating material 122 may be deposited to cover the top surface of the gate 108 or the stress-inducing material 116 disposed over the gate 108 , for example.
- the first material 116 / 122 is patterned with a first pattern 124 a, 124 b, and 124 c for a lower portion of at least one feature 140 a, 140 b, and 140 c (see FIG. 7 ), as shown in FIG. 3 .
- the first material 116 / 122 is patterned by depositing a photosensitive material over the first material 116 / 122 , patterning the photosensitive material using a lithography mask or direct etch process, developing the photosensitive material, and using the photosensitive material as an etch mask while exposed portions of the first material 116 / 122 are etched away, leaving the patterns 124 a, 124 b, and 124 c in the first material 116 / 122 , as shown in FIG. 3 .
- the patterns 124 a, 124 b, and 124 c comprise a first pattern for a lower portion of at least one conductive feature, such as a contact or via.
- the patterns 124 a, 124 b, and 124 c may comprise a width comprising dimension d 2 , wherein dimension d 2 is about 100 nm or less, although alternatively, dimension d 2 may comprise other dimensions.
- Dimension d 2 may comprise a minimum feature size of the lithography system and process used to form the patterns 124 a, 124 b, and 124 c, in some embodiments, for example. Alternatively, dimension d 2 may be larger than a minimum feature size, as another example.
- the width or dimension d 2 of the first patterns 124 a, 124 b, and 124 c in the first material 116 / 122 is also referred to herein as a first width.
- the patterns 124 a, 124 b, and 124 c may comprise a square or rectangular shape in a top view, for example, not shown.
- the patterns 124 a, 124 b, and 124 c may alternatively be round or elliptical in a top view, also not shown.
- the patterns 124 a, 124 b, and 124 c may comprise other shapes.
- Pattern 124 a shown in FIG. 3 comprises a pattern for a lower portion of a conductive feature or contact that is coupled to the gate 108 of the transistor 120 .
- Pattern 124 b comprises a pattern for a lower portion of a contact that is coupled to the source or drain region 112 of the transistor 120 .
- Pattern 124 c comprises a pattern for a lower portion of a contact that is coupled to the isolation region 104 proximate the transistor 120 .
- the patterns 124 a , 124 b, and 124 c in the first material 116 / 122 are filled with a sacrificial material 126 , as shown in FIG. 4 .
- the sacrificial material 126 may comprise a top surface that extends over a top surface of the first insulating material 122 of the first material 116 / 122 , for example, as shown at 128 in phantom.
- the workpiece 102 may be exposed to a CMP and/or an etch process to remove the excess sacrificial material 126 from over the top surface of the first insulating material 122 , as shown.
- the sacrificial material 126 comprises an insulating material in some embodiments.
- the sacrificial material 126 may comprise carbon or germanium oxide (GEO 2 ), as examples.
- the sacrificial material 126 may comprise other types of materials that are easily removed in a subsequent processing step from the patterns 124 a, 124 b, and 124 c in some embodiments, for example.
- the sacrificial material 126 may be deposited using CVD or other deposition processes, for example.
- the top surface of the sacrificial material 126 and the first insulating material 122 may be coplanar, as shown.
- a second material 132 is then formed over the first material 116 / 122 and the sacrificial material 126 , as shown in FIG. 5 .
- the second material 132 comprises a second insulating material in some embodiments, for example.
- the second material 132 may alternatively comprise other materials, such as a conductive material or semiconductive material in other embodiments.
- the second material 132 may comprise a similar material or materials as described for the first insulating material 122 , for example.
- the second material 132 may comprise the same material as the first insulating material 122 , or the second material 132 may comprise a different material than the first insulating material 122 , for example.
- the second material 132 may comprise a thickness or dimension d 3 of about 100 nm or greater, as an example, although alternatively, the dimension d 3 may comprise other values.
- the second material 132 may comprise a thickness or dimension d 3 that is less than the thickness or dimension d 1 of the first insulating material 122 , for example, as shown in FIG. 5 .
- the second material 132 may comprise a greater thickness or dimension d 3 than the thickness or dimension d 1 of the first insulating material 122 , or the second material 132 may comprise a thickness or dimension d 3 that is substantially the same as the thickness or dimension d 1 of the first insulating material 122 , as examples, not shown.
- the second material 132 is patterned using a second lithography process, forming a second pattern 134 a, 134 b, and 134 c in the second material 132 for an upper portion of features, as shown in phantom in FIG. 5 .
- the second patterns 134 a, 134 b, and 134 c may comprise a width comprising dimension d 4 that may be larger than the width or dimension d 2 of the first patterns 124 a, 124 b, and 124 c, as shown, in some embodiments.
- the second patterns 134 a , 134 b, and 134 c being larger than the first patterns 124 a, 124 b, and 124 c ensures alignment of the second patterns 134 a, 134 b, and 134 c with the underlying first patterns 124 a, 124 b, and 124 c, for example.
- Dimension d 4 may comprise about twice a minimum feature size of the lithography system and process used to process the semiconductor device 100 in some embodiments, for example. Alternatively, dimension d 4 may comprise other values.
- the width or dimension d 4 of the second patterns 134 a, 134 b, and 134 c in the second material 132 is also referred to herein as a second width, wherein the second width or dimension d 4 is greater than the first width or dimension d 2 of the first patterns 124 a, 124 b, and 124 c in the first material 116 / 122 .
- the etch process used to form the second patterns 132 a, 134 b, and 134 c may result in second patterns 132 a, 134 b, and 134 c comprising tapered sidewalls, wherein the second patterns 132 a, 134 b, and 134 c are larger at the top than at the bottom within the second insulating material 132 .
- the etch process used to form the first patterns 124 a, 124 b, and 124 c may also comprise tapered sidewalls, being larger at the top of the first material 116 / 122 than at the bottom of the first material 116 / 122 , not shown.
- the etch process used to form the first patterns 124 a, 124 b, and 124 c in the first material 116 / 112 may comprise more of an isotropic component than the etch process used to form the second patterns 132 a, 134 b, and 134 c in the second material 132 , resulting in first patterns 124 a, 124 b, and 124 c having substantially vertical sidewalls, as shown.
- At least portions of the second patterns 134 a, 134 b, and 134 c in the second material 132 may be larger than the first patterns 124 a, 124 b, and 124 c in the first material 116 / 122 .
- the second patterns 134 a, 134 b, and 134 c may comprise substantially the first width or dimension d 2 in the bottom portion of the second material 132
- the second patterns 134 a , 134 b, and 134 c may comprise substantially the second width or dimension d 4 in a top portion of the second material 132 , as shown in phantom in FIG. 5 .
- a different lithography mask may be used to pattern the second insulating material 132 than the lithography mask used to pattern the first insulating material 122 and the stress-inducing material 116 , for example.
- the second patterns 134 a, 134 b, and 134 c being larger than the first patterns 124 a , 124 b, and 124 c is advantageous in some embodiments because the fill process or deposition process for the third material 140 (see FIG. 7 ) is facilitated, for example.
- the second patterns 134 a, 134 b, and 134 c may be about 20 to 40% larger than the first patterns 124 a, 124 b, and 124 c in some embodiments, for example. In other embodiments, the second patterns 134 a, 134 b, and 134 c may be about 50% or less larger than the first patterns 124 a, 124 b, and 124 c, as another example.
- Second patterns 134 a, 134 b, and 134 c also facilitates in the removal of the sacrificial material 126 from within the first patterns 124 a, 124 b, and 124 c in the first material 116 / 122 , for example.
- the sacrificial material 126 is removed from the first patterns 124 a, 124 b, and 124 c in the first material 116 / 122 , as shown in FIG. 6 .
- the sacrificial material 126 may be removed using an etch process, an ashing process, a cleaning process, or a removal process comprising deionized water. Alternatively, the sacrificial material 126 may be removed using other methods.
- the sacrificial material 126 may be removed using a cleaning process comprising deionized water.
- the sacrificial material 126 comprises carbon
- the sacrificial material 126 may be removed using an ashing process, wherein the workpiece 102 is heated and the ashed carbon is then cleaned from the workpiece 102 .
- the method of removing the sacrificial material 126 may be selected according to the type of material used for the sacrificial material 126 . In accordance with some embodiments, for example, the material choice of the sacrificial material 126 is selected to that the sacrificial material 126 is easy to remove.
- the first patterns 124 a, 124 b, and 124 c in the first material 116 / 122 and the second patterns 134 a, 134 b, and 134 c in the second material 132 are then filled with a third material 140 , as shown in FIG. 7 .
- the third material 140 comprises a conductive material in some embodiments, e.g., if the first material 116 / 122 and the second material 132 comprise insulating materials.
- the third material 140 may alternatively comprise a semiconductive material.
- the third material 104 may comprise an insulator, e.g., if the first material 116 / 122 and the second material 132 comprise conductive or semiconductive materials.
- the third material 140 comprises a different type of material than the first material 116 / 122 and the second material 132 , in some embodiments.
- the features 140 a, 140 b, and 140 c comprise conductive features in some embodiments, wherein the conductive features comprise contacts or vias that are coupled to portions of the transistor 120 .
- feature 140 a is coupled to the gate 108 of the transistor 120
- feature 140 b is coupled to the source or drain region 112 of the transistor 120 .
- Some features 140 a, 140 b, and 140 c may also be coupled to other devices or regions of the workpiece 102 .
- feature 140 c is coupled to the isolation region 104 proximate the transistor 120 .
- Conductive lines may be formed over the features 140 a, 140 b, and 140 c in subsequently formed conductive line or metallization layers, not shown.
- the conductive lines and the features 140 a, 140 b, and 140 c connect the active areas of the transistor 120 to other regions of the semiconductor device 100 or to contact pads on a upper material layer of the semiconductor device 100 , which may be connected to for use in an end application, e.g., during packaging of the semiconductor device 100 , for example.
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Abstract
Methods of forming features and structures thereof are disclosed. In one embodiment, a method of forming a feature includes forming a first material over a workpiece, forming a first pattern for a lower portion of the feature in the first material, and filling the first pattern with a sacrificial material. A second material is formed over the first material and the sacrificial material, and a second pattern for an upper portion of the feature is formed in the second material. The sacrificial material is removed. The first pattern and the second pattern are filled with a third material.
Description
- This is a divisional application of U.S. application Ser. No. 12/129,479, which was filed on May 29, 2008, and is incorporated herein by reference.
- The present invention relates generally to the fabrication of semiconductor devices, and more particularly to the fabrication of conductive features of transistor devices.
- Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various layers using lithography to form circuit components and elements thereon.
- A transistor is an element that is used frequently in semiconductor devices. There may be millions of transistors on a single integrated circuit (IC), for example. A common type of transistor used in semiconductor device fabrication is a metal oxide semiconductor field effect transistor (MOSFET), as an example. A transistor typically includes a gate dielectric disposed over a channel region in a substrate, and a gate electrode formed over the gate dielectric. A source region and a drain region are formed on either side of the channel region within the substrate.
- Contacts are conductive features that are used to make electrical contact to regions of transistors, such as source regions, drain regions, and gate regions of semiconductor devices. Contacts are often connected between the active regions of the transistors and conductive lines that couple the transistor to other parts of the semiconductor device or to contact pads, for example.
- As features of semiconductor devices are decreased in size, as is the trend in the semiconductor industry, forming conductive features such as contacts becomes more challenging.
- Thus, what are needed in the art are improved methods of forming conductive features of semiconductor devices and structures thereof.
- These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention, which provide novel methods of manufacturing semiconductor devices and transistors and structures thereof.
- In accordance with one embodiment of the present invention, a method of forming a feature includes forming a first material over a workpiece, forming a first pattern for a lower portion of the feature in the first material, and filling the first pattern with a sacrificial material. A second material is formed over the first material and the sacrificial material, and a second pattern for an upper portion of the feature is formed in the second material. The sacrificial material is removed. The first pattern and the second pattern are filled with a third material.
- The foregoing has outlined rather broadly the features and technical advantages of embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of embodiments of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
- For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
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FIGS. 1 through 7 show cross-sectional views of a semiconductor device at various stages of manufacturing in accordance with an embodiment of the present invention, wherein contacts of a transistor are formed using a two step lithography process; and -
FIGS. 8 through 11 show cross-sectional views of a semiconductor device in accordance with another embodiment of the present invention, wherein contacts of an n channel metal oxide semiconductor (NMOS) field effect transistor (FET) and a p channel metal oxide semiconductor (PMOS) FET of a complementary metal oxide semiconductor (CMOS) device are formed using the two step lithography process. - Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale.
- The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
- There is a trend in semiconductor technology to reduce the size of devices, to improve performance and reduce power requirements, as examples. The minimum feature size or critical dimension (CD) of semiconductor devices continues to become smaller and smaller. For example, advanced technology nodes are developing 60 nm, 45 nm, and 32 nm CDs, and the trend in reducing CD's is expected to continue.
- Some conductive features of semiconductor devices may comprise the minimum feature size or CD of a technology node, such as conductive area size and gate widths, which may comprise a minimum size on one side and extend lengthwise on another side, e.g., in a top view. Other types of conductive features may comprise the minimum feature size on both sides, such as contacts or vias.
- Contacts typically are formed in a first metallization layer over a portion of a semiconductor device that is manufactured in a front end of the line (FEOL). Contacts may comprise a minimum feature size because some contacts may be used to make electrical contact with gates, which also comprise the minimum feature size, for example. Contacts can be difficult to manufacture, because they are often formed using a damascene process, wherein an insulating material is patterned and then filled with conductive material to fill the patterns. However, the insulating material may comprise a high aspect ratio, so that the patterns to be filled in the insulating material comprise a greater height than width, making them difficult to pattern and to fill with the conductive materials.
- Thus, what are needed in the art are improved methods of forming contacts, conductive features, and other features of semiconductor devices.
- Embodiments of the present invention achieve technical advantages by providing novel methods of forming features of semiconductor devices. The features may comprise conductive features, and may comprise contacts or vias in some applications, for example. Embodiments of the present invention comprise aspect ratio-friendly contact process flows for semiconductor devices.
- The present invention will be described with respect to preferred embodiments in specific contexts, namely implemented in single transistor devices and CMOS two-transistor device applications. Embodiments of the invention may also be implemented in other semiconductor applications such as memory devices, logic devices, and other applications, for example. Embodiments of the invention may be used to form conductive features of other devices than transistors, and may also be used to form non-conductive features of semiconductor devices.
- In accordance with an embodiment of the present invention, a method of forming a feature comprises forming a first material over a workpiece, patterning the first material with a first pattern for a lower portion of the feature, and filling the first pattern with a sacrificial material. A second material is formed over the first material and the sacrificial material, and the second material is patterned with a second pattern for an upper portion of the feature. The sacrificial material is removed, and the first and second patterns are filled with a third material. The feature may comprise a feature of a semiconductor device, for example.
-
FIGS. 1 through 7 show cross-sectional views of asemiconductor device 100 at various stages of manufacturing in accordance with a preferred embodiment of the present invention. To manufacture thesemiconductor device 100, first, aworkpiece 102 is provided. Theworkpiece 102 may include a semiconductor substrate, body, or workpiece comprising silicon or other semiconductor materials and may be covered by an insulating layer, for example. Theworkpiece 102 may also include other active components or circuits, not shown. Theworkpiece 102 may comprise silicon oxide over single-crystal silicon, for example. Theworkpiece 102 may include other conductive layers or other semiconductor elements, e.g., transistors, diodes, etc. Compound semiconductors, GaAs, InP, Si/Ge, or SiC, as examples, may be used in place of silicon. Theworkpiece 102 may comprise a silicon-on-insulator (SOI) or a germanium-on-insulator (GOI) substrate, as examples. -
Isolation regions 104 are formed in theworkpiece 102. Theisolation regions 104 may comprise shallow trench isolation (STI) regions, deep trench (DT) isolation regions, field oxide isolation regions, or other insulating regions, as examples. Theisolation regions 104 may be formed by depositing a hard mask (not shown) over theworkpiece 102 and forming trenches in theworkpiece 102 and the hard mask using a lithography process. For example, theisolation regions 104 may be formed by depositing a photoresist, patterning the photoresist using a lithography mask and an exposure process, developing the photoresist, removing portions of the photoresist, and then using the photoresist and/or hard mask to protect portions of theworkpiece 102 while other portions are etched away, forming trenches in theworkpiece 102. The photoresist is removed, and the trenches are then filled with an insulating material such as an oxide or nitride, or multiple layers and combinations thereof, as examples. The hard mask may then be removed. Alternatively, theisolation regions 104 may be formed using other methods and may be filled with other materials. - A
gate dielectric material 106 is deposited over theworkpiece 102 and theisolation regions 104. Thegate dielectric material 106 preferably comprises about 200 Angstroms or less of an oxide such as SiO2, a nitride such as Si3N4, a high-k dielectric material having a dielectric constant greater than about 3.9, or combinations and multiple layers thereof, as examples. Alternatively, thegate dielectric material 106 may comprise other dimensions and materials, for example. Thegate dielectric material 106 may be formed using thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), or jet vapor deposition (JVD), as examples, although alternatively, other methods may also be used. - A
gate material 108 is deposited over thegate dielectric material 106. Thegate material 108 comprises an electrode material. Thegate material 108 may comprise a thickness of about 1,500 Angstroms or less, for example. Thegate material 108 may comprise a semiconductor material, such as polysilicon or amorphous silicon, a metal, and/or combinations or multiple layers thereof, as examples. Alternatively, thegate material 108 may comprise other dimensions and materials, for example. Thegate material 108 may be formed by CVD, PVD, or other suitable deposition methods, for example. Thegate material 108 may optionally be implanted with dopants; e.g., thegate material 108 may be predoped or may be doped later, at the same time source and drainregions 112 are implanted with dopants. - The
gate material 108 and thegate dielectric material 106 are patterned using lithography to form agate 108 andgate dielectric 106. For example, a layer of photosensitive material (not shown) such as a photoresist may be deposited over thegate material 108, and the layer of photosensitive material may be patterned with the desired pattern for thegate 108 andgate dielectric 106. An optional hard mask (also not shown) may be formed over thegate material 108 before depositing the layer of photosensitive material, for example. The hard mask may comprise a nitride material such as silicon nitride, an oxide material such as silicon dioxide, or multiple layers and combinations thereof, for example, although alternatively, the optional hard mask may comprise other materials. The patterned layer of photosensitive material and optionally also the hard mask are used as an etch mask to pattern thegate 108 and thegate dielectric 106. The layer of photosensitive material and the optional hard mask are then removed. - The
gate 108 may comprise a width or a gate length of about 35 to 42 nm in some embodiments, for example, although alternatively, thegate 108 may comprise other dimensions. Thegate 108 may comprise a minimum feature size of the technology node, e.g., of the manufacturing and lithography processes used to fabricate thesemiconductor device 100. Thegate 108 may extend lengthwise in and out of the paper in the view shown inFIG. 1 by about 500 nm, as an example. Alternatively, thegate 108 may comprise other dimensions depending on the particular application and the technology node used for the manufacturing of thesemiconductor device 100, for example. - The
workpiece 102 may be lightly doped with a dopant species to form lightly doped regions (not shown) in a top surface of theworkpiece 102 proximate thegate 108 andgate dielectric 106, after the patterning of the optional hard mask,gate 108, and thegate dielectric 106. Other implantation processes (e.g., pocket implants, halo implants, or double-diffused regions) may optionally also be performed as desired after the patterning of thegate 108 andgate dielectric 106, for example. - A
sidewall spacer material 110 is formed over the top surface of thegate 108, theworkpiece 102, theisolation regions 104, and over the sidewalls of thegate 108 andgate dielectric 106, as shown inFIG. 1 . Thesidewall spacer material 110 may comprise one or more liners and may comprise two or more layers of insulating material, e.g., such as silicon nitride, silicon oxide, and/or silicon oxynitride, although other materials may also be used. Thesidewall spacer material 110 may comprise an oxide liner and a nitride layer disposed over the oxide liner, as an example. Thesidewall spacer material 110 may be substantially conformal as-deposited, for example. Thesidewall spacer material 110 is etched using an anisotropic or directional etch process, leavingsidewall spacers 110 on the sidewalls of thegate 108 andgate dielectric 106, as shown inFIG. 1 . The anisotropic etch process removes thesidewall spacer material 110 from the top surfaces of thegate 108, theworkpiece 102, and theisolation regions 104, leavingsidewall spacers 110 on the sidewalls of thegate 108 andgate dielectric 106. The sidewall spacers 110 may comprise downwardly-sloping sidewalls, as shown, due to the anisotropic etch process, for example. The sidewall spacers 110 may comprise a thickness along the sidewalls of thegate 108 of about 100 to 400 Angstroms, although alternatively, thesidewall spacers 110 may comprise other dimensions. - After the formation of the
sidewall spacers 110, theworkpiece 102 may be implanted with a dopant species proximate thefirst sidewall spacers 110, forming source and drainregions 112 of atransistor 120. Theworkpiece 102 may be annealed or heated to drive the dopant species deeper into theworkpiece 102, for example. - The sidewall spacers 110 may comprise temporary sidewall spacers that are later removed and replaced with permanent
first sidewall spacers 110 that remain in the structure in some embodiments, for example. Alternatively, thesidewall spacers 110 may comprise permanent sidewall spacers, as another example. Achannel region 114 of thetransistor 120 is formed in theworkpiece 102 beneath thegate 108, e.g., beneath thegate dielectric 106. - Only one
transistor 120 andisolation region 104 is shown inFIG. 1 . However, there may be a plurality oftransistors 120 andisolation regions 104 formed across a surface of aworkpiece 102, for example, not shown. - Portions of the
transistor 120 comprise active areas, such as thegate 108 and the source and drainregions 112. Thegate 108 and the source and drainregion 112 may optionally be silicided, for example, not shown inFIG. 1 (seesilicide regions FIG. 8 ). - Embodiments of the present invention comprise novel methods of forming features and structures thereof that are coupled to the
transistor 120 active areas or theisolation region 104, to be described further herein. Embodiments of the present invention also include forming other types of devices over theworkpiece 102, and forming features that are coupled to a portion of the devices, for example. - For example, in accordance with embodiments of the present invention, a
first material 116/122 is deposited over theworkpiece 102, as shown inFIGS. 1 and 2 . Thefirst material 116/122 is patterned with afirst pattern feature FIG. 7 ), as shown inFIG. 3 . Asacrificial material 126 is formed in thefirst pattern FIG. 4 . Asecond material 132 is formed over thefirst material 116/122 and thesacrificial material 126, as shown inFIG. 5 , and thesecond material 132 is patterned with asecond pattern feature FIG. 6 . Thesacrificial material 126 is removed. The first andsecond patterns third material 140, as shown inFIG. 7 , forming at least onefeature first material 116/122 and thesecond material 132. Thefeatures transistor 120 and/or theisolation region 104, as shown. - In some embodiments, the
first material 116/122 and thesecond material 132 comprise insulating materials, and thethird material 140 comprises a conductive material or semiconductive material, as shown inFIGS. 1 through 7 in a first embodiment and as shown inFIGS. 8 through 11 in a second embodiment. In other embodiments, thefirst material 116/122 and thesecond material 132 may comprise conductive materials or semiconductive materials, and thethird material 140 may comprise an insulating material, for example. Thethird material 140 may comprise a different type of material than thefirst material 116/122 or thesecond material 132. - The
first material 116/122 may include a stress-inducingmaterial 116 and a first insulatingmaterial 122. The firstinsulating material 122 may comprise a partial insulating material layer for a contact level of thesemiconductor device 100, and the second insulatingmaterial 132 may comprise a remaining insulating material layer for the contact level of thesemiconductor device 100, for example. Thus, the first insulatingmaterial 122 and the second insulatingmaterial 132 may together comprise an insulating material layer for a contact layer. - To fabricate the
semiconductor device 100, thefirst material 116/122 is formed over theworkpiece 102, e.g., over the top surface of theworkpiece 102, theisolation region 104, and thetransistor 120, as shown inFIGS. 1 and 2 . Thefirst material 116/122 may comprise a single material layer in some embodiments, not shown. In other embodiments, thefirst material 116/122 may comprise a stress-inducingmaterial 116 and a first insulatingmaterial 122 disposed over the stress-inducingmaterial 116, as shown inFIG. 2 . - The stress-inducing
material 116 may comprise a material adapted to induce a stress on thetransistor 120, e.g., on thechannel region 114. The stress-inducingmaterial 116 may comprise a nitride material such as silicon nitride, although alternatively, other materials may be used for the stress-inducingmaterial 116. The stress-inducingmaterial 116 may comprise a thickness of about 100 nm or less, for example, although alternatively, the stress-inducingmaterial 116 may comprise other dimensions. The stress-inducingmaterial 116 may be adapted to cause a compressive or tensile stress, depending on the type oftransistor 120, for example. The stress-inducingmaterial 116 may be substantially conformal as deposited, for example. - The type of material, the deposition process, and the thickness of the stress-inducing
material 116 may be selected to achieve the amount and type of stress required to improve the performance of thetransistor 120, for example. The various types and amount of stress may be created in a nitride material such as silicon nitride by changing the deposition temperature and various processing conditions, for example. - If the
transistor 120 comprises a p channel metal oxide semiconductor (PMOS) field effect transistor (FET), the stress-inducingmaterial 116 may comprise a material that increases the tensile stress of the source region and thedrain regions 112 of thetransistor 120, which creates compressive stress on thechannel region 114, for example. As another example, if thetransistor 120 comprises an n channel metal oxide semiconductor (NMOS) field effect transistor (FET), the stress-inducingmaterial 116 may comprise a material adapted to increase the compressive stress of the source and drainregion 112 of thetransistor 120, which creates tensile stress on thechannel region 114, for example. - Alternatively, the stress-inducing
material 116 may not be included in the structure in some embodiments, not shown. Thefirst material 116/122 may only comprise a first insulatingmaterial 122, for example. - A first insulating
material 122 is deposited or formed over the stress-inducingmaterial 116, as shown inFIG. 2 , or over theworkpiece 102, theisolation regions 104, and thetransistor 120, if the stress-inducingmaterial 116 is not included. The firstinsulating material 112 may comprise silicon dioxide, silicon nitride, a low dielectric constant (k) material having a dielectric constant of less than about 3.9, other insulating materials, or combinations or multiple layers thereof, for example. The thickness or dimension d1 of the first insulatingmaterial 122 may comprise several hundred nm, for example, although alternatively, dimension d1 may comprise other values. The thickness or dimension d1 of the first insulatingmaterial 122 may comprise about 200 nm in some embodiments, for example, and may comprise about 100 nm or greater in some applications. The firstinsulating material 122 may be deposited to cover the top surface of thegate 108 or the stress-inducingmaterial 116 disposed over thegate 108, for example. - The first
insulating material 122 may be deposited having a top surface that is disposed above or over the top surface of the stress-inducingmaterial 116. A chemical mechanical polish (CMP) process and/or an etch process may be used to lower the height of the first insulatingmaterial 122, leaving the structure shown inFIG. 2 . The CMP process may be adapted to stop on the stress-inducingmaterial 116 over thegate 108, for example. - The top surface of the stress-inducing
material 116 over thegate 108 may comprise substantially the same height as the top surface of the first insulatingmaterial 122, as shown. The top surface of the stress-inducingmaterial 116 over thegate 108 and the top surface of the first insulatingmaterial 122 may be coplanar, so that a smooth top surface resides over theworkpiece 102, for example. - Next, using a first lithography process, the
first material 116/122 is patterned with afirst pattern feature FIG. 7 ), as shown inFIG. 3 . Thefirst material 116/122 is patterned by depositing a photosensitive material over thefirst material 116/122, patterning the photosensitive material using a lithography mask or direct etch process, developing the photosensitive material, and using the photosensitive material as an etch mask while exposed portions of thefirst material 116/122 are etched away, leaving thepatterns first material 116/122, as shown inFIG. 3 . - The first pattern comprises a plurality of
patterns patterns FIG. 3 ; alternatively, the first pattern for the lower portion of the features may comprisemany patterns workpiece 102. - The
patterns patterns patterns first patterns first material 116/122 is also referred to herein as a first width. - The
patterns patterns patterns -
Pattern 124 a shown inFIG. 3 comprises a pattern for a lower portion of a conductive feature or contact that is coupled to thegate 108 of thetransistor 120.Pattern 124 b comprises a pattern for a lower portion of a contact that is coupled to the source or drainregion 112 of thetransistor 120.Pattern 124 c comprises a pattern for a lower portion of a contact that is coupled to theisolation region 104 proximate thetransistor 120. - The etch process to form the
patterns - Next, in accordance with embodiments of the present invention, the
patterns first material 116/122 are filled with asacrificial material 126, as shown inFIG. 4 . Thesacrificial material 126 may comprise a top surface that extends over a top surface of the first insulatingmaterial 122 of thefirst material 116/122, for example, as shown at 128 in phantom. Theworkpiece 102 may be exposed to a CMP and/or an etch process to remove the excesssacrificial material 126 from over the top surface of the first insulatingmaterial 122, as shown. - The
sacrificial material 126 comprises an insulating material in some embodiments. Thesacrificial material 126 may comprise carbon or germanium oxide (GEO2), as examples. Thesacrificial material 126 may comprise other types of materials that are easily removed in a subsequent processing step from thepatterns sacrificial material 126 may be deposited using CVD or other deposition processes, for example. The top surface of thesacrificial material 126 and the first insulatingmaterial 122 may be coplanar, as shown. - A
second material 132 is then formed over thefirst material 116/122 and thesacrificial material 126, as shown inFIG. 5 . Thesecond material 132 comprises a second insulating material in some embodiments, for example. Thesecond material 132 may alternatively comprise other materials, such as a conductive material or semiconductive material in other embodiments. Thesecond material 132 may comprise a similar material or materials as described for the first insulatingmaterial 122, for example. Thesecond material 132 may comprise the same material as the first insulatingmaterial 122, or thesecond material 132 may comprise a different material than the first insulatingmaterial 122, for example. - The
second material 132 may comprise a thickness or dimension d3 of about 100 nm or greater, as an example, although alternatively, the dimension d3 may comprise other values. Thesecond material 132 may comprise a thickness or dimension d3 that is less than the thickness or dimension d1 of the first insulatingmaterial 122, for example, as shown inFIG. 5 . Alternatively, thesecond material 132 may comprise a greater thickness or dimension d3 than the thickness or dimension d1 of the first insulatingmaterial 122, or thesecond material 132 may comprise a thickness or dimension d3 that is substantially the same as the thickness or dimension d1 of the first insulatingmaterial 122, as examples, not shown. - The
second material 132 is patterned using a second lithography process, forming asecond pattern second material 132 for an upper portion of features, as shown in phantom inFIG. 5 . Thesecond patterns first patterns second patterns first patterns second patterns first patterns semiconductor device 100 in some embodiments, for example. Alternatively, dimension d4 may comprise other values. The width or dimension d4 of thesecond patterns second material 132 is also referred to herein as a second width, wherein the second width or dimension d4 is greater than the first width or dimension d2 of thefirst patterns first material 116/122. - The etch process used to form the
second patterns second patterns second patterns material 132. The etch process used to form thefirst patterns first material 116/122 than at the bottom of thefirst material 116/122, not shown. However, in some embodiments, the etch process used to form thefirst patterns first material 116/112 may comprise more of an isotropic component than the etch process used to form thesecond patterns second material 132, resulting infirst patterns - At least portions of the
second patterns second material 132 may be larger than thefirst patterns first material 116/122. For example, thesecond patterns second material 132, and thesecond patterns second material 132, as shown in phantom inFIG. 5 . - A different lithography mask may be used to pattern the second insulating
material 132 than the lithography mask used to pattern the first insulatingmaterial 122 and the stress-inducingmaterial 116, for example. - The
second patterns first patterns FIG. 7 ) is facilitated, for example. Thesecond patterns first patterns second patterns first patterns second patterns sacrificial material 126 from within thefirst patterns first material 116/122, for example. - After the
second material 132 is patterned to form thesecond patterns first patterns first material 116/122, thesacrificial material 126 is removed from thefirst patterns first material 116/122, as shown inFIG. 6 . Thesacrificial material 126 may be removed using an etch process, an ashing process, a cleaning process, or a removal process comprising deionized water. Alternatively, thesacrificial material 126 may be removed using other methods. - For example, in embodiments wherein the
sacrificial material 126 comprises GeO2, thesacrificial material 126 may be removed using a cleaning process comprising deionized water. In embodiments wherein thesacrificial material 126 comprises carbon, thesacrificial material 126 may be removed using an ashing process, wherein theworkpiece 102 is heated and the ashed carbon is then cleaned from theworkpiece 102. The method of removing thesacrificial material 126 may be selected according to the type of material used for thesacrificial material 126. In accordance with some embodiments, for example, the material choice of thesacrificial material 126 is selected to that thesacrificial material 126 is easy to remove. - The
first patterns first material 116/122 and thesecond patterns second material 132 are then filled with athird material 140, as shown inFIG. 7 . Thethird material 140 comprises a conductive material in some embodiments, e.g., if thefirst material 116/122 and thesecond material 132 comprise insulating materials. Thethird material 140 may alternatively comprise a semiconductive material. Alternatively, thethird material 104 may comprise an insulator, e.g., if thefirst material 116/122 and thesecond material 132 comprise conductive or semiconductive materials. Thethird material 140 comprises a different type of material than thefirst material 116/122 and thesecond material 132, in some embodiments. - The
third material 140 may comprise a conductive material such as W, Cu, Al, TiN, Ti, TaN, other metals, or multiple layers, liners, or combinations thereof in some embodiments, for example, although alternatively, thethird material 140 may comprise other materials. Thethird material 140 may be formed using CVD, PVD, a sputter process, or other methods, as examples, although other methods may also be used to form thethird material 140. Thethird material 140 may be deposited having a top surface that extends over the top surface of thesecond material 132, as shown at 142 in phantom. A CMP process and/or etch process may be used to remove the excessthird material 140 from over the top surface of thesecond material 132, leavingfeatures first material 116/122 and thesecond material 132, as shown inFIG. 7 . Thethird material 140 may be planarized, for example. - The
features material 122, the second insulatingmaterial 132, and the stress-inducingmaterial 116, if present. Dimension d5 may comprise several hundred nm or less, for example, although alternatively, dimension d5 may comprise other values. - The
features transistor 120. For example, feature 140 a is coupled to thegate 108 of thetransistor 120, and feature 140 b is coupled to the source or drainregion 112 of thetransistor 120. Some features 140 a, 140 b, and 140 c may also be coupled to other devices or regions of theworkpiece 102. For example, feature 140 c is coupled to theisolation region 104 proximate thetransistor 120. - Conductive lines, not shown, may be formed over the
features features transistor 120 to other regions of thesemiconductor device 100 or to contact pads on a upper material layer of thesemiconductor device 100, which may be connected to for use in an end application, e.g., during packaging of thesemiconductor device 100, for example. - Thus, embodiments of the present invention provide novel methods of forming
features semiconductor device 100, wherein a two-step lithography process is used to form thepatterns features first material 116/122 and thesecond material 132. Thesacrificial material 126 fills thefirst patterns first material 116/122 during the formation of thesecond patterns second material 132. Advantageously, because thesecond patterns first patterns third material 140 is improved, avoiding the formation of voids within thepatterns second patterns first patterns - Embodiments of the present invention may also be implemented in semiconductor devices comprising multiple transistors. Embodiments of the present invention may be implemented in a CMOS device, on either the PMOS FET or the NMOS FET, or both, of a CMOS device.
FIGS. 8 through 11 illustrate cross-sectional views of an embodiment of the present invention implemented in both anNMOS FET 254 and aPMOS FET 258 of aCMOS device 250. Like numerals are used for the various elements that were described inFIGS. 1 through 7 . To avoid repetition, each reference number shown inFIGS. 8 through 11 is not described again in detail herein. Rather, similar materials x02, x04, x06, x08, etc. . . . are preferably used to describe the various material layers shown as were used to describeFIGS. 1 through 7 , where x=1 inFIGS. 1 through 7 and x=2 inFIGS. 8 through 11 . As an example, the materials and dimensions described for the stress-inducingmaterials 116 in the description forFIGS. 1 through 7 may also be used for the stress-inducingmaterials FIGS. 8 through 11 . - Referring next to
FIG. 8 , thesemiconductor device 200 includes aworkpiece 202 comprising afirst region 252 wherein theNFET 254 is formed and asecond region 256 wherein thePFET 258 is formed. A plurality ofNFETs 254 andPFETs 258 may be formed across the surface of theworkpiece 202, for example, not shown, in thefirst region 252 and thesecond region 256, or in a plurality offirst regions 252 andsecond regions 256. TheNFET 254 may comprise a first transistor and thePFET 258 may comprise a second transistor. Thefirst transistor 254 may alternatively comprise a PFET, and thesecond transistor 258 may alternatively comprise an NFET, for example. -
Sidewall spacers transistors first oxide liner nitride material oxide liners second oxide liner nitride material sidewall spacers - The source and drain
regions shallow implantation regions gates deeper implantation regions sidewall spacers - A
silicide regions gates silicide regions workpiece 202 to an annealing process. Any remaining silicidation metal after the anneal process may then be removed. - A first stress-inducing
material 216 a is disposed or formed over thefirst transistor 254 in thefirst region 252, and a second stress-inducingmaterial 216 b is disposed over thefirst transistor 254 in thesecond region 256, as shown inFIG. 9 . The second stress-inducingmaterial 216 b may be different than the first stress-inducingmaterial 216 a and may introduce a different amount or type of stress than the first stress-inducingmaterial 216 a, for example. The second stress-inducingmaterial 216 b may overlap the first stress-inducingmaterial 216 a in athird region 272 between thefirst region 252 and thesecond region 256, for example. - If the
first transistor 254 comprises an NFET, the first stress-inducingmaterial 216 a may comprise a nitride liner adapted to induce a tensile stress on thechannel region 214 a, for example. If thesecond transistor 258 comprises a PFET, the second stress-inducingmaterial 216 b may comprise a nitride liner adapted to induce a compressive stress on thechannel region 214 b, for example. Alternatively, the first and second stress-inducingmaterials - The first
insulating material 222 is formed over the first stress-inducingmaterial 216 a and the second stress-inducingmaterial 216 b, also shown inFIG. 9 . The firstinsulating material 222, the first stress-inducingmaterial 216 a, and the second stress-inducingmaterial 216 b are patterned with a first pattern for a lower portion of at least one conductive feature in at least thefirst region 252 and thesecond region 256. The first pattern in the first insulatingmaterial 222, the first stress-inducingmaterial 216 a, and the second stress-inducingmaterial 216 b is filled with asacrificial material 226, as shown inFIG. 10 . - A second insulating
material 232 is formed over the first insulatingmaterial 222 and thesacrificial material 226. The secondinsulating material 232 is patterned with a second pattern a pattern for an upper portion of the at least one conductive feature in at least thefirst region 252 and thesecond region 256. At least a portion of the second pattern is disposed over the first pattern in the first insulatingmaterial 222 and the first and second stress-inducingmaterials sacrificial material 226 is removed from within the first insulatingmaterial 222, the first stress-inducingmaterial 216 a, and the second stress-inducingmaterial 216 b. The first pattern in the first insulatingmaterial 222, the first stress-inducingmaterial 216 a, and the second stress-inducingmaterial 216 b and the second pattern in the second insulatingmaterial 232 are filled a conductive material 240, formingconductive features FIG. 11 . - The conductive features 240 a, 240 b, and 240 c may comprise a
conductive liner 274 and aconductive fill material 276 formed over theliner 274, for example. Theconductive liner 274 may comprise TaN, Ti, or TiN, and theconductive fill material 276 may comprise W in some embodiments, for example.Materials -
Conductive feature 240 a is coupled to thegate 208 b of thesecond transistor 258.Conductive feature 240 b is coupled to a source or drainregions 212 a of thefirst transistor 254.Conductive feature 240 c is coupled to theisolation region 204. A plurality ofconductive features workpiece 202, for example, not shown. Each of theconductive features semiconductor device 200, for example. - In some embodiments, patterning the first insulating
material 222, the first stress-inducingmaterial 216 a, and the second stress-inducingmaterial 216 b with the first pattern for the lower portion of the at least oneconductive feature first region 252 and thesecond region 256 may further comprise removing the second stress-inducingmaterial 216 b and the first stress-inducingmaterial 216 a in the third region. This may be advantageous in some applications wherein leaving the second stress-inducingmaterial 216 b over the first stress-inducingmaterial 216 a may have deleterious effects on the stress of thesemiconductor device 200, for example. - The manufacturing process for the
semiconductor device 200 is then continued to complete the fabrication of thedevice 200. Metallization layers (not shown) may be formed over the second insulatingmaterial 232 to interconnect the various components of thesemiconductor device 200. Thesemiconductor device 200 may be annealed to activate the dopants implanted during the various implantation steps, for example, e.g., such asimplantation regions regions - Embodiments of the present invention may be implemented in applications where transistors are used, as described herein and shown in the figures. One example of a memory device that embodiments of the present invention may be implemented in that uses both PMOS FET's and NMOS FET's is a static random access memory (SRAM) device. A typical SRAM device includes arrays of thousands of SRAM cells, for example. Each SRAM cell may have four or six transistors, for example, although other numbers of transistors may also be used. A commonly used SRAM cell is a six-transistor (6T) SRAM cell, which has two PMOS FET's interconnected with four NMOS FET's, as one example. The novel methods of forming source and drain regions and structures thereof described herein may be implemented in the manufacturing process of SRAM devices and other memory devices, for example.
- Embodiments of the present invention include methods of forming features and methods of fabricating the
semiconductor devices semiconductor devices - Advantages of embodiments of the present invention include providing novel structures and methods for forming
features semiconductor devices conductive features first material 116/122 and 216 a/216 b/222 and thesecond material - Embodiments of the present invention are easily implementable in existing manufacturing process flows, with a small or reduced number of additional processing steps being required, for example. Embodiments of the present invention are particularly beneficial in technology nodes having very small minimum feature sizes, such as about 45 nm and below, for example.
- Shorts that may form
proximate gates partial material layers conductive features - The patterns for the
conductive features improved device first material 116/122 and 216 a/216 b/222 and thesecond material conductive features - The methods described herein result in reduced diversity in contact hole types or species, e.g., between gate contacts, source and drain contacts, and isolation region contacts. A process window for forming the
conductive features - Although embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present invention. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (20)
1. A semiconductor device comprising:
a workpiece including a conductive region;
a first insulating material disposed over the workpiece;
a first opening for a first portion of a conductive feature disposed within the first insulating material;
a second insulating material disposed over the first insulating material;
a second opening for a second portion of the conductive feature disposed in the second insulating material; and
a conductive material filling the first opening and the second opening to form the conductive feature, wherein the conductive feature is electrically coupled to the conductive region, wherein the first portion of the conductive feature comprises a first width in the first insulating material, and wherein the second portion of the conductive feature comprises a second width in at least a portion of the second insulating material, the second width being greater than the first width.
2. The device according to claim 1 , wherein the conductive feature comprises substantially the first width in a bottom portion of the second insulating material.
3. The device according to claim 1 , wherein the conductive feature comprises substantially the second width in a top portion of the second insulating material.
4. The device according to claim 1 , wherein the second opening comprises tapered sidewalls in the second insulating material.
5. The device according to claim 1 , wherein the first insulating material comprises a stress-inducing material and an insulating material disposed over the stress-inducing material.
6. The device according to claim 1 , wherein the conductive material comprises a liner continuously lining sidewalls of the first opening and the second opening.
7. The device according to claim 6 , wherein the liner is disposed over a bottom surface of the first opening.
8. A semiconductor device comprising:
a first insulating material disposed over a workpiece having a conductive region;
a second insulating material disposed over the first insulating material;
a first opening disposed within the first insulating material, wherein at least a portion of the first opening comprises a first width;
a second opening disposed in the second insulating material, wherein at least a portion of the second opening comprises a second width, the second width being greater than the first width, the second opening and the first opening forming a first single continuous opening; and
a conductive material filling the first opening and the second opening, wherein the conductive material filling the first opening and the second opening is electrically coupled to the conductive region.
9. The device according to claim 8 , wherein the first opening comprises substantially the first width in a bottom portion of the second insulating material.
10. The device according to claim 8 , wherein the second opening comprises tapered sidewalls in the second insulating material.
11. The device according to claim 8 , wherein the first insulating material comprises a stress-inducing material and an insulating material disposed over the stress-inducing material.
12. The device according to claim 8 , wherein the conductive material comprises a liner continuously lining sidewalls of the first opening and the second opening.
13. The device according to claim 12 , wherein the liner is disposed over a bottom surface of the first opening.
14. The device according to claim 8 , further comprising:
a gate electrode disposed over the workpiece;
a third opening disposed within the first insulating material, the third opening disposed over the gate electrode, wherein at least a portion of the third opening comprises a third width; and
a fourth opening disposed in the second insulating material, wherein at least a portion of the fourth opening comprises a fourth width, the fourth width being greater than the third width, the fourth opening and the third opening forming a second single continuous opening, wherein the conductive material fills the third opening and the fourth opening, and wherein the conductive material filling the third opening and the fourth opening electrically couples to the gate electrode.
15. A semiconductor device comprising:
a first insulating material disposed over a workpiece;
a second insulating material disposed over the first insulating material;
a gate electrode disposed over the workpiece;
a first opening disposed in the first insulating material, the first opening disposed over the gate electrode, wherein at least a portion of the first opening comprises a first width;
a second opening disposed in the second insulating material, wherein at least a portion of the second opening comprises a second width, the second width being greater than the first width, the second opening and the first opening forming a first single continuous opening; and
a conductive material filling the first opening and the second opening, wherein the conductive material filling the first opening and the second opening is electrically coupled to the gate electrode.
16. The device according to claim 15 , wherein the second opening has a tapered sidewall.
17. The device according to claim 15 , wherein the first opening comprises substantially the first width in a bottom portion of the second insulating material.
18. The device according to claim 15 , wherein the second opening comprises tapered sidewalls in the second insulating material.
19. The device according to claim 15 , wherein the conductive material comprises a liner continuously lining sidewalls of the first opening and the second opening, wherein the liner is disposed over a bottom surface of the first opening.
20. The device according to claim 15 , further comprising:
a third opening disposed within the first insulating material, the third opening disposed over a conductive region of the workpiece, wherein at least a portion of the third opening comprises a third width; and
a fourth opening disposed in the second insulating material, wherein at least a portion of the fourth opening comprises a fourth width, the fourth width being greater than the third width, the fourth opening and the third opening forming a second single continuous opening, wherein the conductive material fills the third opening and the fourth opening, and wherein the conductive material filling the third opening and the fourth opening electrically couples to the conductive region.
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US13/074,888 US20110175148A1 (en) | 2008-05-29 | 2011-03-29 | Methods of Forming Conductive Features and Structures Thereof |
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US12/129,479 US7947606B2 (en) | 2008-05-29 | 2008-05-29 | Methods of forming conductive features and structures thereof |
US13/074,888 US20110175148A1 (en) | 2008-05-29 | 2011-03-29 | Methods of Forming Conductive Features and Structures Thereof |
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Also Published As
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US7947606B2 (en) | 2011-05-24 |
US20090294986A1 (en) | 2009-12-03 |
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