CN104104434A - Power failure alarm implementation method capable of rapidly inserting alarm frame - Google Patents
Power failure alarm implementation method capable of rapidly inserting alarm frame Download PDFInfo
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- CN104104434A CN104104434A CN201410356223.1A CN201410356223A CN104104434A CN 104104434 A CN104104434 A CN 104104434A CN 201410356223 A CN201410356223 A CN 201410356223A CN 104104434 A CN104104434 A CN 104104434A
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Abstract
The invention discloses a power failure alarm implementation method capable of rapidly inserting an alarm frame. The power failure alarm implementation method capable of rapidly inserting the alarm frame includes: receiving an input signal of a power failure detection circuit in real time through a field programmable gate array (FPGA); when the FPGA receives a power failure alarm signal output by the power failure detection circuit, cutting off normal power supplies of power consumption modules except an optical module, preempting a normal business flow channel from a system business processing module to the optical module, and guaranteeing that the alarm frame is sent out through the optical module within power supply time. The power failure alarm implementation method capable of rapidly inserting the alarm frame guarantees that a device can constantly, accurately and successfully send the power failure alarm frame under the critical failure of power failure, and reduces the requirement for energy storage circuit cost.
Description
Technical field
The present invention relates to communication technical field, relate in particular to a kind of power fail warning implementation method of quick insertion alarm frame.
Background technology
Along with the transition to packet-switch technology by traditional SDH (SDH (Synchronous Digital Hierarchy)) technology of operation bearer network, be exchanged for the large-scale application of packet carrying network of core with packet label.Off the net at packet bearer, produce packet access terminal equipment.In the network of operator, can administer and maintain performance to the network equipment and have higher performance requirement, requirement possess higher can telemanagement ability, requirement can be carried out monitoring constantly to the running status of equipment, in the time of device looses power, can on webmaster, find corresponding alarm (being commonly called as power fail warning), be convenient to locating network fault fast, recover fast network unimpeded.The power fail warning of block terminal access device requires to adopt two kinds of modes, and one is based on fatal event report and alarm in IEEE802.3ah agreement OAM (being commonly called as two layers of power fail warning of Ethernet); Another kind is the alarm report mechanism (being commonly called as three layers of power fail warning of Ethernet) based on SNMP TRAP.The core of two kinds of modes is all that access device detects that sending Ethernet message after power down sends warning information.
Access device is Ethernet (two layers or the three layers) power fail warning of realizing self, traditional solution as shown in Figure 1, the built-in power-fail detection circuit of equipment, central processing unit (CPU) detect power-fail detection circuit send power fail warning signal after organize power fail warning Ethernet message, then warning message is sent to Packet Service processing module, warning message will send from physical port (PHY) through interface module in Packet Service processing module (SWITCH) after queuing up, store and forwarding.
As everyone knows, above-mentioned several devices (CPU, SWITCH, PHY) power consumption is all larger, and the exemplary power (P) of mini-plant is in 40W left and right.In the time that device power supply (DPS) is abnormal, CPU module detects by poll or interruption the power fail warning signal that circuit sends, then organize power fail warning frame, alarm frame by SWITCH channel queue, storage and forwarding after through PHY drive optical interface send, generally send the time (t) of alarm frame needs up to 15ms, for ensureing to send out frame success rate, we calculate transmitting time (t) by running fire 5 frames is 75ms.If the input voltage (U1) while normally work according to circuit is 5V, the minimum input voltage (U2) that can normally work is 3.3V calculating, in traditional circuit, need storage capacitor C (C=2Pt/ (U12-U22)) to reach 0.4F, need to just can meet design requirement with farad capacitor, thereby cause equipment cost higher.
Summary of the invention
The object of this invention is to provide a kind of power fail warning implementation method of quick insertion alarm frame, guarantee that equipment can constantly, accurately, successfully send power fail warning frame under this critical failure of power down, reduce the demand to accumulator cost.
The object of the invention is to be achieved through the following technical solutions:
A power fail warning implementation method for quick insertion alarm frame, the method comprises:
Receive in real time the output signal of power-fail detection circuit by on-site programmable gate array FPGA;
In the time that described FPGA receives the power fail warning signal of power-fail detection circuit output, cut off the normal power supply of other power consumption modules outside optical module, and seize system business processing module to the regular traffic circulation road between optical module, guarantee by described optical module, power fail warning frame outwards to be sent in power-on time.
As seen from the above technical solution provided by the invention, kidnap the power fail warning implementation method dependable performance of light sendaisle quick insertion alarm frame based on FPGA, the scope of application is very extensive, guarantee that equipment can constantly, accurately, successfully send power fail warning frame under this critical failure of power down, reduce the demand to accumulator cost.
Brief description of the drawings
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing of required use during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain other accompanying drawings according to these accompanying drawings.
The schematic diagram of the conventional power down alarm solution that Fig. 1 provides for background technology of the present invention;
The schematic diagram of the power fail warning implementation method of a kind of quick insertion alarm frame that Fig. 2 provides for the embodiment of the present invention;
The schematic diagram of the FPGA realization of functions that Fig. 3 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiment.Based on embodiments of the invention, those of ordinary skill in the art, not making the every other embodiment obtaining under creative work prerequisite, belong to protection scope of the present invention.
Embodiment
The embodiment of the present invention provides a kind of power fail warning implementation method of quick insertion alarm frame, and the method comprises:
Receive in real time the output signal of power-fail detection circuit by FPGA (field programmable gate array);
In the time that described FPGA receives the power fail warning signal of power-fail detection circuit output, cut off the normal power supply of other power consumption modules outside optical module, and seize system business processing module to the regular traffic circulation road between optical module, guarantee by described optical module, power fail warning frame outwards to be sent in power-on time.
Further, it is described in the time that described FPGA receives the power fail warning signal of power-fail detection circuit output, the normal power supply that cuts off other power consumption modules outside optical module comprises: described in the time that described FPGA receives the power fail warning signal of power-fail detection circuit output, send control signal to power switch circuit, the module of cutting off the electricity supply is to the normal power supply of other power consumption modules outside optical module.
Further, the method also comprises: in the time that described FPGA receives the power fail warning signal of power-fail detection circuit output, and buffer memory power fail warning frame therein.
The FPGA that the embodiment of the present invention provides kidnaps the implementation method of the power fail warning of light sendaisle quick insertion alarm frame, in the time that FPGA detects that this fatal error of power down occurs, the power supply of cut-out equipment high power module, seizes optical channel, sends fast in time power fail warning frame.The present invention has reduced the requirement of equipment to energy storage, thereby has reduced the hardware cost (FPGA used completes other system function conventionally simultaneously, does not therefore need additionally to increase cost) of power-fail detection circuit part
For the ease of understanding, below in conjunction with accompanying drawing, 2-3 is described further.
As shown in Figure 2, FPGA connects optical interface sending module and nested design Service Processing Module, and signal input part, control signal output are corresponding is respectively connected with power-fail detection circuit, power switch circuit.
In the time detecting that power-fail detection circuit output power-off signal is normal, this FPGA ensures the normal transmission of nested design Service Processing Module to Business Stream between optical interface sending module.
In the time detecting that power-fail detection circuit output power-off signal is normal, (power-fail detection circuit output power fail warning detected), FPGA cuts off the power supply of the highly energy-consuming components and parts such as CPU, PHY, SWITCH, ensures FPGA, optical module normal power supply time.FPGA, the needed power of optical module (P) only need 2W left and right.Meanwhile, FPGA seizes regular traffic circulation road, organizes rapidly the transmission of power fail warning frame.It is very fast that FPGA sends out frame time, calculates according to 25M clock and long 64 bytes of parcel, and need to send out frame time (t) be 0.006ms, we equally as required running fire 5 frames to calculate a frame time (t) be 0.03ms.Input voltage (U1) while normally work according to circuit is equally 5V, the minimum input voltage (U2) that can normally work is 3.3V calculating, and in the present invention, normal energy storage capacitor C (C=2Pt/ (U12-U22)) only needs 9uF just can meet the designing requirement on circuit.In practicality, power supply coupling capacitor is much larger than 9uF, therefore without increase special accumulator for detection of power loss.
Specifically, in the embodiment of the present invention, FPGA is mainly achieved as follows function (referring to Fig. 3):
1) FPGA receives power-fail detection circuit output signal, real-time judge device power supply (DPS) operating state.
2) FPGA connects optical interface sending module and nested design Service Processing Module.In the time detecting that power-fail detection circuit output power-off signal is normal, ensure the normal transmission of nested design Service Processing Module to Business Stream between optical interface sending module.
3) FPGA connects power switch circuit, controls flexibly power switch circuit, exports when normal at device looses power testing circuit, ensures the normal power source power supply of relevant connection module.In the time power-fail detection circuit output power fail warning being detected, control in time the module of cutting off the electricity supply to the normal power supply of the high-power power consumption module of equipment, make equipment enter low-power consumption battery saving mode, ensure the power-on time of FPGA and optical module.
4) in the time power-fail detection circuit output power fail warning being detected, FPGA inner buffer power fail warning frame.
5) FPGA, in the time the alarm of power-fail detection circuit out-put supply being detected, cuts off and seizes system business processing module immediately to the regular traffic circulation road between optical module, and sends in real time the power fail warning message in buffer memory in power-on time.
In the embodiment of the present invention, kidnap the power fail warning implementation method dependable performance of light sendaisle quick insertion alarm frame based on FPGA, the scope of application is very extensive, guarantee that equipment can constantly, accurately, successfully send power fail warning frame under this critical failure of power down, reduce the demand to accumulator cost.
The above; only for preferably embodiment of the present invention, but protection scope of the present invention is not limited to this, is anyly familiar with in technical scope that those skilled in the art disclose in the present invention; the variation that can expect easily or replacement, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claims.
Claims (3)
1. a power fail warning implementation method for quick insertion alarm frame, is characterized in that, the method comprises:
Receive in real time the output signal of power-fail detection circuit by on-site programmable gate array FPGA;
In the time that described FPGA receives the power fail warning signal of power-fail detection circuit output, cut off the normal power supply of other power consumption modules outside optical module, and seize system business processing module to the regular traffic circulation road between optical module, guarantee by described optical module, power fail warning frame outwards to be sent in power-on time.
2. method according to claim 1, is characterized in that, described in the time that described FPGA receives the power fail warning signal of power-fail detection circuit output, the normal power supply that cuts off other power consumption modules outside optical module comprises:
Describedly in the time that described FPGA receives the power fail warning signal of power-fail detection circuit output, send control signal to power switch circuit, the module of cutting off the electricity supply is to the normal power supply of other power consumption modules outside optical module.
3. method according to claim 1, is characterized in that, the method also comprises:
In the time that described FPGA receives the power fail warning signal of power-fail detection circuit output, buffer memory power fail warning frame therein.
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Cited By (9)
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| CN106033997A (en) * | 2015-03-20 | 2016-10-19 | 中兴通讯股份有限公司 | Processing method and device for power-off alarms and terminal |
| CN106201775A (en) * | 2016-06-24 | 2016-12-07 | 广东电网有限责任公司电力科学研究院 | A kind of information power-down protection apparatus, guard method and embedded system |
| CN107507405A (en) * | 2017-09-22 | 2017-12-22 | 烽火通信科技股份有限公司 | Reduce the method and system of power fail warning handling duration |
| CN108882270A (en) * | 2018-06-26 | 2018-11-23 | 新华三技术有限公司 | A kind of network equipment and device management method |
| CN109257185A (en) * | 2018-11-21 | 2019-01-22 | 新华三技术有限公司 | A kind of network equipment, service card, logic device and notification information transmission method |
| CN109347685A (en) * | 2018-11-21 | 2019-02-15 | 新华三技术有限公司 | A kind of network equipment, logic device and notification information transmission method |
| CN112087258A (en) * | 2019-06-13 | 2020-12-15 | 青岛海信宽带多媒体技术有限公司 | Optical module |
| CN114124690A (en) * | 2021-08-30 | 2022-03-01 | 济南浪潮数据技术有限公司 | Alarm configuration method, system and related device for data center |
| CN116963135A (en) * | 2023-09-20 | 2023-10-27 | 四川恒湾科技有限公司 | O-RU power failure alarm reporting method, device and system |
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| CN107507405A (en) * | 2017-09-22 | 2017-12-22 | 烽火通信科技股份有限公司 | Reduce the method and system of power fail warning handling duration |
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| CN108882270A (en) * | 2018-06-26 | 2018-11-23 | 新华三技术有限公司 | A kind of network equipment and device management method |
| CN109257185A (en) * | 2018-11-21 | 2019-01-22 | 新华三技术有限公司 | A kind of network equipment, service card, logic device and notification information transmission method |
| CN109347685A (en) * | 2018-11-21 | 2019-02-15 | 新华三技术有限公司 | A kind of network equipment, logic device and notification information transmission method |
| CN109347685B (en) * | 2018-11-21 | 2021-01-26 | 新华三技术有限公司 | Network equipment, logic device and notification information transmission method |
| CN112087258A (en) * | 2019-06-13 | 2020-12-15 | 青岛海信宽带多媒体技术有限公司 | Optical module |
| WO2020248743A1 (en) * | 2019-06-13 | 2020-12-17 | 青岛海信宽带多媒体技术有限公司 | Optical module |
| CN112087258B (en) * | 2019-06-13 | 2022-06-10 | 青岛海信宽带多媒体技术有限公司 | Optical module |
| CN114124690A (en) * | 2021-08-30 | 2022-03-01 | 济南浪潮数据技术有限公司 | Alarm configuration method, system and related device for data center |
| CN116963135A (en) * | 2023-09-20 | 2023-10-27 | 四川恒湾科技有限公司 | O-RU power failure alarm reporting method, device and system |
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