CN104103649A - Grid array type SOI photoelectric detector with resonant cavity enhancement effects - Google Patents
Grid array type SOI photoelectric detector with resonant cavity enhancement effects Download PDFInfo
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- CN104103649A CN104103649A CN201410353119.7A CN201410353119A CN104103649A CN 104103649 A CN104103649 A CN 104103649A CN 201410353119 A CN201410353119 A CN 201410353119A CN 104103649 A CN104103649 A CN 104103649A
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Abstract
The invention discloses a grid array type SOI photoelectric detector with resonant cavity enhancement effects. The grid array type SOI photoelectric detector with the resonant cavity enhancement effects solves the problem that semiconductor CMOS technology of an existing CMOS photoelectric detector structure limits improvements of device structures and electrical properties. The grid array type SOI photoelectric detector with the resonant cavity enhancement effects comprises a P-type semiconductor substrate, a buried oxidation layer, an N-type doping region, a P-type ohm contact region, an annular ground electrode, an annular voltage electrode, an N-type ohm contact region, an output electrode, a grid array type PCOMP, a top oxidation layer and polycrystalline silicon. According to the grid array type SOI photoelectric detector with the resonant cavity enhancement effects, the problem that quantum efficiency and responsiveness restrict each other due to the thickness of an absorbing layer is solved, performance of the grid array type SOI photoelectric detector with the resonant cavity enhancement effects is greatly improved, an application field is greatly broadened, the size of a photoelectric system is decreased, weight of the photoelectric system is reduced, performance and reliability of the photoelectric system are improved, and simultaneously resource saving is facilitated.
Description
Technical field
The invention belongs to technical field of semiconductors, relate to a kind of SOI photodetector with resonant cavity enhancement effect grid array type.
Background technology
Because the continuous growth of optical fiber communication, infrared remote sensing and Military Application demand has promoted the development of semiconductor part and optical circuit thereof.Along with the continuous embodiment of optical circuit system powerful advantages, photoelectric device and circuit thereof have a wide range of applications in fields such as computing system, free space satellite system, optical disc storage application, imaging system and communication systems.Consider the compatibility of CMOS technique, traditional Si base photodetector is that the injection of carrying out N-shaped ion on Si substrate forms n well region (n-well), closes on the source region that forms p between n well region, at the metal lead wire of source region Base top contact electrode in substrate top; In n well region, carry out p-type Implantation by grid array type and form the PCOMP of grid array type, generate the ohmic contact regions of n in the part at PCOMP and n well region edge, and at the metal lead wire of ohmic contact regions Base top contact electrode; Form the ohmic contact regions of p at each PCOMP top, and at the metal lead wire of the Base top contact electrode of ohmic contact regions.Traditional cmos photodetector is because the absorption coefficient of Si is lower, thereby quantum efficiency is low, if improve quantum efficiency by increasing absorber thickness, can make bandwidth greatly reduce, and is unfavorable for improving the composite characteristic of device and system.Along with the development of semiconductor technology and TCAD, adopt spatial modulation (SML), the horizontal isostructural CMOS photodetector of PIN to be subject to CMOS process technology limit, responsiveness and bandwidth cannot further meet the demand of the light interconnection such as ultrahigh speed short distance.In order to realize the more photodetector of high-responsivity and bandwidth, researcher has also proposed avalanche breakdown photodetector (APD) structure based on silicon CMOS technique, the performance such as responsiveness and frequency bandwidth of this structure is all better, weak point is that photodetector need to apply high reverse biased, has limited photodetector application scope greatly.
Summary of the invention
The present invention is directed to the deficiencies in the prior art, a kind of SOI photodetector with resonant cavity enhancement effect grid array type is provided, by introducing Fabry-spread out chamber, utilize grid array type structure simultaneously, increase depletion region area, quantum efficiency is increased greatly, can not make Bandwidth Reduction simultaneously, this device can be realized in SOI CMOS technique, concrete well processing compatibility, thus can integrate and form electro-optical system on optoelectronic integrated circuit chip or sheet with common cmos device; Compare other CMOS compatible photodetectors simultaneously, there is high-quantum efficiency, high-responsivity and high bandwidth feature.
A kind of SOI photodetector with resonant cavity enhancement effect grid array type of the present invention, comprises p-type Semiconductor substrate, buries oxide layer, N-shaped n-well well region, p-type ohmic contact regions, PCOMP, top layer oxide layer and the polysilicon of electrode, annular voltage pole, N-shaped ohmic contact regions, output electrode, grid array type circlewise;
Be provided with and bury oxide layer apart from p-type semiconductor substrate surface 2 um places, p-type Semiconductor substrate upper surface is provided with N-shaped n-well well region, annular p-type ohmic contact regions is arranged on p-type Semiconductor substrate upper surface and is positioned at N-shaped n-well well region outside, electrode is arranged on annular p-type ohmic contact regions circlewise, be arranged on p-type Semiconductor substrate upper surface in annular N-shaped ohmic contact regions and be positioned at N-shaped n-well well region inner side, annular voltage pole is arranged on annular N-shaped ohmic contact regions, at p-type Semiconductor substrate upper surface and be positioned at annular voltage pole inner side and be provided with the PCOMP of grid array type, the output electrode of grid type is set on the PCOMP of grid array type, between each electrode of p-type Semiconductor substrate 1 upper surface, cover layer of oxide layer, at surface coverage one deck polysilicon of oxide layer,
Described p-type Semiconductor substrate is Sapphire Substrate or silicon substrate;
The described oxidated layer thickness that buries is 140nm;
Described N-shaped n-well well region thickness is 1.5um;
The PCOMP thickness of described grid array type is 1um;
The oxidated layer thickness of described top layer is 140nm;
Described polysilicon thickness is 60nm;
The material of described electrode circlewise, annular voltage pole and output electrode is respectively the one of Al or Cu;
Distance between described each PCOMP is 1um.
The described epitaxial growth mode of burying oxide layer, N-shaped n-well well region, the PCOMP of grid array type, HenXing ohmic contact regions, annular p-type ohmic contact regions adopts note oxygen isolation (SIMOX) method to realize.
The present invention, by introducing Fabry-spread out chamber, makes light wave reciprocating motion in cavity, thereby makes light wave Multiple through then out absorbed layer reach photoelectricity enhancement effect, and device can obtain higher quantum efficiency.Utilize grid array type structure, increase depletion region area, simultaneously because absorbed layer is thinner, the transit time of the electron-hole pair that photo-generated carrier produces in absorbed layer is less, can make device obtain higher bandwidth, solve between the quantum efficiency of photodetector and bandwidth the problem of restriction mutually.
In the inventive method, epitaxial growth adopts note oxygen isolation (SIMOX) method to realize, and inventive point of the present invention is, the longitudinally change of (three-dimensional) structure horizontal to photodetector based on SOI CMOS technique.
Beneficial effect: the present invention, by changing horizontal, longitudinal (three-dimensional) structure of photodetector, makes this new device have higher responsiveness and bandwidth in the time working as photodetector.
Brief description of the drawings
Fig. 1 is structural representation of the present invention;
Fig. 2 is the vertical view of Fig. 1;
Fig. 3 is the A-A schematic cross-section of Fig. 1;
Fig. 4 is the B-B schematic cross-section of Fig. 1.
Embodiment
As shown in Fig. 1,2,3 and 4, there is a SOI photodetector for resonant cavity enhancement effect grid array type, comprise p-type Semiconductor substrate 1, bury oxide layer 2, N-shaped n-well well region 3, p-type ohmic contact regions 4, PCOMP 9, top layer oxide layer 11 and the polysilicon 10 of electrode 5, annular voltage pole 6, N-shaped ohmic contact regions 7, output electrode 8, grid array type circlewise;
Apart from the surperficial 2 um places of p-type Semiconductor substrate 1 be provided with thickness be 140nm bury oxide layer 2, p-type Semiconductor substrate 1 upper surface is provided with the N-shaped n-well well region 3 that thickness is 1.5um, annular p-type ohmic contact regions 4 is arranged on p-type Semiconductor substrate upper surface and is positioned at N-shaped n-well well region outside, electrode 5 is arranged on annular p-type ohmic contact regions circlewise, the N-shaped ohmic contact regions 7 of annular is arranged on p-type Semiconductor substrate upper surface and is positioned at N-shaped n-well well region inner side, annular voltage pole 6 is arranged on annular N-shaped ohmic contact regions, at p-type Semiconductor substrate upper surface and be positioned at annular voltage pole 6 inner sides and be provided with the PCOMP 9 that thickness is the grid array type of 1um, the output electrode 8 of grid type is set on the PCOMP of grid array type, between each electrode of p-type Semiconductor substrate 1 upper surface, cover the oxide layer 11 that a layer thickness is 140nm, the polysilicon 10 that is 60nm in surface coverage a layer thickness of oxide layer.
Described p-type Semiconductor substrate is silicon substrate;
Distance between described each PCOMP is 1um;
The material of described electrode circlewise, annular voltage pole and output electrode is all Cu;
The described epitaxial growth mode of burying oxide layer, N-shaped n-well well region, the PCOMP of grid array type, HenXing ohmic contact regions, annular p-type ohmic contact regions adopts injection oxygen isolation technology (SIMOX) method to realize.
When photon incides photosensitive equipment surperficial, absorbed part photon can excite photosensitive material production electron-hole pair, forms electric current, is called photoelectric effect, and the electronics now producing is called quantum efficiency with the ratio of the number of photons of all incidents.The quantum efficiency computing formula of normal optical electric explorer
, the computing formula of the quantum efficiency of resonant cavity type photodetector
, wherein r
1, r
2for the reflection coefficient of the upper and lower minute surface of resonant cavity,
for the absorption coefficient of material, L is depletion layer thickness.In resonant cavity, owing to choosing suitable mirror up and down, it is large that reflection coefficient becomes, the structure of grid array type can increase the effective area of depletion layer simultaneously, but the motion for charge carrier can not cause delay, thereby can in the time of thin depletion layer, obtain larger quantum efficiency, ensure that bandwidth can not narrow simultaneously.When top mirror is a pair of Si-SiO2, when end mirror is three couples of Si-SiO2, can be calculated by formula
=0.325, be the 2-3 of normal optical electric explorer doubly.This is the method for having supported theoretically to improve with the cavity resonator structure of grid array type device quantum efficiency, has higher responsiveness when device is interconnected for light.
Claims (10)
1. there is a SOI photodetector for resonant cavity enhancement effect grid array type, comprise p-type Semiconductor substrate, bury oxide layer, N-shaped n-well well region, p-type ohmic contact regions, PCOMP, top layer oxide layer and the polysilicon of electrode, annular voltage pole, N-shaped ohmic contact regions, output electrode, grid array type circlewise;
It is characterized in that: be provided with and bury oxide layer apart from p-type semiconductor substrate surface 2 um places, p-type Semiconductor substrate upper surface is provided with N-shaped n-well well region, annular p-type ohmic contact regions is arranged on p-type Semiconductor substrate upper surface and is positioned at N-shaped n-well well region outside, electrode is arranged on annular p-type ohmic contact regions circlewise, be arranged on p-type Semiconductor substrate upper surface in annular N-shaped ohmic contact regions and be positioned at N-shaped n-well well region inner side, annular voltage pole is arranged on annular N-shaped ohmic contact regions, at p-type Semiconductor substrate upper surface and be positioned at annular voltage pole inner side and be provided with square matrix-shaped PCOMP, the output electrode of grid type is set on the PCOMP of grid array shape, between each electrode of p-type Semiconductor substrate 1 upper surface, cover layer of oxide layer, at surface coverage one deck polysilicon of oxide layer.
2. a kind of SOI photodetector with resonant cavity enhancement effect grid array type according to claim 1, is characterized in that: described p-type Semiconductor substrate is Sapphire Substrate or silicon substrate.
3. a kind of SOI photodetector with resonant cavity enhancement effect grid array type according to claim 1, is characterized in that: the described oxidated layer thickness that buries is 140nm.
4. a kind of SOI photodetector with resonant cavity enhancement effect grid array type according to claim 1, is characterized in that: described N-shaped n-well well region thickness is 1.5um.
5. a kind of SOI photodetector with resonant cavity enhancement effect grid array type according to claim 1, is characterized in that: the PCOMP thickness of described grid array shape is 1um.
6. a kind of SOI photodetector with resonant cavity enhancement effect grid array type according to claim 1, is characterized in that: the oxidated layer thickness of described top layer is 140nm.
7. a kind of SOI photodetector with resonant cavity enhancement effect grid array type according to claim 1, is characterized in that: described polysilicon thickness is 60nm.
8. a kind of SOI photodetector with resonant cavity enhancement effect grid array type according to claim 1, is characterized in that: the material of described electrode circlewise, annular voltage pole and output electrode is respectively the one of Al or Cu.
9. a kind of SOI photodetector with resonant cavity enhancement effect grid array type according to claim 1, is characterized in that: the distance between each PCOMP is 1um.
10. a kind of SOI photodetector with resonant cavity enhancement effect grid array type according to claim 1, is characterized in that: the described epitaxial growth mode of burying oxide layer, N-shaped n-well well region, the PCOMP of grid array shape, HenXing ohmic contact regions, annular p-type ohmic contact regions adopts note oxygen partition method to realize.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111710751A (en) * | 2020-06-24 | 2020-09-25 | 中国电子科技集团公司第二十四研究所 | Silicon-based germanium avalanche photodetector array and preparation method thereof |
| CN112701128A (en) * | 2020-12-29 | 2021-04-23 | 上海烨映微电子科技股份有限公司 | SON structure and preparation method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111710751A (en) * | 2020-06-24 | 2020-09-25 | 中国电子科技集团公司第二十四研究所 | Silicon-based germanium avalanche photodetector array and preparation method thereof |
| CN112701128A (en) * | 2020-12-29 | 2021-04-23 | 上海烨映微电子科技股份有限公司 | SON structure and preparation method thereof |
| CN112701128B (en) * | 2020-12-29 | 2022-04-19 | 上海烨映微电子科技股份有限公司 | SON structure and preparation method thereof |
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Application publication date: 20141015 |