CN104103588A - Method for manufacturing COMS device - Google Patents
Method for manufacturing COMS device Download PDFInfo
- Publication number
- CN104103588A CN104103588A CN201310124021.XA CN201310124021A CN104103588A CN 104103588 A CN104103588 A CN 104103588A CN 201310124021 A CN201310124021 A CN 201310124021A CN 104103588 A CN104103588 A CN 104103588A
- Authority
- CN
- China
- Prior art keywords
- grid
- active area
- type
- layer
- shallow trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
Abstract
The invention discloses a method for manufacturing a COMS device. The method includes: forming a shallow trench filed oxide and well regions; growing a gate oxide and a polycrystalline silicon layer in sequence and performing N type and P type ion implantation on the polycrystalline silicon layer, and performing photoetching to form grid electrodes, the grid electrodes including a first grid electrode and a second grid electrode which are in contact; forming source and drain regions; forming an interlayer film; performing photoetching to form an elongated hole which crosses a contact interface of the first grid electrode and the second grid electrode to realize simultaneous contact with the first grid electrode and the second grid electrode. The method for manufacturing the COMS device in the invention omits the step of adopting a metal silicide to realize grid electrode interconnection of NMOS and PMOS devices, thereby reducing parasitic resistance and capacitance between the contact hole and the grid electrodes and improving the speed of the device, the problem of polycrystalline silicon exhaustion caused by boron dosage concentration reduction and boron reduction of the PMOS device can be eliminated, and introduction of metallic elements before formation of the contact hole can be eliminated, thereby improving reliability of the device.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, particularly relate to a kind of manufacture method of cmos device.
Background technology
In the method for manufacturing technology of existing cmos device, method is to utilize at the upper deposition of polysilicon (poly) one deck conductive metal layer of grid to realize N-type MOS(NMOS) and P type MOS(PMOS) a gate interconnect, mostly the conducting metal of existing gate interconnect is tungsten silicide (WSi) and autoregistration cobalt silicide (Co salicide).
As shown in Figure 1, be the vertical view of the cmos device of existing method formation; Fig. 2 is the cutaway view along the cmos device of AA ' line in Fig. 1; Existing method comprises step:
Utilize chemical wet etching technique to form shallow trench on silicon substrate 101, by described shallow trench, define active area; In described shallow trench, fill silica and form shallow trench field oxygen 104, by 104 pairs of described active areas of oxygen, described shallow trench field, isolated.
Surfaces of active regions growth one deck sacrificial oxide layer at described silicon substrate 101, and carry out particle and be infused in and in active area, form P type well region 102 and N-type well region 103, the active area that makes P type well region 102 is the first active area, and the active area of N-type well region 103 is the second active area.
In the front of described silicon substrate 101, utilize wet method to get rid of sacrificial oxide layer, and one deck gate oxide 105 of growing, then deposit one deck polysilicon layer (Poly Si), the implantation of carrying out subsequently the impurity of N-type polysilicon 106 and P type polysilicon 107 is Implantation, on forming, deposit layer of metal tungsten silicide 108 and one deck silicon nitride on polysilicon layer, utilize dry etching to form grid.As illustrated in fig. 1 and 2, the metal silication tungsten 108 of grid after by etching and N-type polysilicon 106 and the P type polysilicon 107 of its bottom form, wherein N-type polysilicon 106 is used to form the first grid of nmos device, P type polysilicon 107 is used to form the second grid of PMOS device, and metal silication tungsten 108 is used to form the interconnected of first grid and second grid.
Then carrying out lightly doped drain (LDD) implantation is Implantation, deposition layer of sin, and the side that SiN is dry-etched in to grid forms side wall (spacer), then carries out source and leaks the source-drain area that Implantation forms respectively nmos device and PMOS device.Wherein the source-drain area of nmos device and PMOS device does not show in Fig. 2, and the direction that in Fig. 1, the source region of nmos device and drain region are linked to be is BB ' line direction, just can see the source-drain area of nmos device on the profile of BB ' line; The direction that the source region of PMOS device and drain region are linked to be also and BB ' line parallel.
After completing step described above, deposition one deck phosphorosilicate glass is the SiO2(PSG of phosphorus doping), utilize cmp (CMP) technique to grind PSG layer, deposit again afterwards the undoped SIO2 of one deck (NSG), by PSG layer and NSG layer, form interlayer film 109, then utilize dry etch process to carry out etching to interlayer film 109 and form contact hole 110, in contact hole 110, fill metal and realize drawing of grid.
As from the foregoing, existing manufacture method need to realize by metal silication tungsten the gate interconnect of NMOS and PMOS device, the boron (Boron) mixing in the P type polysilicon of PMOS device grids solubility in metal silication tungsten and polysilicon (Poly-Si) or amorphous silicon (α-Si) is roughly 100:1, Boron in described P type polysilicon can be diffused in metal silication tungsten, cause the grid concentration of PMOS device to subtract light, when making the work of PMOS device, easily form and exhaust, increase device cut-in voltage.If eliminate the concentration that Boron diffusion causes and subtract light loss by increasing the concentration of the Boron in the grid in PMOS device, can cause again the problem of reliability.The contact resistance of metal silication tungsten and polysilicon can carry out the operating rate that dividing potential drop reduces device simultaneously to device simultaneously; Due to the existence of metal silication tungsten, in the process of grid dry method, wet etching, the introducing meeting of metal ion impacts the reliability of device.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of manufacture method of cmos device, can omit the step that adopts metal silicide to realize the gate interconnect of NMOS and PMOS device, thereby can reduce dead resistance and electric capacity between contact hole and grid, the speed of device is provided, the boron doping concentration that can eliminate the grid of PMOS device subtracts light and boron and subtracts the problem of the light depletion of polysilicon causing, thereby can eliminate before contact hole forms, introduces the reliability that metallic element can improve device.
For solving the problems of the technologies described above, the manufacture method of cmos device provided by the invention, comprises the steps:
Step 1, utilize chemical wet etching technique on silicon substrate, to form shallow trench, by described shallow trench, define active area; In described shallow trench, fill silica and form shallow trench field oxygen, by described shallow trench field oxygen, described active area is isolated.
Step 2, carry out the well region that Implantation forms cmos device, the well region of described cmos device comprises the P type well region that is used to form nmos device and the N-type well region that is used to form PMOS device, described P type well region is formed in the first active area, described N-type well region is formed in the second active area, and the described shallow trench field oxygen of isolating between described the first active area and described the second active area is the first shallow trench field oxygen.
Step 3, in the front of described silicon substrate, grow successively gate oxide, polysilicon layer, in the selection area of described polysilicon layer, carry out respectively N-type Implantation and P type Implantation and form respectively N-type polysilicon layer and P type polysilicon layer, and utilizing chemical wet etching technique to carry out to described polysilicon layer the grid that etching forms described cmos device; Described grid comprises the first grid of described nmos device and the second grid of described PMOS device, and the N-type polysilicon layer of described first grid after by etching forms, the P type polysilicon layer of described second grid after by etching forms; Described first grid is covered in described the first top, active area and by the described P type well region surface that described first grid covered, is used to form the raceway groove of described nmos device; Described second grid is covered in described the second top, active area and by the described N-type well region surface that described second grid covered, is used to form the raceway groove of described PMOS device, and described first grid and described second grid also extend to respectively on described the first oxygen surface, shallow trench field and contact.
Step 4, in described first active area of described first grid both sides, form the N-type source-drain area of described nmos device, in described second active area of described second grid both sides, form the P type source-drain area of described PMOS device.
Step 5, the described active area outside described grid and described grid and described shallow trench field oxygen surface form interlayer film; Adopt chemical wet etching technique to carry out etching to described interlayer film and form strip contact hole, described strip contact hole is positioned at the top of described first grid and described second grid and strides across described first grid and the contact interface of described second grid is realized and being contacted with described second grid with described first grid simultaneously.
Further improve and be, in step 2, carry out Implantation and form the step that is also included in surfaces of active regions growth one deck sacrificial oxide layer of described silicon substrate before the well region of described cmos device, also comprise the step of removing described sacrificial oxide layer after forming described well region.
Further improve is in step 4, before forming described N-type source-drain area and described P type source-drain area, also to comprise step:
Carry out N-type LDD Implantation and in described first active area of described first grid both sides, form described nmos device NXing LDD district, carry out P type LDD Implantation and in described second active area of described second grid both sides, form the P XingLDD district of described PMOS device.
At the positive deposition of described silicon substrate one deck silicon nitride layer, adopt dry etch process to carry out etching and form side wall in the side of described grid described silicon nitride.
Further improve is that interlayer film described in step 5 comprises two-layer, forms step and is divided into:
Deposition one deck PSG layer, described PSG layer covers on the described active area and oxygen surface, described shallow trench field in described grid and described grid outside.
Adopt CMP technique to carry out planarization to described PSG layer.
Described PSG layer surface deposition one deck NSG layer after planarization, forms described interlayer film by described PSG layer and described NSG layer.
The inventive method just can realize the gate interconnect of N-type polysilicon gate and P type polycrystalline silicon gate in cmos device technique without metal silicide as WSi technique, by the contact hole in cmos device region is adopted to strip, be that cross section is that rectangular structure connects N-type polysilicon gate and P type polycrystalline silicon gate, thereby can realize the interconnected of N-type polysilicon gate and P type polycrystalline silicon gate.Owing to having saved metal silication tungsten step in the inventive method, the grid of nmos device and PMOS device is all the time in same current potential, contact hole does not have unnecessary dead resistance and electric capacity between nmos device and the grid of PMOS device, so can improve the speed of device; In addition, the inventive method also can solve boron in the grid of PMOS device and is diffused into metal level and subtracts the problem of the light depletion of polysilicon causing as metal silication tungsten causes boron element concentration in the P type polycrystalline silicon gate of PMOS device; In addition, the inventive method was not all introduced metal ion before contact hole etching, can avoid the too early impact that metal ion produces device reliability of introducing in technique.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the vertical view of the cmos device of existing method formation;
Fig. 2 is the cutaway view along the cmos device of AA ' line in Fig. 1;
Fig. 3 is the flow chart of embodiment of the present invention method;
Fig. 4 is the vertical view of the cmos device of embodiment of the present invention method formation;
Fig. 5 is the cutaway view along the cmos device of CC ' line in Fig. 4.
Embodiment
As shown in Figure 3, be the flow chart of embodiment of the present invention method, Fig. 4 is the vertical view of the cmos device of embodiment of the present invention method formation; Fig. 5 is the cutaway view along the cmos device of CC ' line in Fig. 4.The manufacture method of embodiment of the present invention cmos device, comprises the steps:
Step 1, utilize chemical wet etching technique to form shallow trench on silicon substrate 1, by described shallow trench, define active area; In described shallow trench, fill silica and form shallow trench field oxygen 4, by 4 pairs of described active areas of oxygen, described shallow trench field, isolated.
Step 2, at surfaces of active regions growth one deck sacrificial oxide layer of described silicon substrate 1, through described sacrificial oxide layer, carry out the well region that Implantation forms cmos device, the well region of described cmos device comprises the P type well region 2 that is used to form nmos device and the N-type well region 3 that is used to form PMOS device, described P type well region 2 is formed in the first active area, described N-type well region 3 is formed in the second active area, and the described shallow trench field oxygen 4 of isolating between described the first active area and described the second active area is the first shallow trench field oxygen 4.Utilize afterwards wet-etching technology to remove described sacrificial oxide layer.As shown in Figure 4, it is all rectangle that described the first active area and described the second active area are overlooked on face, and long side direction and DD ' line parallel.
Step 3, in the front of described silicon substrate 1, grow successively gate oxide 5, polysilicon layer, in the selection area of described polysilicon layer, carry out respectively N-type Implantation and P type Implantation and form respectively N-type polysilicon layer and P type polysilicon layer, and utilizing chemical wet etching technique to carry out to described polysilicon layer the grid that etching forms described cmos device; Described grid comprises the first grid 106 of described nmos device and the second grid 107 of described PMOS device, described first grid 106 by the N-type polysilicon layer after etching form, described second grid 107 is comprised of the P type polysilicon layer after etching; Described first grid 106 is covered in described the first active area top and described P type well region 2 surfaces that covered by described first grid 106 are used to form the raceway groove of described nmos device; Described second grid 107 is covered in described the second active area top and described N-type well region 3 surfaces that covered by described second grid 107 are used to form the raceway groove of described PMOS device, and described first grid 106 and described second grid 107 also extend to respectively described the first shallow trench field oxygen 4 surfaces and go up and contact.As shown in Figure 4, contact the grid structure forming elongated by described first grid 106 and described second grid 107, overlooking on face is a rectangle, this rectangular long side direction and CC ' line parallel, and CC ' line is vertical with DD ' line.
Step 4, carry out N-type LDD Implantation and in described first active area of described first grid 106 both sides, form described nmos device NXing LDD district, carry out P type LDD Implantation and in described second active area of described second grid 107 both sides, form the P XingLDD district of described PMOS device.
At the positive deposition one deck of described silicon substrate 1 silicon nitride layer, adopt dry etch process to carry out etching and form side wall in the side of described grid described silicon nitride.
In described first active area of described first grid 106 both sides, form the N-type source-drain area of described nmos device, in described second active area of described second grid 107 both sides, form the P type source-drain area of described PMOS device.Described N-type source-drain area and described P type source-drain area do not show in Fig. 5, and N-type source region is identical with DD ' line with drain region line direction, and P type source region and drain region line direction are also and DD ' line parallel.
Step 5, deposition one deck PSG (SiO2 of phosphorus doping) layer, described PSG layer covers on the described active area and oxygen 4 surfaces, described shallow trench field in described grid and described grid outside.
Adopt CMP technique to carry out planarization to described PSG layer.
Described PSG layer surface deposition one deck NSG (undoped SiO2) layer after planarization, forms interlayer film 9 by described PSG layer and described NSG layer.
Adopt chemical wet etching technique to carry out etching to described interlayer film 9 and form strip contact hole 8, described strip contact hole 8 is positioned at the top of described first grid 106 and described second grid 107 and strides across described first grid 106 and the contact interface of described second grid 107 is realized and being contacted with described second grid 107 with described first grid 106 simultaneously.Insert metal in described strip contact hole 8 after, can directly described first grid 106 and described second grid 107 be drawn, comparison diagram 2 and Fig. 5 are known, have omitted the metal silication tungsten of the grid that is used for connecting nmos device and PMOS device in prior art in the inventive method.
By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (4)
1. a manufacture method for cmos device, is characterized in that, comprises the steps:
Step 1, utilize chemical wet etching technique on silicon substrate, to form shallow trench, by described shallow trench, define active area; In described shallow trench, fill silica and form shallow trench field oxygen, by described shallow trench field oxygen, described active area is isolated;
Step 2, carry out the well region that Implantation forms cmos device, the well region of described cmos device comprises the P type well region that is used to form nmos device and the N-type well region that is used to form PMOS device, described P type well region is formed in the first active area, described N-type well region is formed in the second active area, and the described shallow trench field oxygen of isolating between described the first active area and described the second active area is the first shallow trench field oxygen;
Step 3, in the front of described silicon substrate, grow successively gate oxide, polysilicon layer, in the selection area of described polysilicon layer, carry out respectively N-type Implantation and P type Implantation and form respectively N-type polysilicon layer and P type polysilicon layer, and utilizing chemical wet etching technique to carry out to described polysilicon layer the grid that etching forms described cmos device; Described grid comprises the first grid of described nmos device and the second grid of described PMOS device, and the N-type polysilicon layer of described first grid after by etching forms, the P type polysilicon layer of described second grid after by etching forms; Described first grid is covered in described the first top, active area and by the described P type well region surface that described first grid covered, is used to form the raceway groove of described nmos device; Described second grid is covered in described the second top, active area and by the described N-type well region surface that described second grid covered, is used to form the raceway groove of described PMOS device, and described first grid and described second grid also extend to respectively on described the first oxygen surface, shallow trench field and contact;
Step 4, in described first active area of described first grid both sides, form the N-type source-drain area of described nmos device, in described second active area of described second grid both sides, form the P type source-drain area of described PMOS device;
Step 5, the described active area outside described grid and described grid and described shallow trench field oxygen surface form interlayer film; Adopt chemical wet etching technique to carry out etching to described interlayer film and form strip contact hole, described strip contact hole is positioned at the top of described first grid and described second grid and strides across described first grid and the contact interface of described second grid is realized and being contacted with described second grid with described first grid simultaneously.
2. the manufacture method of cmos device as claimed in claim 1, it is characterized in that: in step 2, carry out Implantation and form the step that is also included in surfaces of active regions growth one deck sacrificial oxide layer of described silicon substrate before the well region of described cmos device, also comprise the step of removing described sacrificial oxide layer after forming described well region.
3. the manufacture method of cmos device as claimed in claim 1, is characterized in that: in step 4, before forming described N-type source-drain area and described P type source-drain area, also comprise step:
Carry out N-type LDD Implantation and in described first active area of described first grid both sides, form described nmos device NXing LDD district, carry out P type LDD Implantation and in described second active area of described second grid both sides, form the P XingLDD district of described PMOS device;
At the positive deposition of described silicon substrate one deck silicon nitride layer, adopt dry etch process to carry out etching and form side wall in the side of described grid described silicon nitride.
4. the manufacture method of cmos device as claimed in claim 1, is characterized in that: interlayer film described in step 5 comprises two-layer, forms step and is divided into:
Deposition one deck PSG layer, described PSG layer covers on the described active area and oxygen surface, described shallow trench field in described grid and described grid outside;
Adopt CMP technique to carry out planarization to described PSG layer;
Described PSG layer surface deposition one deck NSG layer after planarization, forms described interlayer film by described PSG layer and described NSG layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310124021.XA CN104103588B (en) | 2013-04-10 | 2013-04-10 | Method for manufacturing COMS device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310124021.XA CN104103588B (en) | 2013-04-10 | 2013-04-10 | Method for manufacturing COMS device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104103588A true CN104103588A (en) | 2014-10-15 |
| CN104103588B CN104103588B (en) | 2017-02-15 |
Family
ID=51671610
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310124021.XA Active CN104103588B (en) | 2013-04-10 | 2013-04-10 | Method for manufacturing COMS device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104103588B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110379809A (en) * | 2019-07-17 | 2019-10-25 | 上海华力集成电路制造有限公司 | SRAM and its manufacturing method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5468669A (en) * | 1993-10-29 | 1995-11-21 | At&T Corp. | Integrated circuit fabrication |
| JPH11126828A (en) * | 1997-10-24 | 1999-05-11 | Nec Corp | Semiconductor device and its manufacture |
| US20070247914A1 (en) * | 2006-04-11 | 2007-10-25 | Monolithic System Technology, Inc. | Non-Volatile Memory In CMOS Logic Process And Method Of Operation Thereof |
| US20100148274A1 (en) * | 2006-10-16 | 2010-06-17 | Sony Corporation | Semiconductor device and method for manufacturing same |
| CN102394220A (en) * | 2011-11-17 | 2012-03-28 | 上海华力微电子有限公司 | Method for improving carrier mobility of MOS (Metal Oxide Semiconductor) device and MOS device manufacturing method |
-
2013
- 2013-04-10 CN CN201310124021.XA patent/CN104103588B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5468669A (en) * | 1993-10-29 | 1995-11-21 | At&T Corp. | Integrated circuit fabrication |
| JPH11126828A (en) * | 1997-10-24 | 1999-05-11 | Nec Corp | Semiconductor device and its manufacture |
| US20070247914A1 (en) * | 2006-04-11 | 2007-10-25 | Monolithic System Technology, Inc. | Non-Volatile Memory In CMOS Logic Process And Method Of Operation Thereof |
| US20100148274A1 (en) * | 2006-10-16 | 2010-06-17 | Sony Corporation | Semiconductor device and method for manufacturing same |
| CN102394220A (en) * | 2011-11-17 | 2012-03-28 | 上海华力微电子有限公司 | Method for improving carrier mobility of MOS (Metal Oxide Semiconductor) device and MOS device manufacturing method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110379809A (en) * | 2019-07-17 | 2019-10-25 | 上海华力集成电路制造有限公司 | SRAM and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104103588B (en) | 2017-02-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10032766B2 (en) | VDMOS transistors, BCD devices including VDMOS transistors, and methods for fabricating integrated circuits with such devices | |
| US11158737B2 (en) | LDMOS component, manufacturing method therefor, and electronic device | |
| US10141421B2 (en) | Vertical power MOSFET and methods of forming the same | |
| CN107978635B (en) | Semiconductor device, manufacturing method thereof and electronic device | |
| CN100570892C (en) | Semiconductor device and manufacture method thereof | |
| US9087920B2 (en) | Vertical power MOSFET and methods of forming the same | |
| CN103000572A (en) | Contact for high-K metal gate device | |
| CN103715133B (en) | Mos transistor and forming method thereof | |
| CN104347420A (en) | LDMOS (Lateral Double-Diffused MOSFET (Metal Oxide Semiconductor Field Effect Transistor)) device and forming method thereof | |
| US10249721B2 (en) | Semiconductor device including a gate trench and a source trench | |
| CN104810368A (en) | Cmos transistor and forming method thereof | |
| US20090014787A1 (en) | Multi-Layer Semiconductor Structure and Manufacturing Method Thereof | |
| WO2016015501A1 (en) | Tunneling transistor structure and manufacturing method therefor | |
| TW201937565A (en) | Dual gate LDMOS and a process of forming thereof | |
| CN101924110A (en) | SOI (Silicon On Insulator) transistor structure of body contact and preparation method thereof | |
| CN105428241A (en) | Manufacturing method of trench gate power device with shield grid | |
| KR101469343B1 (en) | Vertical power mosfet and methods of forming the same | |
| CN105336779A (en) | LDMOS (lateral double-diffused MOSFET) device and formation method therefor | |
| CN104681490A (en) | Forming method of CMOS (complementary metal-oxide-semiconductor) transistor | |
| CN104701136A (en) | Capacitor, semiconductor device and production method of capacitor | |
| CN104425279A (en) | Fin type field effect transistor, forming method of fin type field effect transistor and semiconductor device | |
| CN104103588A (en) | Method for manufacturing COMS device | |
| CN103077926A (en) | Formation method for semiconductor device | |
| CN103094217B (en) | Manufacture method of transistor | |
| CN103137694B (en) | A kind of surface channel field-effect transistor and manufacture method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |