CN104102593B - Graphic system based on row address processor - Google Patents
Graphic system based on row address processor Download PDFInfo
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- CN104102593B CN104102593B CN201410313814.0A CN201410313814A CN104102593B CN 104102593 B CN104102593 B CN 104102593B CN 201410313814 A CN201410313814 A CN 201410313814A CN 104102593 B CN104102593 B CN 104102593B
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Abstract
The invention discloses a kind of graphic system based on row address processor, mainly by processing unit, and the imaging sensor composition being connected with the processing unit, it is characterized in that, it is additionally provided with the row address processor being connected with processing unit, the row address processor is by Micro-processor MCV, the row address register array being connected with the P10 pins of the Micro-processor MCV, the battery BT being serially connected between the VDD pins of Micro-processor MCV and GND pins, the electric capacity C12 being in parallel with battery BT, and base stage is connected after resistance R13 with the P33 pins of Micro-processor MCV, positive pole of the colelctor electrode with battery BT after inductance L is connected, and the triode Q2 compositions of grounded emitter.The overall structure of the present invention is very simple, and its processing speed is very fast, and the picture of processing 1028*1028 pixels only needs 0.5s, is more than 10 times of conventional process speed.
Description
Technical field
The invention belongs to technical field of image processing, in particular to the graphic system based on row address processor.
Background technology
At present, the image recognition product using scanner as representative emerges in an endless stream, and it greatly enriches the life of people.But
That the recognition capability of these image recognition products has certain limitation at present, i.e. its image recognition rate and precision
Still it is not high, the situation that image or paper are bonded with scanning sensor imprecision, therefore meeting occurs in identification process in addition
Cause distortion zone occur, it is impossible to really reflect actual effect.
The content of the invention
It is an object of the invention to overcome recognition speed present in current image identification system and precision not high, Yi Jihui
There is the defects of distortion zone, there is provided the graphic system based on row address processor.
The purpose of the present invention is achieved through the following technical solutions：Based on the graphic system of row address processor, mainly
By processing unit, and the imaging sensor composition being connected with the processing unit, meanwhile, it is additionally provided with and is connected with processing unit
Row address processor, the row address processor is by Micro-processor MCV, the row being connected with the P10 pins of the Micro-processor MCV
Address register array, the battery BT being serially connected between the VDD pins of Micro-processor MCV and GND pins, is in parallel with battery BT
Electric capacity C12, and base stage is connected after resistance R13 with the P33 pins of Micro-processor MCV, colelctor electrode after inductance L with electricity
Pond BT positive pole is connected and the triode Q2 of grounded emitter is formed.
Described processing unit is by drive circuit, and the process circuit being connected with drive circuit is formed；The driving
Circuit is by high-speed driving chip K, triode Q1, and one end is connected with high-speed driving chip K FX pins, the other end and triode
The resistance R10 that Q1 base stage is connected, one end is connected with high-speed driving chip K F1 pins, the other end after electric capacity C10 with
The resistance R11 that high-speed driving chip K FC pins are connected, and one end is connected with triode Q1 emitter stage, the other end
The resistance R12 compositions being connected after polar capacitor C11 with high-speed driving chip K BE pins；The current collection of the triode Q1
Pole is grounded, and F2 pin of the described image sensor directly with high-speed driving chip K is connected, and high-speed driving chip K BN
End is then connected with the BM ends of Micro-processor MCV.
Described process circuit is by driving chip U, and P poles are connected with driving chip U SW pins, N poles are through polar capacitor
The diode D1 being grounded after C1, one end is connected with diode D1 N poles, the other end is grounded after resistance R2 resistance R1, one
End is connected with driving chip U COMP pins, the electric capacity C2 of other end ground connection, one end and driving chip U COMP pin phases
The resistance R3 that connection, the other end are grounded after electric capacity C3, one end is connected with driving chip U VIN pins, the other end is grounded
Electric capacity C5 and polar capacitor C6, one end is connected with driving chip U VIN pins, the resistance that the other end is grounded after resistance R5
R4, the electric capacity C7 being in parallel with resistance R5, and one end is connected with driving chip U SS pins, the electric capacity of other end ground connection
C4 is formed；The tie point of the resistance R1 and resistance R2 are also connected with driving chip U FB pins；The driving chip U's
MIN pins are connected with high-speed driving chip K M1 pins, and driving chip U MOUT pins are managed with high-speed driving chip K M2
Pin is connected.
To ensure using effect, described driving chip U is LT1942 type integrated chips, and the high-speed driving chip K is
EMD2050 type integrated chips, and it by quantity is that more than one address register is suitable that described row address register array, which is then,
The array that sequence arrangement forms.
The present invention compared with prior art, has the following advantages that and beneficial effect：
（1）The overall structure of the present invention is very simple, and its processing speed is very fast, handles the picture of 1028*1028 pixels only
0.5s is needed, is more than 10 times of conventional process speed.
（2）The present invention is integrated with LT1941 types integrated chip, EMD2050 high speed integrated chips, therefore can greatly improve
The picture frame treatment effeciency of unit interval, so as to improve recognition efficiency.
（3）The initiative core for employing row address processor and being used as data processing of the invention, can be line by line to image
Row address scanning and arrangement are carried out, so as to greatly provide scanning accuracy.
Brief description of the drawings
Fig. 1 is the overall structure diagram of the present invention.
Embodiment
With reference to embodiment and accompanying drawing, the present invention is described in further detail, but embodiments of the present invention are not
It is limited to this.
As shown in figure 1, the graphic system based on row address processor of the present embodiment, mainly by processing unit, with
The imaging sensor that the processing unit is connected, and the row address processor group being connected with processing unit into.Wherein, row ground
Location processor is the core point of the present invention, and it is by Micro-processor MCV, the row ground being connected with the P10 pins of the Micro-processor MCV
Location register array, the battery BT being serially connected between the VDD pins of Micro-processor MCV and GND pins, it is in parallel with battery BT
Electric capacity C12, and base stage is connected after resistance R13 with the P33 pins of Micro-processor MCV, colelctor electrode after inductance L with battery
BT positive pole is connected and the triode Q2 of grounded emitter is formed.
The processing unit is by drive circuit, and the process circuit being connected with drive circuit is formed.As shown in figure 1,
The drive circuit is by high-speed driving chip K, triode Q1, resistance R10, resistance R11, resistance R12, electric capacity C10 and polar capacitor
C11 is formed.During connection, resistance R10 one end is connected with high-speed driving chip K FX pins, the other end and triode Q1
Base stage is connected；Resistance R11 one end is connected with high-speed driving chip K F1 pins, the other end after electric capacity C10 with a high speed
Driving chip K FC pins are connected；Resistance R12 one end is connected with triode Q1 emitter stage, the other end is through polarity electricity
It is connected after holding C11 with high-speed driving chip K BE pins.
Meanwhile the grounded collector of the triode Q1, and F2 pin of the imaging sensor directly with high-speed driving chip K
It is connected, and high-speed driving chip K BN ends are then connected with the BM ends of Micro-processor MCV.
Described process circuit is by driving chip U, polar capacitor C1, diode D1, resistance R1, resistance R2, electric capacity C2, electricity
Hinder R3, electric capacity C3, electric capacity C4, resistance R4, electric capacity C7, polar capacitor C6, electric capacity C5 and resistance R5.During connection, diode D1 P
Pole is connected with driving chip U SW pins, N poles are grounded after polar capacitor C1；Resistance R1 one end and diode D1 N poles
It is connected, the other end is grounded after resistance R2；Electric capacity C2 one end is connected with driving chip U COMP pins, another termination
Ground；Resistance R3 one end is connected with driving chip U COMP pins, the other end is grounded after electric capacity C3；Polar capacitor C6's
One end is connected with driving chip U VIN pins, other end ground connection, meanwhile, electric capacity C5 one end is managed with driving chip U VIN
Pin is connected, the other end is grounded.
Resistance R4 one end is connected with driving chip U COMP pins, and its other end is grounded after resistance R5, electric capacity C7
Then it is in parallel with resistance R5；Electric capacity C4 one end is connected with driving chip U SS pins, other end ground connection.Meanwhile resistance R1
Also it is connected with resistance R2 tie point with driving chip U FB pins.
To ensure using effect, the driving chip U in the present embodiment is preferentially realized using LT1942 types integrated chip, and
High-speed driving chip K is then realized using EMD2050 types integrated chip.
As described above, it can preferably realize the present invention.
Claims (5)
1. based on the graphic system of row address processor, mainly by processing unit, and be connected with the processing unit
Imaging sensor forms, it is characterised in that is additionally provided with the row address processor being connected with processing unit, the row address processor
By Micro-processor MCV, the row address register array being connected with the P10 pins of the Micro-processor MCV, microprocessor is serially connected in
Battery BT between MCU VDD pins and GND pins, the electric capacity C12 being in parallel with battery BT, and base stage is after resistance R13
It is connected with the P33 pins of Micro-processor MCV, positive pole of the colelctor electrode with battery BT after inductance L is connected and grounded emitter
Triode Q2 composition；Described processing unit is by drive circuit, and the process circuit being connected with drive circuit is formed；Institute
Drive circuit is stated by high-speed driving chip K, triode Q1, one end is connected with high-speed driving chip K FX pins, the other end with
The resistance R10 that triode Q1 base stage is connected, one end is connected with high-speed driving chip K F1 pins, the other end is through electric capacity
The resistance R11 being connected after C10 with high-speed driving chip K FC pins, and one end be connected with triode Q1 emitter stage,
The resistance R12 compositions that the other end is connected after polar capacitor C11 with high-speed driving chip K BE pins；The triode Q1
Grounded collector, and F2 pin of the described image sensor directly with high-speed driving chip K is connected, and high-speed driving chip
K BN ends are then connected with the BM ends of Micro-processor MCV.
2. the graphic system according to claim 1 based on row address processor, it is characterised in that described processing
Circuit is by driving chip U, the diode D1 that P poles are connected with driving chip U SW pins, N poles are grounded after polar capacitor C1,
The resistance R1 that one end is connected with diode D1 N poles, the other end is grounded after resistance R2, one end and driving chip U COMP
Pin is connected, the electric capacity C2 of other end ground connection, and one end is connected with driving chip U COMP pins, the other end is through electric capacity C3
The resistance R3 being grounded afterwards, one end is connected with driving chip U VIN pins, the electric capacity C5 and polar capacitor C6 of other end ground connection,
The resistance R4 that one end is connected with driving chip U VIN pins, the other end is grounded after resistance R5, it is in parallel with resistance R5
Electric capacity C7, and one end is connected with driving chip U SS pins, the electric capacity C4 compositions of other end ground connection；The resistance R1 and
Resistance R2 tie point is also connected with driving chip U FB pins；The MIN pins of the driving chip U and high-speed driving core
Piece K M1 pins are connected, and driving chip U MOUT pins are connected with high-speed driving chip K M2 pins.
3. the graphic system according to claim 2 based on row address processor, it is characterised in that described driving
Chip U is LT1942 type integrated chips.
4. the graphic system based on row address processor according to any one of claims 1 to 3, it is characterised in that
The high-speed driving chip K is EMD2050 type integrated chips.
5. the graphic system according to claim 4 based on row address processor, it is characterised in that described row ground
It by quantity is that more than one address register sequentially arranges the array formed that location register array, which is,.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410313814.0A CN104102593B (en) | 2014-07-03 | 2014-07-03 | Graphic system based on row address processor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410313814.0A CN104102593B (en) | 2014-07-03 | 2014-07-03 | Graphic system based on row address processor |
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| CN104102593A CN104102593A (en) | 2014-10-15 |
| CN104102593B true CN104102593B (en) | 2017-12-01 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1188912A (en) * | 1997-01-20 | 1998-07-29 | 株式会社东芝 | Access method image formation save device and address generated method and device for image storage |
| CN1832542A (en) * | 2005-03-07 | 2006-09-13 | 富士胶片株式会社 | Solid-state image sensor having its photosensitive cells broadened in area |
| CN101262553A (en) * | 2007-01-03 | 2008-09-10 | 三星电子株式会社 | Image sensor possessing temperature sensor and its driving method |
| WO2012144869A2 (en) * | 2011-04-22 | 2012-10-26 | Semisolution Co., Ltd. | Sensor-integrated chip for ccd camera |
| CN204028896U (en) * | 2014-07-03 | 2014-12-17 | 宁波摩米创新工场电子科技有限公司 | Graphic system based on row address processor |
-
2014
- 2014-07-03 CN CN201410313814.0A patent/CN104102593B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1188912A (en) * | 1997-01-20 | 1998-07-29 | 株式会社东芝 | Access method image formation save device and address generated method and device for image storage |
| CN1832542A (en) * | 2005-03-07 | 2006-09-13 | 富士胶片株式会社 | Solid-state image sensor having its photosensitive cells broadened in area |
| CN101262553A (en) * | 2007-01-03 | 2008-09-10 | 三星电子株式会社 | Image sensor possessing temperature sensor and its driving method |
| WO2012144869A2 (en) * | 2011-04-22 | 2012-10-26 | Semisolution Co., Ltd. | Sensor-integrated chip for ccd camera |
| CN204028896U (en) * | 2014-07-03 | 2014-12-17 | 宁波摩米创新工场电子科技有限公司 | Graphic system based on row address processor |
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| CN104102593A (en) | 2014-10-15 |
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Effective date of registration: 20210914 Address after: 463005 Zhumadian public bonded center, intersection of Xingye Avenue and Gongye 2nd Road, Zhumadian City, Henan Province Patentee after: Zhumadian Momi Innovation workshop Electronic Technology Co.,Ltd. Address before: Room 505 and 510, No. 298, bachelor Road, Yinzhou District, Ningbo City, Zhejiang Province Patentee before: NINGBO MOMI INNOVATION WORKS ELECTRONIC TECHNOLOGY Co.,Ltd. |
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Granted publication date: 20171201 |