CN1188912A - Access method image formation save device and address generated method and device for image storage - Google Patents

Abstract

The invention provides a method to access any data of transverse direction, long direction, an entire block and a part of a block within a block in an impulse train mode. By adopting the invention, a picture memory can be accessed at a high speed whatever the direction is. The invention is achieved by dividing a complete image into blocks and constituting the blocks with the data of the memory address which can be accessed in an impulse train mode.

Description

Image memory access method, image formation, save set and address generating method and device

The present invention relates to video memory is carried out image memory access method, image processing system, image formation save set, address generating method and the address generating device of access.

In recent years, image information can have been used easily as numerical data.As the machine of using these data digital PPC is arranged.This is not as traditional simulation PPC, carries out image by the reflected light on the optical system guiding original copy on photoreceptor and forms.But be transformed into digital signal after once the reflected light on the original copy being read as electric signal with ccd sensor.To after once digitized original copy was implemented all processing, utilize the laser duplicator to output on the paper again.

By original image once had been transformed into digital signal, just can be undertaken correction, amplify and all processing such as dwindle, part is deleted outside the frame deletion by signal Processing from the input characteristics of ccd sensor to the output characteristics of laser duplicator.

And then the image that is transformed into digital signal can improve storage efficiency by carrying out the encoding process amount of compressed data.The image of being stored can be decoded into original image by the random order of thinking printout, and exports any number to the laser duplicator.

Past is because these permutations are to use classifier, stacker to carry out operation mechanically to the printout of printing, so the maximization of device, the increaseization of noise are with inevitable.In addition, plurality of sheets of paper be printed and repeatedly printing must be carried out.

In addition, preparation has 1 page video memory (page storage), once from the image of scanister (image read-out) or code storage image after launching on the video memory, playback mode output meaning that can be by changing video memory be 90 degree, 180 degree, 270 image rotatings of spending.

By the rotation output image, always can export with unidirectional transfer sheet regardless of the placement direction of original copy, perhaps by alternatively exporting in length and breadth and utilizing the direction of transfer sheet to distinguish separation between a plurality of parts.

Also have,, can realize linking and print, i.e. the image (4 close 1,2 closes 1) of a plurality of pages of printing on a piece of paper by the image or the code storage image from scanister of a plurality of pages of in video memory, having launched to dwindle with a page.When doing this binding printing, need more according to the number that is linked, transfer sheet is changed in length and breadth with the rotation of correspondence image export.

For the rotation output image, after once original image being write video memory, need to read video memory image rotating.

Be high picture element ground type-script, the resolution when need improving original copy and reading or on the laser duplicator during print image.Certainly, also increase with the accompany capacity of its needed video memory of high resolving power thereupon.For example, when reading the original copy of 1 page of A4 size with the resolution of 400dpi by the monochrome data of 1 of every pixel, needed video memory size is about the 2M byte, then is the 4.4M byte when the resolution of 600dpi.And when the gray-scale data with 8 of every pixels reads, it will further expand and arrive its size of 8 times.

Like this, because of recording image data needs very huge storer, so video memory is used the cheap DRAM of a unit price usually.

Common DRAM has high speed page-mode or hypervelocity page-mode, promptly, specify specific address by row (ROW) and two addresses of row (COLUMN), if specified row address, then because of in inside being all data of reading same row address, thus as with the data of delegation as long as specify columns address just the high speed page-mode or the hypervelocity page-mode of (situation with two addresses of row address and column address is compared) a plurality of data of access at high speed.

In addition, the synchronous dram of high speed more etc. is arranged, that is, and at inner continuous column address and the synchronous dram of producing of DRAM by only providing the total signal of column address further at a high speed continuation address to be carried out access to DRAM by the outside.

As the DRAM corresponding TC5116160A is arranged with the high speed page-mode, as the DRAM corresponding TC5116165BJ (see also databook in detail: nineteen ninety-five version (strain) MOC of Toshiba DRAM memory (multidigit product) is compiled) is arranged, (see also databook in detail: nineteen ninety-five version (strain) MOC of Toshiba storer ASMIC compile) such as TC59S1604FT arranged as synchronous dram with the hypervelocity page-mode.

After, our regulation as described abovely provides as the address of starting point and carries out the burst accesses (burst access) that consecutive access at a high speed calls DRAM DRAM resembling.

When using these DRAM composing images storeies, the image to two dimension in the flat 6-85676 of publication number sequentially increases storage address from upper left line by line to the bottom right.

Therefore, be the corresponding two-dimentional video memory in continuous address that makes storer, increase the address to the right from the left end of going, and the storage address of the capable left end of the storage address of the right terminal of row and next line (row under) is continuous.

Storage address is given low level row (COLUMN) address assignment, and row (ROW) address assignment is given high-order.

So, in the left and right directions of delegation, for making the address continuous, in the variation range of low order address, keeping same value as the row address of high address.

But, because the address is discontinuous on the above-below direction of different rows, so, do not guarantee that the high address is same value.

Be high picture element ground type-script, the resolution when need improving original copy and reading or on the laser duplicator during print image.Certainly, also increase with the accompany capacity of its needed video memory of high resolving power thereupon.For example, when reading the original copy of 1 page of foregoing A4 size with the resolution of 400dpi by the monochrome data of 1 of every pixel, needed video memory size is about the 2M byte, then is the 4.4M byte when the resolution of 600dpi.And when the gray-scale data with 8 of every pixels reads, it will further expand and arrive its size of 8 times.

For on video memory, handling these so a large amount of view data, just require very high image storage transfer rate, transmit to the view data of video memory, transmit and with being used for the picture coding of memory image, image transmission etc. between the decoding device to the view data of duplicator by video memory to finish by scanister.

For example, in one minute the view data on the video memory when duplicator transmits 60 times, the black white image of A4 size, 600dpi is by the gray-scale data when reading of p.s. 8 of 4.4M byte, every pixels, then need its 8 times p.s. the 35.2M byte transfer rate.

In the traditional approach, when the image storage of the corresponding two dimension of the continuation address that makes storer, do not consider the continuity of the storage address of left and right directions and above-below direction.

Therefore, above-below direction during access of left and right directions by common access time the, rotation, the piece of two dimension is carried out duplicator that the Flame Image Process of access or coding and decoding processing, a plurality of laser explosure device relatively can multirow print simultaneously and carries out multirow when reading as handling unit, at every turn only can be by institute to row address and column address at 1 enterprising line access of word unit, can not utilize the burst accesses of DRAM to carry out high speed transmission.

In addition, when needs transmit at a high speed,, will increase unit scale or cost inevitably for the memory component of the bit width of the word of expanding access each time or the high speed by using other is corresponding with it.

The object of the present invention is to provide to remove and resemble the device that can not carry out the shortcoming of zero access as described above video memory, that is, provide image memory access method, image processing system, image formation save set, address generating method and the address generating device that can carry out burst accesses and zero access to video memory.

The present invention is in by the video memory that constitutes with lower device: promptly, by a plurality of row, the memory array that a plurality of row are formed, by the bit data that can read and write in batch delegation with respect to this memory array in batch, and keep the data register of this delegation's bit data, by selecting to carry out that this data register read and write in batch delegation's bit data in batch, the row address selecting arrangement of the row of above-mentioned memory array, and by the bit data of selecting to keep above-mentioned delegation, the reading and write of data register, in the video memory that the column address selecting arrangement of certain bits is formed

Original image is divided into the piece of forming by a plurality of pixels, and same pixel data is kept in the same delegation of above-mentioned memory array, if to the access of the pixel data in same, then as long as specify the once row address of above-mentioned memory array, but provide the column address of only specifying above-mentioned data register a plurality of pixel datas in same of the access just then.

The present invention is in by the video memory that constitutes with lower device: promptly, by a plurality of row, the memory array that a plurality of row are formed, by the bit data that can read and write in batch delegation with respect to this memory array in batch, and keep the data register of this delegation's bit data, by what select to carry out to the bit data of reading and write in batch delegation in batch of this data register, the row address selecting arrangement of the row of above-mentioned memory array, and by the bit data of selecting to keep above-mentioned delegation, the reading and write of data register, in the video memory that the column address selecting arrangement of certain bits is formed

Original image is divided into the piece of forming by some pixels, and same pixel data is kept in the same delegation of above-mentioned memory array, if to the pixel data access in same, promptly, if in the above-mentioned data register, have a bit data of eligible row address that is comprised, then come a plurality of pixel datas in same of the access by the column address of only specifying above-mentioned data register.

The present invention is in the image processing system that uses by the video memory that constitutes with lower device: promptly, by a plurality of row, the memory array that a plurality of row are formed, by the bit data that can read and write in batch delegation with respect to this memory array in batch, and the data register of the bit data of maintenance delegation, by what select to carry out to the bit data of reading and write in batch delegation in batch of this data register, the row address selecting arrangement of the row of above-mentioned memory array, and by select carrying out, the certain bits of reading and writing of data register that keeps the bit data of above-mentioned delegation, in the image processing system of the video memory that the column address selecting arrangement is formed

Constitute: the reading device that reads the original image pixel data; When the view data of utilizing this reading device to read forms image, simultaneously it is divided into and is included in piece in same, that form by a plurality of pixels to the pixel data that forms image, and same pixel data is kept at save set in the same delegation of above-mentioned memory array; If the pixel data in same is read, then only specify the once row address of above-mentioned memory array, then, read a plurality of pixel datas in same continuously by the column address of only specifying above-mentioned data register, to read out in simultaneously the readout device that forms the pixel data of image when image forms continuously; The corresponding pixel data of reading by this readout device, form the image processing system that simultaneously a plurality of pixels is formed image on the medium at image.

The present invention is in the image processing system that uses by the video memory that constitutes with lower device: promptly, by a plurality of row, the memory array that a plurality of row are formed, by the bit data that can read and write in batch delegation with respect to this memory array in batch, and the data register of the bit data of maintenance delegation, by what select to carry out to this data register, read and write in batch the bit data of delegation in batch, the row address selecting arrangement of the row of above-mentioned memory array, and by select carrying out, the certain bits of reading and writing of data register that keeps the bit data of above-mentioned delegation, in the image processing system of the video memory that the column address selecting arrangement is formed

Constitute: the reading device that reads the original image pixel data; When the view data of utilizing this reading device to read forms image, simultaneously it is divided into and is included in the piece of forming by a plurality of pixels in same to the pixel data that forms image, and same pixel data is kept at save set in the same delegation of above-mentioned memory array; Pixel data in same is read, promptly, if in above-mentioned data register, there is the bit data of eligible row address that is comprised, then read a plurality of pixel datas in same continuously, read out in the readout device that forms the pixel data of image when image forms simultaneously continuously by the column address of only specifying above-mentioned data register; The corresponding pixel data of reading by this readout device, form the image processing system that simultaneously a plurality of pixels is formed image on the medium at image.

The present invention is using the image by the video memory that constitutes with lower device to form in the save set: promptly, by a plurality of row, the memory array that a plurality of row are formed, by the bit data that can read and write in batch delegation with respect to this memory array in batch, and the data register of the bit data of maintenance delegation, by what select to carry out to the bit data of reading and write in batch delegation in batch of this data register, the row address selecting arrangement of the row of above-mentioned memory array, and by select carrying out, the data register that keeps the bit data of above-mentioned delegation, the certain bits of reading and writing, the image of the video memory that the column address selecting arrangement is formed forms in the save set

Constitute: the reading device that reads the original image pixel data; The view data of utilizing this reading device to read is divided into the piece of forming by as a plurality of pixels of encoding process unit, and same pixel data is kept at the save set in the same delegation of above-mentioned memory array; If the pixel data in same is read, then only specify the once row address of above-mentioned memory array, then, the column address by only specifying above-mentioned data register, read readout devices piece, a plurality of pixel datas in batch as encoding process unit; The code device that the pixel data of the piece read by this readout device is encoded; Preservation is translated into the coded data save set of coded data by above-mentioned code device; By sequence of pages arbitrarily read, be kept at coded data on the coded data save set, more than one page, the coded data readout device; Decoding is the decoding device that unit is translated into coded data with the piece; Only specify once the row address of above-mentioned memory array, what read in decoding in batch is the pixel data of unit with the piece, then, the column address by only specifying above-mentioned data register, write writing stations piece, a plurality of pixel datas in batch as decoding processing unit; The corresponding pixel data that writes by this above-mentioned writing station, form the image processing system that forms image on the medium at image.

The present invention is a plurality of words on the line direction, a plurality of words are as 1 piece on the column direction, there are a plurality of for this at line direction, when column direction exists a plurality of video memory to carry out the image memory access of two dimension, on the row of regulation, produce the address of the burst accesses of the column direction number of words that constitutes 1 piece, whenever carry out the access of pulsatile once string, just generate the address add after the number of words that constitutes 1 piece, whenever carry out a plurality of burst accesses of a column direction, just multiply by with the value of the number of words that constitutes 1 piece and from a plurality of numbers of column direction, deduct a value behind the piece, and add the value of the number of words of the column direction in 1 on the value after deducting this value, again its end value is generated as the address, and whenever carry out a plurality of burst accesses of column direction of a plurality of numbers of words of line direction, just the value of the number of words that deducts the column direction that constitutes 1 piece from the number of words that constitutes 1 piece is produced as the address.

The present invention is in the video memory with following array apparatus, promptly, going by most, most the memory arrays that row are formed, by the bit data that can read and write in batch delegation with respect to this memory array in batch, and the data register of the bit data of maintenance delegation, by what select to carry out to this data register, read and write in batch the bit data of delegation in batch, the row address selecting arrangement of the row of above-mentioned memory array, and by select carrying out, the reading and write of data register that keeps the bit data of above-mentioned delegation, the column address selecting arrangement of certain bits is formed, simultaneously, be that original image is divided into the piece of being made up of a plurality of pixels, and the pixel data in same is kept in the same delegation of above-mentioned memory array, if to the access of the pixel data in same, then by only specifying the once row address of above-mentioned memory array, then, undertaken by the column address of only specifying above-mentioned data register in the video memory of access of a plurality of pixel datas in same

Constitute: the row address of above-mentioned video memory as the high address, the address that column address is represented as low order address is as the one dimension storage address, the a plurality of words of line direction, the a plurality of words of column direction are as a piece, the piece of original image is formed in is divided into a plurality of on the line direction, be divided into a plurality of on the column direction, when carrying out two-dimentional access, calculate the flat address of the word of the initial access of each piece, the value of the row address that is equivalent to this flat address is specified once as the row address of above-mentioned memory array, on the value of the column address that is equivalent to above-mentioned flat address, add the value after the off-set value of the plus or minus that each consecutive access is general, column address as above-mentioned memory array is set in proper order, and carry out consecutive access in the piece by a specify columns address, the address generating device that is used to carry out above-mentioned consecutive access comprises: the storage address save set of preserving present consecutive access start address, the first address increment specified device, the second address increment specified device, three-address increment specified device, a consecutive access as the 1st counting assembly that once calculates the consecutive access number of times, a consecutive access as the 2nd counting assembly that once calculates the consecutive access number of times, the 1st count cycle specified device of above-mentioned the 1st counting assembly, the 2nd count cycle specified device of above-mentioned the 2nd counting assembly, and be starting point with the consecutive access start address, the specified device of displacement of storage address of each word of consecutive access is carried out in appointment, the access start address of each consecutive access is calculated as follows: promptly, flat address with the word of the initial access of the page is an initial value, the consecutive access start address present with respect to preservation, above-mentioned storage address save set, just add the 1st address increment by whenever carrying out the one-time continuous access, whenever carry out the consecutive access of one the 1st count cycle, just add the 2nd address increment, whenever carry out the consecutive access of one the 2nd count cycle, just add that the 3rd address increment calculates, and carry out the storage address of the word of each consecutive access, be by start address, add that the displacement meter of the storage address of each word that carries out above-mentioned consecutive access calculates with respect to above-mentioned consecutive access.

Shown in Figure 1 is that the letter of image processing system of the present invention more constitutes sectional drawing.Shown in Figure 2 is the whole block scheme of the control circuit of image processing system.Shown in Figure 3 is the block scheme of the formation of elementary cell.Shown in Figure 4 is the block scheme of the formation of system's elementary cell.Shown in Figure 5 is the block scheme of the formation of system extension unit.Shown in Figure 6 is the block scheme of image processing circuit.Shown in Figure 7 is the block scheme of the formation of system, control circuit.Shown in Figure 8 is the block scheme of the formation of communication memory access-control scheme.Shown in Figure 9 is the block scheme of the formation of page storage access-control scheme.Shown in Figure 10 is the block scheme of the formation of address control circuit.Shown in Figure 11 is the block scheme of the formation of address generating unit.Shown in Figure 12 is the block scheme of the formation of data control circuit.Shown in Figure 13 is the block scheme that view data transmits the formation of control part.Shown in Figure 14 is the pie graph of timer.Shown in Figure 15 is the block scheme of the detailed formation of image trunk priority degree control part.Shown in Figure 16 is the block scheme of the detailed formation of page storage relative importance value control part.Shown in Figure 17 is the block scheme that terminal counter constitutes in detail.Shown in Figure 180 is one of electronic separation example.Shown in Figure 19 is the inside formation of DRAM.Shown in Figure 20 is the general mode of DRAM and the access sequential chart of fast page mode.Shown in Figure 21 is the general mode of DRAM and the access sequential chart of fast page mode.Shown in Figure 22 is to be used to illustrate the pixel map that constitutes original image.Shown in Figure 23 is to be used to illustrate the memory cell figure that constitutes DRAM.Shown in Figure 24 is the IP address figure of the moving burst accesses of non-rotating access time shift.Shown in Figure 25 is the interior column address deflection graph of piece.Shown in Figure 26 is the interior column address of piece and the graph of a relation of storage address.Storage access calculation flow chart when being non-rotating access shown in Figure 27.Shown in Figure 28 is the IP address figure of the moving burst accesses of rotation access time shift.Shown in Figure 29 is storage access calculation flow chart when rotating access.Shown in Figure 30 is the pie graph of the IP address counting circuit of burst accesses.Shown in Figure 31 is the configuration example of video memory.Figure 32 is the time sequential routine of the video memory IP address counting circuit of Figure 31.Shown in Figure 33 is the pie graph of DRAM control signal generative circuit.Shown in Figure 34 is the JPEG video memory configuration example in when coding.Shown in Figure 35 is the configuration example of utilizing the preservation of JPEG image encoded, transcriber.Figure 36 is to use the exposure device figure of a plurality of laser beam.The state that is to use a plurality of laser beam on photosensitive drums, to expose shown in Figure 37.Shown in Figure 38 is the figure that video memory in the past carries out sequential access line by line.Shown in Figure 39 is that the view data of order line by line is transformed into the circuit diagram of a plurality of laser pumping device drive signals.The burst accesses figure that is to use video memory of the present invention shown in Figure 40.Shown in Figure 41 is the circuit diagram that the view data of burst accesses is transformed into a plurality of laser pumping device drive signals.Shown in Figure 42 is that the piece of the video memory of 1 of 1 pixel constitutes and the rotation diagram of image.Shown in Figure 43 is that the piece of the video memory of 8 of 1 pixels constitutes and the rotation diagram of image.Figure 44 is the figure of image rotating method that explanation utilizes with the piece burst accesses that is unit.

Below, with reference to drawing the 1st example of the present invention is described.

That is, the embodiment that the present invention is used to have the compound image processing system that duplicates, faxes, prints 3 kinds of functions is described.

Shown in Figure 1 is as the in-built summary formation of the digital copy machine of one of image processing system of the present invention example block diagram.

As shown in Figure 1, the digital copy facility have device body 110, in this device body 110, are provided with the scanister 13 that plays the reading device effect described later, and as the duplicator 15 with image processing system function.

On device body 110, be provided with by what clear glass constituted and be used for mounting reading object thing, i.e. the original copy mounting table 112 of original copy D.In addition, on device body 110, also be equipped with the auto document feeder 107 automatically original copy delivered on the original copy mounting table 112 (below be referred to as ADF).This ADF107 sets and is that original copy mounting table 112 opens and closes relatively, its also have make that the original copy D that is positioned on the original copy mounting table 112 and original copy mounting table closely contact compress the original copy function.

ADF107 have mounting original copy D original tray 108, detect the blank sensor 109 have or not original copy, paper taking rollers 114 that more than of original copys are taken out from original tray 108, transmit the original copy that taken out to paper roll 115, the cylinder that comes into line in front that digests the manuscript to 116 and almost cover whole original copy mounting table 112 and the travelling belt 118 that sets.And, on the original tray 108 upwards numerous original copy of mounting be from its nextpage, promptly begin to take out in turn by last page, by come into line cylinder to 116 arrangements after, utilize travelling belt 118 to be sent to the assigned position place of original copy mounting table 112.

Among the ADF107, hold under the arm every travelling belt 118 with come into line the end of cylinder to 116 opposite sides on, be equipped with counter-rotating cylinder 120, non-counter-rotating sensor 121, baffle plate 122, paper ejection drum 123.Original copy D by scanister 13 reading images information described later is sent from original copy mounting table 112 by travelling belt 118, by discharging in counter-rotating cylinder 120, baffle plate 122 and the paper ejection drum 123 original copy row paper portion 124 on ADF107.When reading the back side of original copy, by switching baffle plate 122, the original copy D that sends by travelling belt 118 through 120 counter-rotatings of counter-rotating cylinder after, be sent to the assigned position place of original copy mounting table 112 once more by travelling belt 118.

The scanister 13 that is configured in the device body 110 has the exposure lamp 125 that is positioned in the light source of the original copy on the original copy mounting table 112 as illumination, and the reflected light of original copy D is partial to the 1st catoptron 126 of prescribed direction, these exposure lamps 125 and the 1st catoptron 126 are installed on the 1st carrier 127 that is provided in original copy mounting table 112 belows.

The 1st carrier 127 and original copy mounting table 112 configured in parallel and removable utilize drive motor by there not being the illustrated below that has toothed belt etc. to move back and forth in original copy mounting table 112.

In addition, below original copy mounting table 112 and original copy mounting table 112 dispose movably the 2nd carrier 128 with paralleling.On the 2nd carrier 128, be in the 2nd and the 3rd catoptron 130,131 is installed squarely, these catoptrons are used for the reflected light from original copy D of order deflection by 126 deflections of the 1st catoptron.The 2nd carrier 128 has toothed belt etc. in driven with respect to the 1st carrier 127 by what drive the 1st carrier 127, also moves abreast along original copy mounting table 112 with 1/2 speed with respect to the 1st carrier.

Also have, below original copy mounting table 112, also dispose convergence and carry out the ccd sensor 134 of opto-electronic conversion by the reflected light of image lens 132 convergences and to it from the catoptrical image lens 132 and the reception of the 3rd catoptron 131 on the 2nd carrier 128.Image lens 132 can be provided in movably by driving mechanism and comprise by in the face of the optical axis of the light of the 3rd catoptron 131 deflections, and utilizes self to move and make reflected light form image by desired multiplying power.And then the reflected light of ccd sensor 134 opto-electronic conversion incidents carries out, and the electrical signal of the corresponding original copy that is read of output.

On the other hand, duplicator 15 has the laser explosure device 140 that plays a role as latent image formation device.Laser explosure device 140 has: as the semiconductor laser 141 of light source; Be used for continuous deflection from the shoot laser of semiconductor laser 141 and as the polygon mirror 136 of sweep unit; Drive the polygonal motor (polygon motor) 137 of polygon mirror 136 rotations and double as scan module with regulation rotation number rotation described later; Be used for deflection from the laser of polygon mirror and with the optical system 142 of it guiding photosensitive drums 144 described later.So the laser explosure device 140 that constitutes is fixedly supported on not having on the illustrated support frame of device body 110.

Gauge tap such as the image information of the original copy D that semiconductor laser 141 correspondences are read by scanister 13 or facsimile recorder sending and receiving fileinfo, this laser towards photosensitive drums 144, forms electrostatic latent image by scanning photosensitive drums 144 side faces via polygon mirror 136 and optical system 142 on photosensitive drums 144 side faces.

In addition, duplicator 15 has the photosensitive drums free to rotate 144 as image carrier that is provided in device body 110 substantial middle positions, on the side face of photosensitive drums 144, pass through exposure, can form desired electrostatic latent image from the laser of laser explosure device 140.Around photosensitive drums 144, sequentially dispose: make the charged charger 145 of wearing the regulation electric charge bulging week; Provide as the toner of developer and the imagescope 146 that carries out video picture with the concentration of expectation to the electrostatic latent image that is formed on photosensitive drums 144 side faces; 144 that be made of one with photosensitive drums, be used for the transfer sheet of carton feeding in described later year, promptly duplicate with paper P and peel off charger 147 from what photosensitive drums 144 was separated; Make the toner that is formed on the photosensitive drums 144 look like to copy to and duplicate charger 148 on the paper P; Peel off the separation claw 149 of transfer sheet P from photosensitive drums 144 side faces; What cleaning remained in the swabbing pig 150 of the toner on photosensitive drums 144 side faces and eliminated static on photosensitive drums 144 side faces removes electrical equipment 151.

Bottom in device body 110 disposes the epimere that can extract from device body respectively with being in layered laminate and carries that carton 152, stage casing carry carton 153, hypomere carries carton 154, is mounted with the different transfer sheet of size in the carton in each year.The side of carton is provided with high capacity and adds paper device 155 in these years, and this high capacity adds the transfer sheet P that can hold the high size of frequency of utilization on the paper device 155, for example, can hold about 3000 of the transfer sheet P of A4 size.In addition, high capacity add paper device 155 above, what be mounted with that the double as that can freely load and unload manually gives carton 156 gives carton 157.

In device body 110, be formed with from each year carton and high capacity add that paper device 150 begins to extend and by in photosensitive drums 144 with duplicate the transfer passage 158 of the portion of duplicating between the charger 148, be provided with fixing device 160 in the end of transfer passage 158 with photographic fixing lamp 160a.On the sidewall of the device body 110 of facing fixing device 160, be formed with escape hole 161, on escape hole 161, be equipped with the truing device 180 of single mount frame.

Epimere carry carton 152, stage casing carry carton 153, hypomere carry carton 154, give carton 157 nearby and high capacity add paper device 150 near, be respectively arranged with from carrying carton or high capacity and add the pickup roller 163 of more than ground taking-ups of paper device transfer sheet P.In addition, on transfer passage 158, also be provided with via transfer passage 158 carry the transfer sheet P that takes out by pickup roller 163 a plurality of to paper roll to 164.

The upstream side of photosensitive drums 144 is provided with guide pulley to 165 in transfer passage 158.Guide pulley to 165 in the inclination of the transfer sheet P that proofread and correct to take out, also make toner picture on the photosensitive drums 144 foremost with the matching foremost of transfer sheet P, and with the speed identical with the translational speed of photosensitive drums 144 side faces to duplicating the feeding transfer sheet P of portion.To 165 front, promptly give paper roll 164 1 sides at guide pulley, be provided with the alignment front sensor 166 of the arrival that detects transfer sheet P.

Add the transfer sheet P of more than ground taking-ups of paper device by flowing to guide pulley to 165 to 164 by pickup roller 163 from carrying carton or high capacity to paper roll.And then transfer sheet P is sent to the portion of duplicating after through guide pulley 165 pairs being adjusted foremost.

In the portion of duplicating, be formed on the developer picture on the photosensitive drums 144, promptly the toner picture copies on the transfer sheet P by duplicating charger 148.The effect that the transfer sheet P that duplicates the toner picture is peeled off charger 147 and separation claw 149 is stripped from from the side face of photosensitive drums 144, is sent to fixing device 160 via the belt conveyor 167 that constitutes one of transfer passage 52 portion.And then, by fixing device 160 developer is looked like to dissolve photographic fixing after on the transfer sheet P, transfer sheet P by to paper roll to 168 and paper ejection drum be discharged on the truing device 180 via escape hole 161 169.

Below transfer passage 158, dispose the transfer sheet P counter-rotating of having passed through fixing device 160, and give guide pulley once more 165 ADU 170.ADU 170 have interim storage replication paper P interim storage part 171, from transfer passage 158 begin to diverge and the transfer sheet P counter-rotating of having passed through fixing device 160 and be directed to the inverting channel 172 of interim storage part 171, many ground take out the transfer sheet P that is stored in interim storage part pickup roller 173 and via transfer passage 174 the transfer sheets that pick up be fed into guide pulley to 165 to paper roll 175.In addition, also be provided with the distribution gate 176 that transfer sheet P is distributed to selectively escape hole 161 or inverting channel 172 at the difference portion place of transfer passage 158 and inverting channel 172.

When carrying out duplex printing, the transfer sheet P that has passed through fixing device 160 is directed to inverting channel 172 by distribution gate 176, after the state with counter-rotating is stored in interim storage part 171 temporarily, by pickup roller 173 and be sent to guide pulley to 165 via transfer passage 174 to paper roll 175.And then transfer sheet P is delivered to the portion of duplicating once more after guide pulley is put in order 165, and prints the toner picture at the back side of transfer sheet P.After this, transfer sheet P is discharged to truing device 180 via transfer passage 158, fixing device 160 and paper ejection drum 169.

Truing device 180 is to be the device of unit with a file of formation of bail bookbindery discharge with the portion.Fairlead 181 is just near being repaired by the card side when discharging the transfer sheet P of a process classification from escape hole 161.Be over then paper pressing arm 152 compresses the portion of being discharged is the transfer sheet P of unit and binds fixing by stapler 183 if all discharge.After this, fairlead 181 is stepped back, and the transfer sheet P that fixedly is over of bookbinding is that unit is trimmed device and discharges cylinder 185 and be discharged to and repair discharge dish 184 with part.The slippage of finishing discharge dish 184 determines the degree that it should descend by the number of the transfer sheet P that is discharged, and a unit of every discharge just descends a step.In addition, the fairlead 181 of the transfer sheet P that discharged of finishing is positioned to bump less than putting to be loaded on the finishing discharge dish 184 and has bound on the height and position of the transfer sheet P that fixes.

Other has, and finishing discharge dish 184 is connected when classification mode by part and moves in travel mechanism's (not diagram) of (for example, forwards, backwards about 4 directions).

Shown in Figure 2 is the integral body formation block diagram of image processing system, and this device is made of following three systems: promptly, elementary cell 1, it can realize basic copy function; System's elementary cell 2, it has preserves view data temporarily or preserve the page storage of view data when editing and processing view data and duplicating when this device is connected with other system; System extension unit 3, it has and is used for electronization ground and semipermanent preserves by the optical disc apparatus of the view data of above-mentioned elementary cell 1 input etc., and have when between with other system, carrying out the exchange of view data or control data, can be transformed into view data and control data the control device of other system of systems, picture format.

Above-mentioned elementary cell 1 is connected by the basic portion system interface 4 of exchanging control data and the basic portion image interface 5 of exchange image data with system elementary cell 2.

Said system elementary cell 2 is connected by the extension system interface 6 of exchanging control data and the extension image interface 7 of exchange image data with system extension unit 3.

Be that above-mentioned elementary cell 1 directly is not connected with system extension unit 3, the exchange of control data and view data must be undertaken by system's elementary cell 2.

This image processing system utilization has or not the connection of system's elementary cell 2 and system extension unit 3 that 3 kinds of forms can be arranged.

Promptly the 1st form is to have only the formation of elementary cell, and the basic function under this formation is a copy function, dwindles the replication processes that simple editing and processing such as processing, shielding/deburring processing accompanies with amplification and also is fine.

The 2nd form is the form of connected system elementary cell 2 on elementary cell 1, in this form, except that the copy function of elementary cell 1, can also use the page storage of interim preservation view data to carry out the rotation processing of image, the editing and processing such as synthetic processing of a plurality of images.In addition, on this system's elementary cell 2, can also connect duplicator controller 9, so that except that the system extension unit 3, FAX (facsimile recorder) unit 8 of communication loop control device such as formation facsimile recorder and the duplicator of elementary cell 1 use as the remote copy machine of control machines such as external personal computer, and can give other system or machine via communication loop by this FAX unit 8 image, perhaps receive view data by communication loop from other system or machine on the contrary, the view data that is received is sent to elementary cell 1 by duplicator printout described later.

The 3rd form is the form of representing with the form that connects elementary cell 1, system's elementary cell 2 and system extension unit 3 as shown in Figure 2.

In this form,, can also realize following each function: promptly, preserve the data preservation/management function of the view data of view data and administrative institute preservation except the function of the 1st and the 2nd form electronicly and semipermanently; Utilization sends image by the LAN loop to other system or machine by LAN described later (LAN) circuit control device, perhaps on the contrary by system or the machine image data transmission receiving function that receive the LAN of view data of LAN loop from other; By general-purpose interface the printing control code of being sent by personal computer is transformed into view data, and passes through the printing function of the page storage of system's elementary cell 2 by the above-mentioned view data of duplicator printout of elementary cell 1.

Above-mentioned elementary cell 1 as shown in Figure 3, by the system CPU 11 that constitutes the control part body, control panel 12, as constituting from the scanister 13 of the input media of original copy reading images, image processing circuit 14 and as the duplicator 15 of output unit with operating portion and display part.Said system CPU11 is connected by the duplicator 15 that basic portion system bus 16 carries out the output unit of image formation output with control panel 12, scanister 13, image processing circuit 14 and conduct, and can control them.This basic portion system bus 16 is connected on the above-mentioned basic portion system interface 4.

Above-mentioned scanister 13 has the CCD line sensor of being made up of a plurality of (1 row) photo-sensitive cell that is configured to the row shape (not diagram), according to read the original image of mounting on document board (not having diagram) line by line from the indication of system CPU 11, after image deep or light being transformed into 8 numerical data, export to image processing circuit 14 as the time series numerical data together by scanister interface and synchronizing signal.

Above-mentioned duplicator 15 is by at laser optical system (do not have diagram) with made up image forming part (the not illustrating) formation that can form the electronic photo mode of image on transfer sheet, it is a device of working as follows, promptly, be synchronized with the Digital Image Data of synchronizing signal according to indication by the duplicator interface from 4 of image processing circuit 14 inputs from system CPU 11, when the laser of the pulse width of utilizing the correspondence image size of data photosensitive drums (not diagram) go up form electrostatic latent image after, utilize the visual above-mentioned electrostatic latent image of visualization device (not diagram), again by reproducing unit (not have diagram) visual copying image to transfer sheet, at last by the image on fixing device (not having to illustrate) the photographic fixing transfer sheet and export this transfer sheet.

Above-mentioned control panel 12 is made of the expression portion of the image frame in the state of the operating portion of the operator scheme of setting this device or parameter and expression system or the page storage that expression is kept at system's elementary cell 2.

Said system CPU11 also can control each one of system described later elementary cell 2.

Above-mentioned image processing circuit 14 as shown in Figure 4, by smoothing edge sharpening circuit 14a, editor/walking circuit 14b, amplification/dwindle circuit 14c and greyscale transformation circuit 14d forms.

The noise that above-mentioned smoothing edge sharpening circuit 14a sneaks into when utilizing the smoothing circuit to remove reading images is again by the edge sharpening circuit sharpening edge fuzzy because of smoothing produces.

Above-mentioned editor/walking circuit 14b is the piece that carries out with the simple editing processing of behavior unit, and mobile processing, shielding/deburring of carrying out as line direction are handled.

Above-mentioned amplification/dwindle circuit 14c utilizes the combination of corresponding re-treatment of specifying the pixel that becomes multiplying power or difference processing and interpolation processing to amplify to dwindle processing.

Above-mentioned greyscale transformation circuit 14d usable floor area gray scale method is transformed into the view data of 8 of the every pixels that is read by above-mentioned scanister 13 gray level of appointment.And then, be sent to duplicator 15 or be sent to said system elementary cell 2 with view data form through the view data after the greyscale transformation as 4 of every pixels of duplicator figure place by scanister data bus 17 and above-mentioned basic portion image interface 5.

When usable floor area gray scale method is carried out the gray scale processing, carry out the gamma correction of the input-output characteristic of above-mentioned duplicator 15 simultaneously.

Said system elementary cell 2 is provided with as shown in Figure 4: preserve the page storage 28 as the bit image data that read by scanister 13 of view data and the coded data after this view data of compression etc.; The control information of CPU in system CPU 11 in the control elementary cell 1 and the system extension unit 3 is communicated by letter, or control from elementary cell 1 and system extension unit 3 to the system, control circuit 21 of the access of page storage 28; Generate the page storage address control circuit 26 of the address of page storage 28; Carry out the image bus 29 that the data between each equipment transmit in system's elementary cell 2; The page storage data control circuit 27 that control data transmits when the data transmission of being undertaken by this image bus 29 between page storage address 28 and the miscellaneous equipment.

Page storage 28 is made of image-region (perform region, the video memory) 28a of the view data of preserving one page and coding region (file area) 28b of the coded data of preserving compressed some pages.Above-mentioned image-region 28a is made of DRAM described later.

In addition, also be provided with view data I/F210, resolution conversion 2 value rotation circuits 212 and compression/expansion circuit 211.Wherein, view data I/F210 conversion image data when transmitting elementary cell 1 and view data by basic portion image interface 5; Resolution conversion 2 value rotation circuits 212 are when the different machine of resolution sends view data, view data is transformed into the resolution of other machine, or be transformed into the resolution of the duplicator 15 of elementary cell 1, or carry out 90 of 2 value view data and spend rotation processing receiving view data from the different machine of resolution; Compression/expansion circuit 211 is used for compressing image data, so that can be to importing for carrying out the equipment that facsimile transmission or CD preserve compressing image data and send, receive view data, or expansion be in be compressed form view data to be used for by duplicator 15 visual original images.

In addition, also be provided with: the working storage of the control information of using by the FONT storer of preserving text font, interim saved system CPU11, preserve the system storage (ROM/RAM) 24 that the program storage etc. of the handling procedure when using system elementary cell 2 is handled constitutes; Be used for carrying out at a high speed the system DMA controller 23 that the data between the equipment of basic portion system bus 16 transmit; Between duplicator controller 9 and system CPU 11, carry out the control information exchange, or between duplicator controller 9 and image bus 29, carry out changing when view data transmits the duplicator control unit interface 213 of above-mentioned control information and view data.

And then, also be provided with: be connected on the system, control circuit 21, be used to preserve the communication memory 25 of control information when between the CPU of system CPU 11 and system extension unit 3, carrying out control information communication; Be connected on the view data I/F210, by duplicator 15 output image datas the time, be used to that view data is revolved and turn 90 degrees or the many-valued rotating memory 214 of 180 degree outputs.

Other has, according to selecting also can connect above-mentioned FAX unit 8 and duplicator controller 9.

Said system expanding element 3 is made of following each one as shown in Figure 5, comprising: by the extension CPU 31 of inner each equipment of extension system bus 43 controls; Be controlled at the expansion dma controller 32 that the data on the extension system bus 43 transmit; General isa bus 44; The isa bus controller 33 of contact extension system bus 43 and isa bus 44; Be connected in extension system bus 43 and be used for preserving the save set of view data electronicly, as hard disk unit 35, as the hard-disk interface 34 of its interface; Be connected in above-mentioned isa bus and be used for preserving the save set of view data electronicly, as optical disc apparatus 38, as the CD interface 37 of its interface; Be used to realize the LAN circuit control device (LAN) 41 of LAN function; Be used to realize the duplicator controller control device 40 of printing function; Have the G4FAX control circuit 39 of G4FAX control function, the expansion scsi interface 42 that when connecting SCSI specification equipment, uses; Be used for the extension image bus 45 of exporting to system's elementary cell 2 from the view data of above-mentioned duplicator controller control device 40 by above-mentioned expanded images interface 7; Carry out the memory buffer 36 of interface when between above-mentioned extension system bus 43 and extension image bus 45, carrying out exchanges data.

Have, above-mentioned CD interface 37, optical disc apparatus 38, G4FAX control circuit 39, duplicator controller control device 40, LAN circuit control device 41, expansion scsi interface 42 are options again, for can be from the system extension unit 3 formations of installing.

Above-mentioned optical disc apparatus 38 is connected with isa bus 44 by interface 37, and above-mentioned extension CPU 31 uses the SCSI instruction by extension system bus 43, isa bus controller 33, the above-mentioned optical disc apparatus 38 of isa bus 44 controls.

Above-mentioned LAN circuit control device 41 by according to the control of the standard of the network system that is connected with the circuit controls portion that communicates by letter of other machine on the network and control data or view data, the interim preservation from the communication control data of LAN or view data or from the control data of system extension bus or the common storage of view data, and the system extension bus interface constitutes.

Above-mentioned duplicator controller control device 40 comprises by constituting with the lower part: and carry out between the personal computer control code or view data exchange, personal computer with duplicator output specification with reference to parallel interface; Obtain with the page storage 28, system extension portion image bus 45, the system extension image bus interface of communicating by letter that are used for the bit image data are sent to system's elementary cell; The view data that view data in the control device transmits transmits control part; Explanation is from the control code of personal computer, notify extension CPU 31 control information by extension system bus 43 and isa bus 44, perhaps explain printing control code from personal computer, after it is for conversion into an information, again position information is kept at control device on the storer in the device; Obtain the system extension bus interface of communicating by letter with isa bus 44.

Below, the formation of wanting portion and function in the said system elementary cell 2 are elaborated.

Said system control circuit 21 by constituting with the lower part, comprising as shown in Figure 7: between control said system CPU11 and the extension CPU 31, control information communication, communication memory access-control scheme 401; Obtain the communication memory interface 402 of communicating by letter with above-mentioned communication memory 25; Control from elementary cell 1 and system extension unit 3 to the page storage access-control scheme 403 of the access of page storage 28; The basic portion system bus interface 405 that distributes above-mentioned control information or image information on the address of control information that decoding is transported by the ultimate system bus by the system CPU 11 of elementary cell 1 or the image information that transports simultaneously and the piece in qualified system elementary cell 2; The address of control information that decoding is transported by system extension unit 3 or the image information that transports simultaneously also is assigned to the system extension bus interface 406 on qualified in the circuit; The device (CPU31 of system extension unit 3 and dma controller 32) that the device of the page storage access on can carrying out basic portion system bus 16 (CPU11 in the elementary cell and dma controller 22) maybe can carry out the page storage access on the system extension bus 43 is got in touch the page storage interface 404 that the view data between above-mentioned page storage access-control scheme 403 and the page storage 28 exchanges during by the view data in the system bus access page storer 28 separately.

Above-mentioned image memory access control circuit 401 is at the CPU31 of the CPU11 of elementary cell 1 and system extension unit 3, when communicating the operation of storer 25 and control code by the communication memory interface 402 in the system, control circuit 21, control the access of this communication memory 25.

Above-mentioned communication memory 25 is mapped with the storage space of the CPU31 of the CPU11 of elementary cell 1 and system extension unit, by its specific zone separately of access, can carry out the reading and writing of data to above-mentioned communication memory 25.

Above-mentioned communication memory access-control scheme 401 constitutes by reconciling circuit 410, communication memory access sequence generator 412, two-way choice device 413 and interrupt control circuit 414 as shown in Figure 8.

Above-mentioned conciliation circuit 410 carry out the CPU11 of elementary cell 1 and system extension unit 3 CPU31 which have the control of communication memory access priority.That is, simultaneously during accessing communication storer 25, allow a certain side's access according to the relative importance value that sets, and allow the opposing party's access wait at the CPU31 of the CPU11 of above-mentioned elementary cell 1 and system extension unit 3.

Above-mentioned communication memory access sequence generator 412 is according to the requirement control signal that 25 outputs are read or write to communication memory of the CPU that is allowed to.

Above-mentioned two-way choice device 413 is according to the conciliation result who reconciles circuit 410, and the clock signal of the control device that is allowed to being exported, exported with respect to the address and the communication memory access sequence generator 412 of communication memory 25 is synchronous and export to communication memory 25.And the communication information (data) and the address information that export together CPU handle that is allowed in write operation and address are exported to communication memory 25 simultaneously.In read operation, then be used to from the CPU that is allowed to about the address of communication memory 25 and the communication information of reading from communication memory 25 by the clock signal input of communication memory access sequence generator 412 outputs, and export to the CPU that is allowed to.

Above-mentioned page storage access-control scheme 403 as shown in Figure 9, by reconciling circuit 430, data register 431,432,436,437, address register 433, two-way choice device 434 and page storage access sequence generator 435 constitute.

Above-mentioned conciliation circuit 430 carries out the relative importance value control of page storage access of the CPU31 of the CPU11 of elementary cell 1 and system extension unit 3.Simultaneously during accession page storer 28, it allows the CPU access of a certain side according to the relative importance value that configures at CPU11 and CPU31, and allows the access of CPU of opposite side wait for.

Above-mentioned page storage access sequence generator 435 outputs to address control circuit 26 to the control signal that reads or writes with respect to page storage 28 according to the requirement that is allowed to CPU.

Above-mentioned two-way choice device 434 is according to the conciliation result who reconciles circuit 430, and is synchronous and export to address control circuit 26 the clock signal of exporting about the address of page storage 28 and page storage access sequence generator 435 of the CPU output that is allowed to.And the CPU that is allowed in write operation is that the information (data) that export together handle and address is exported to data control circuit 27 together with address information.And in read operation, then be to be used to import the view data that from page storage 28, reads out via data control circuit 27, and export to the above-mentioned CPU that is allowed to from the clock signal that address and the page storage access sequence generator 435 about the page storage 28 that are allowed to CPU are exported.

Above-mentioned data register 431 and data register 432 are registers of interim storage data when elementary cell 1 access page storer 28, and above-mentioned address register 433 is registers of address of temporarily preserving the page storage 28 of elementary cell 1 output.

Here, when elementary cell 1 was used data register 431 access page storeies 28, the address of elementary cell 1 output was temporarily stored in the address register 433, exports to page storage 28 by address control circuit 26 again.In contrast, when elementary cell 1 was used data register 432 accession page storeies 28, the address of elementary cell 1 output was left in the basket, and the address generator of address control circuit 26 outputs to the address on the page storage 28 according to set information.

In addition, above-mentioned data register 436 and data register 437 are registers of interim storage data during 3 access page storeies 28 in the system extension unit, in the system extension unit during 3 accession page storeies 28, two registers all output to the address on the page storage 28 according to the set information of the address generator of address control circuit 26.

The system DMA controller 23 of elementary cell 1 is the transfer control that does not carry out the data transmission of each equipment room on the basic portion system bus 22 by the CPU11 of elementary cell 1 with hardware at high speed.

As using said system dma controller 23 to carry out the processing that data transmit, transmit just like inferior data, promptly have: the transmission of the packed data (coded data) when FAX transmission reception is handled between page storage 28 and the FAX unit 8; Be used in the page storage 28 of the image on the display page storer 28 on the control panel 12 and the transmission of the view data between the control panel 12; Be used in the system storage 24 of display-operation picture on the control panel 12 and the data transmission between the control panel 12 etc.

Generate above-mentioned page storage 28 the address address control circuit 26 as shown in figure 10, constitute by following part, promptly comprise: the transmission control sequence generator 610 of various transfer sequences is carried out in the request of sending according to image bus 29; The conciliation portion 611 that the request of the request of image bus 29 and system bus 22 is mediated; Be created on address generating unit 612 by the various storage addresss of a plurality of passages in the transmission of image bus 29; Switching is by the address of these address generating unit 612 outputs and the selector switch 613 of system address; Generate the address of DRAM (image-region 28a) and the DRAM control part 614 of control signal.

Above-mentioned address control circuit 26 reception are from the memory access requests of image bus 29 and system bus 22 these two systems.This request is mediated by conciliation portion 611, and the data transfer process of the triumph side of mediating.

When the mediation request of system bus side was won, the system address of being selected by selector switch 613 was imported into DRAM control part 614.The DRAM control part also produces the needed control signal of reading and writing when the address mapping of input is become the address of DRAM (image-region 28a).

In addition, be transfused to the address tunnel signal that has and import together from the request of image bus 29 on the control sequence generator 610 transmitting, and one of select a plurality of addresses generating unit in address generating unit 612.If the mediation request of image bus 29 sides is won, then export the storage address of selected passage, and it is input to DRAM control part 614 by address generating unit 612.

Above-mentioned address generating unit 612 as shown in figure 11, by the fifo address maker 635,636 of two-dimensional address maker 613,632,633,634,2 passages of 4 passages and by the channel selecting signal of transfer sequence generator output, add that one the selector switch of selecting in the storage address that they produced 637 constitutes.

By using such two-dimensional address maker that generates various addresses, can transmit, rotate and read or read repeatedly any rectangular area of page storage 28, in addition, by using the two-dimensional address maker of 2 passages, can do between the arbitrary region of page storage 28 that image moves, rotates, conversion in length and breadth, repeatedly, picture editting such as mirror image.

Fifo address maker 635,636 generates and is used for page storage 28 is controlled needed state as fifo address, the FIFO that the FIFO storer uses.

As state FIFO full (fifo area is full of the not state of sense data), FIFO sky (fifo area does not have the not state of sense data), FIFO half (fifo area has the state of not sense data over half) are arranged.Also have, can know data volume and the vacant capacity that enters FIFO by the register of reading FIFO from system CPU.

Carry out FIFO control by these states, be sent to miscellaneous equipment or when the equipment of image bus 29 sends system bus 22 at equipment from image bus 29, can can realize that data at a high speed transmit with the storer alleviation transfer rate separately or the difference of transmission sequential of FIFO.

In addition, fifo address maker 635,636 can use the flat address maker of 1 passage that is had as 2 passages when not carrying out the control of FIFO.

Above-mentioned data control circuit 27 as shown in figure 12, by constituting with next part, promptly comprise: the data of each equipment room transmission on the image bus 29 in the control system elementary cell 2, and the view data that the data between equipment on the image bus 29 and the page storage 28 transmit transmits control part 701; Carry out the image processing part 702 of blit and all grating computings (logical operation); The system interface 703 that connects data when the CPU31 of the CPU11 of elementary cell 1 or system extension unit 3 passes through said system control circuit 21 accesses (read/write) page storage 28; Writing in the processing of page storage 28, the result is reconciled in page storage access according to above-mentioned address control circuit 26, selection is to allow to transmit the data access from the equipment on the image bus 29 that control part 701 transports by above-mentioned view data, still allows the selector switch 704 from the data access of CPU (CPU31 of the CPU11 of elementary cell 1 or system extension unit 3) that transports by system interface 703; Reading the processing from the data of page storage 28, the result is reconciled in page storage access according to above-mentioned address control circuit 26, selection is that the equipment on the image bus 29 that transmits control part 701 by above-mentioned view data is carried data, still to the selector switch 705 of carrying data by the CPU (CPU31 of the CPU11 of elementary cell 1 or system extension unit 3) of system interface 703.

Below, the control that above-mentioned view data shown in Figure 12 is transmitted control part 701 describes.The view data transmission form that view data transmits control part 701 controls has 2 kinds of following forms.

One of form is that the data between the I/O equipment on the image bus 29 of system's elementary cell 2 transmit, source (transfer source)/destination (transmission target) is transmitted the read cycle of the data buffer in the control part 701 and two cycles of write cycle time that the data on the data buffer write destination address is constituted by from the source data being taken into view data all on image bus 29.

Another form is that I/O equipment and the data between the page storage 28 on the image bus 29 of system's elementary cell 2 transmit, and two cycles of data transfer cycles of being transmitted between data transfer cycles, data buffer and the page storage 28 between the data buffer in the control part 701 by I/O equipment and view data constitute.

Owing to be independent of image bus 29 between page storage 28 and the data buffer, so two cycles can parallel work-flow.

Also have, view data transmits control part 701 and can specify the data of above-mentioned 2 forms on 8 passages to transmit, and the data that can carry out 8 passages simultaneously transmit.

Above-mentioned view data transport unit 701 is made of data buffer 740, image trunk priority degree control part 741, transmission control sequence generator 742, page storage relative importance value control part 743, page storage sequential control portion 744, terminal counter 745, interrupt control portion 746, control bus interface 747, parameter register 748 and I/O impact damper 749 as shown in figure 13.

Above-mentioned data buffer 740 has to be preserved from the data in source and has the data register of port number temporarily in data transmit.

Above-mentioned image trunk priority degree control part 741 inputs are from the data transmission requests (REQ) of the equipment on the image bus 29, and relative importance value according to the rules determines to allow the equipment of data transmission, and notify the equipment that is allowed to begin data and transmit (ACK).

Above-mentioned transmission control sequence generator 742 generates the data transmission clock signal of determined source device and destination equipment room and exports to image bus 29 according to the relative importance value control result of above-mentioned image trunk priority degree control part 741.

The request signal of above-mentioned page storage relative importance value control part 743 Input Data Buffers 740 outputs, and relative importance value is according to the rules determined the data-transmission channel between page storage 28 and the data buffer 740.

Above-mentioned page storage sequential control portion 744 transmits clock signal and outputs to address control circuit 26 according to page storage 28 and the data between the data buffer 740 that the relative importance value control result of page storage relative importance value control part 743 generates the transmission passage that is determined.Transmission request signal from data buffer 740 is carrying out writing in the processing page storage 28, when the data from the equipment on the image bus 29 are in the state that is stored in the data buffer 740, and carry out from the data of page storage 28 read handle, when data are not stored in data buffer 740 internal states, all be output in the page storage relative importance value control part 743.

Above-mentioned parameter register 748 is to be used to set each transfer source that transmits passage, transmission destination, transmission byte number, the register of the Interrupt Process when having or not transmission to finish etc.

Above-mentioned image bus 29 has 32 data width, always no matter the bit width of each pixel transmits as the data of what carrying out 32.For example, when from scanister 13 2 values (1/pixel) when data write page storage 28, be once 32 pixel datas to be transmitted control part 701 from view data I/F210 via view data to send page storage 28 on image bus 29, and to many-valued (4/pixel) data being write the situation of page storage 28, then be the data that once on image bus 29, transmit 8 pixels.32 changes of data are carried out respectively by the figure place of corresponding each pixel of each equipment on the image bus 29.

In addition, on the system bus 16 of Fig. 3, be connected with timer 900.This timer 900 as shown in Figure 4, by timer control part 901, reference clock generative circuit 902, reference clock frequency dividing circuit 903, down counter 904 constitutes.

By system bus 16, set by the frequency dividing ratio of carrying out reference clock frequency dividing circuit 902 by system CPU 11 for time control part 901, down counter 904 countings begin and stop control.

Also have, time control part 901 utilizes from the carry of the down counter 904 outputs signal that successively decreases can produce the look-at-me of relative system CPU11.

Reference clock produces circuit 902 and utilizes crystal oscillator to produce the standard square wave of 25MHz.

Reference clock frequency dividing circuit 903 is according to the setting from system CPU 11, the reference clock frequency number that is 1/n with any frequency dividing ratio frequency division of from 1/1 to 1/65536.

Down counter 904 is scale-of-two down counters of 32 and is synchronized with frequency-dividing clock and carries out countdown.The initial value of this down counter 904 is set by system bus 16 by system CPU 11.

Also have, if produce on the down counter 904 carry successively decrease (by 0 beginning repeat descend) then automatically be set at the initial value that sets by system CPU 11 last time.Whenever the value of this down counter 904 can read from system CPU 11 via system bus 16.

In addition, down counter 904 countdowns begins and stops by the counting gating signal control from 901 outputs of timer control part.

Below, with reference to Figure 15 the detailed formation of the image trunk priority degree control part 741 of Figure 13 is described.Image trunk priority degree control part 741 is made of the request generating unit 912 that the image bus transmits 911,8 passages of request screened circuit of 910,8 passages of mediation request portion.

Request generating unit 912 transmits independent existence the on the passage in each of 8 passages.Input has the image bus to transmit request signal and channel buffer state on the request generating unit 912 of each passage, generates inner effective transmission request when both conditions are met.The image bus transmission request signal here is that the equipment requirements on being connected image bus 29 carries out being become when data transmit effective signal with image bus 29.The state of channel buffer is to represent respectively to transmit the signal that passage carries out the state of the data buffer 740 that Data Receiving uses, and state that valid data do not enter the state of " sky " of data buffer of its passage and " expiring " that valid data have entered data buffer two states is altogether arranged.

To data impact damper 740 equipment being read the transmission situation by image bus 29 equipment, at the buffer state of the data buffer of the passage of wanting to transmit is " sky " and when being effective from the request signal to this passage of equipment, generates inner effective transmission request by request generating unit 912.

In addition, to writing the transmission situation by the equipment of 740 pairs of image bus 29 equipment of data buffer, in the data buffer 740 of the passage of wanting to transmit, there is active data, the state of impact damper is " expiring " and when being effective from the request signal to this passage of equipment, generates inner effective transmission request by request generating unit 912.

Whether the control of request screened circuit 911 is effective by the transmission request that the request generating unit 912 of leading portion makes.

Transmit the passage gating determine this channel transfer allow forbid.

TC shielding is the operation that is used to carry out conveying capacity control, preestablishes to want the number of words that transmits on terminal counter 745, if the transmission of regulation number of words finishes, then the TC shielding is for effective status and forbid the transmission of this passage.When not carrying out this conveying capacity control, can utilize to set to make the TC shielding always be in disarmed state.

FIFO control shielding when carrying out FIFO control, control this channel transfer allow forbid that FIFO control shielding is forbidden transmitting with effective status, disarmed state allows to transmit.

According to selecting from the setting of system CPU 11 is to carry out FIFO control according to the fifo status from fifo address maker 635,636, still the comparative result according to the transmission comparer of terminal counter 745 carries out FIFO control, or does not carry out FIFO control.When not carrying out FIFO control, make FIFO control shielding always keep disarmed state by setting.

The image bus transmits mediation request portion 910 and reconciles the transmission request of 8 passages of asking screened circuit 911 generations and select 1 passage, again the equipment of selected passage is exported the image bus transmission answer signal that expression accepts request and allows transmission.The equipment that receives this answer signal transmits at image bus 29 enterprising line data.

Send simultaneously when transmitting request at a plurality of passages, the relative importance value of mediating is controlled at a passage 1 to 8 and during for ring-type, allows the relative importance value that last time carried out the passage that transmits be minimum cycle control.Thus, even if 8 passages all send the request of transmission continuously, because of it must sequentially be done by turns in 8 times that are carried out are transmitted, so, but each passage transmits equably.

Below, with reference to Figure 16 the detailed formation of the page storage relative importance value control part 743 of Figure 13 is described.This page storage relative importance value control part 743 is made of the request generating unit 923 that page storage transmits request screened circuit 922,8 passages of mediation request portion 921,8 passages.

Request generating unit 923 independently exists at each transmission passage of 8 passages.Input has the channel buffer state on the request generating unit 923 of each passage, generates inner effective transmission request when satisfying the condition of channel buffer state.

The channel buffer state is to represent respectively to transmit the signal that passage carries out the state of the data buffer 740 that data buffering uses, and state that valid data do not enter the state of " sky " of data buffer 740 of its passage and " expiring " that valid data have entered data buffer two states is altogether arranged.

To 740 memory read transmits situation from page storage 404 to data buffer, be " sky " at the buffer state of the data buffer 740 of the passage of wanting to transmit, in the time of promptly can receiving data, generate inner effective transmission request by request generating unit 923.

In addition, to 404 memory write transmits situation from data buffer 740 to page storage, in the data buffer 740 of the passage of wanting to transmit, there is active data, when buffer state is " expiring ", generates inner effective transmission request by request generating unit 923.

Whether the control of request screened circuit 922 is effective by the transmission request that the request generating unit 923 of leading portion makes.

Transmit the passage gating determine this channel transfer allow forbid.

TC shielding is the operation that is used to carry out conveying capacity control, preestablishes to want the number of words that transmits on terminal counter 745, if the transmission of regulation number of words finishes, then the TC shielding is for effective status and forbid the transmission of this passage.When not carrying out conveying capacity control, can utilize to set to make the TC shielding always be in disarmed state.

FIFO control shielding when carrying out FIFO control, control this channel transfer allow forbid that the effective status of FIFO control shielding transmits for forbidding, disarmed state is for allowing transmission.

According to selecting from the setting of system CPU 11 is to carry out FIFO control according to the fifo status from fifo address maker 635,636, still the comparative result according to the transmission comparer of terminal counter 745 carries out FIFO control, or does not carry out FIFO control.Utilizing to set when not carrying out FIFO control makes FIFO control shielding always be in disarmed state.

Page storage transmits mediation request portion 921 and reconciles the transmission request of 8 passages of asking screened circuit 922 generations and select 1 passage, the selection signal (RCHN) of the address generator of setting on the selected passage is outputed on the address control part 26 again.

Send transmission request situation simultaneously for a plurality of passages, when the conciliation relative importance value of mediating is controlled at a passage 1 to passage 8 and for ring-type, carry out the relative importance value of the passage that carried out last time transmitting is made as minimum cycle control.Therefore, even if 8 passages all send the request of transmission continuously, because of it must be sequentially to do by turns in 8 times that are carried out are transmitted, so, but each passage transmits equably.

Below, with reference to Figure 17 the detailed formation of the terminal counter 745 of Figure 13 is described.Terminal counter 745 is to calculate the device of the transmission number of words of each passage in each passage, is connected one 4 and is transmitted number comparers 933 and constitute by the successively decrease transmission number of words counter 932 of signal generating unit 931,8 passages, per two passages of counting.

Counting successively decrease signal generating unit 931 relatively based on the conciliation result's of image trunk priority degree control part 741 the transmission channel signal and the transmission number of words counter 932 of selected passage, transmit after the end signal output counting signal that successively decreases.

Transmission number of words counter 932 is that of its channel image bus 29 of every end transmits just 32 scale-of-two down counter of countdown.Here, the initial value of counter 745 is set by system bus 16 by system CPU 11.If produce carry successively decrease (since 0 to decline) just outlet terminal count signal.

Whenever transmit the value of number of words counter 932 can be read by system bus 16 by system CPU 11.

The terminal count signal of interrupt mask circuit 934 relative 8 passages carry out to the interruption of system CPU allow forbid, and get they " or " the result export as the terminal count look-at-me.The setting that allows to forbid of each passage is undertaken by system CPU 11.

Transmit the relatively transmission number of words of two passages of number comparer 933, and when transmitting number of words and equate as a comparison the result make and be output as effectively.

In addition, transmitting number comparer 933 can be by setting the transmission number of words separately that will compare by each integral multiple comparison arbitrarily.Usually setting each is one times of use.For example, be that 2 times of B are 1 times if set A for two passages of A, B, then when the transmission number of words of A reach B the transmission number of words 1/2 the time comparative result for effective.This comparative result is used to use as the control signal of carrying out FIFO when control between two passages.

Below, the operation in as above such formation is described.At first, to describing from the basic operation of scanister 13 to page storage 28 input image datas.The image output data of 8/pixel of the original copy that scanister 13 is read is transmitted to image data interface 210 by image processing circuit 14 as the scanister view data of 8/pixel or 4/pixel or 2/pixel or 1/pixel, compile a plurality of pixels (4,8,16,32 pixel) that the scanister view data is arranged in these image data interface 210 inside, and send data control circuit 27 to via image bus 29DMA as the transmission data of 32 units.

32 the writing of scanister view data carried out in the addresses of the page storage 28 that 27 pairs of data control circuits generate at address control circuit 26.

Below, the processing of the view data of compressed page storer 28 is described.Page storage 28 logically is image-region 28a that preserves view data and the coding region 28b that preserves the coded data of doing overcompression by difference.

View data transmits on the control part 701 and is set with 2 passages, that is, as transmit passage by the image-region 28a of page storage 28 to the image input channel of compression elongation circuit 211 with output to the passage of the coding region 28b of page storage 28 by the coding that circuit 211 is extended in compression.

In addition, by the transmission destination of coding output as hard-disk interface 34 or CD interface 37, can be on the recording medium of low level unit price the more a large amount of image of record.

After having carried out all setting of compression processing on the compression elongation circuit 211, carry out the coding sign on.

View data is read and is input to compression elongation circuit 211 from page storage 28.211 pairs of images of compression elongation circuit are encoded and coding are outputed on the coding region 28b of page storage 28.

Below, the extension process of the page storage 28 that is interpreted into the image encoded data is described.Transmit on the control part 701 in view data, compression is extended the coding input of circuit 211 and by the image output of compression elongation circuit 211 view data of the image-region 28a of page storage 28 exported two passages as transmitting the coding region 28b of path setting by page storage 28.In addition, by the transfer source of coding input as hard-disk interface 34 or CD interface 37, can on the recording medium of low level unit price more, write down a large amount of image of being stored.

After having carried out all setting of extension process on the compression elongation circuit 211, carry out the decoding sign on.

Coded data is read and is imported into from page storage 28 the compression elongation circuit 211.And then 211 pairs of images of compression elongation circuit are decoded and the view data of separating are outputed among the image-region 28a of page storage 28.

Below, instruction page storer 28 is to the printout operation of duplicator 15.At first, by page storage 28 to duplicator 15 output image datas.After the view data of 32 units that the address of the page storage 28 that is generated by address control circuit 26 is specified is transmitted to data control circuit 27, sent to image data interface 210 via image bus 29 by DMA again.

At image data interface 210, carry out from the figure place of view data to 1 pixel of 32 be the conversion of 4/pixel or 2/pixel or 1/pixel being used for to duplicator 15 outputs, and transmit by image processing part 14 and to export to duplicator 15.

As mentioned above, carried out following basic operation, that is: by the image input operation of scanister 13 to page storage 28; Image Data Compression on the page storage 28 is handled; The view data of being encoded is to the extension process of page storage 28; By the printout operation of page storage 28 to duplicator 15.

Below, with reference to Figure 18 electronic separation is described.Electronic separation is exactly to read many original copys that become object of classification, and it once had been stored in the memory storages such as semiconductor memory or hard disk CD, then the image of being stored by order number output arbitrarily arbitrarily.By such way, can and put the sequence of pages of printout in order the page of back input elder generation's line output, and export the many parts of printouts that sequence sequence of pages.Figure 18 is one of electronic separation example, as shown in the figure, if order is imported 4 original copys, when exporting in groups, begins sequentially the needed umber of output continuously from the original copy of last input.Because transfer sheet is from beginning to stack the hard copy of being exported at last, so Shu Ru original copy is output and is deposited in topmost at first.

On the other hand, when category is exported, be by 1 part 1 part ground output of the order opposite with the original copy input, so, repeat required umber to it.

At this, to video memory of the present invention (DRAM: image-region 28a) and the generating run of two-dimensional address describe.

Before the explanation of carrying out video memory, the common access of DRAM and the difference of high speed page-mode are described earlier.

At first, the inside of diagrammatic illustration DRAM (image-region 28a) constitutes.

Shown in Figure 19 is the configuration example that can preserve the DRAM of 1048576 (address) 16 bit data, and it is made of timing sequencer 1001, row address register 1002, row-address decoder 1003, column address register 1004, column address decoder 1005, memory array 1006, line data register 1007, column data selector switch 1008 and data inputoutput buffer 1009.

MMA[9:0] input specifies which address in 1048576 carried out the address that writing of data read.Being taken into and the sequential of data input and output of control signal RAS.CAS.WE control address.MD[15: 0] data of 16 of input and output.For specifying 1048576 addresses to need 20 (1048576=2 ²⁰) address signal, still, can be by dividing input MMA[9:0 2 times] 10 addresses of specifying 20.

MMA[9: 0], control signal RAS.CAS.WE provides MD[15 by address control circuit 26: 0] be exported to data control circuit 27.

The MMA[9 that row address register 1002 keeps as the row address input: 0], the MMA[9 that column address register 1004 keeps as the column address input: 0].Timing sequencer 1001 is that benchmark produces the sequential that keeps the address with the RAS.CAS signal.Row-address decoder 1003 becomes to be used to specify 1024 (1024=2 of other row to 10 row address decoding ¹⁰).Similarly, column address decoder 1004 becomes to be used to specify 1024 of other row to 10 column address decoding.Memory array 1006 is preserved the section data tool in reality and is become following structure, have 1024 row with 1 1024 row as the row of preserving unit, and 16 1024 row multiply by this 1024 array that is listed as, data bit has 16.

Line of input address at first when reading DRAM utilizes the RAS signal that row address is remained in the row address register 1002.Row address is through the specific row of row address decoder 1003 decodings and selection memory array 1006.Reading with behavior unit of DRAM carried out, and the data of selected row are maintained in the line data register (16 1024 row) 1007.Then, the input column address utilizes the CAS signal that column address is remained in the column address register 1004.Column address is deciphered by column address decoder 1005, and utilizes the data of selecting specific row in 1024 data that are listed as of column data selector switch 1008 from remain on line data register 1007 according to decode results.The data of being selected by column data selector switch 1008 are output to outside (data control circuit 27) by data inputoutput buffer 1009.At last, original row on the writing data into memory array 1006 of 1 row of line data register 1007 and end read operation.Why carrying out write-back to original row, is because when reading 1 row to line data register 1007 from memory array 1006, the data on the memory array 1006 of carrying out reading are damaged.

Writing of DRAM is the line of input address, utilizes the RAS signal that row address is remained on the row address register 1002.Row address is by the specific row of row-address decoder 1003 decodings and selection memory array 1006.Reading by the row unit of DRAM undertaken, and the data of selected row are maintained on the line data register (16 of 1024 row) 1007.Utilize the CAS signal that column address is remained in the column address register 1004.Column address becomes the data rewriting of 1 row in the data that remain on the row of 1024 on the line data register 1007 from the data of data inputoutput buffer 1008 inputs according to decoded result through column address decoder 1005 decodings.That is the data of the specified row on the specified row are changed by the data on the line data register 1007 and are write.Then, on the original row on the writing data into memory array 1006 of 1 row of line data register 1007, finish write operation.

The burst accesses of DRAM is on giving row address and 1 capable data being read into basis in the line data register 1007, to reading with the data of delegation, can just can carry out inferior arbitrarily reading by only providing column address, in addition, if to writing on the same row address, also can by only give column address, according to line data register 1007 change and when the change with delegation all is over write-back memory array 1006, thereby realize the burst accesses of DRAM.

What (a)～(d) of Figure 20 was represented is the common sequential of reading.

Shown in Figure 20 (a)～(d), the address is by setting row address at the negative edge of RAS, sets the setting in sequence of column address at the negative edge of CAS, and behind official hour output data.

What (a)～(d) of Figure 21 was represented is the sequential of reading of high speed page-mode.

Shown in Figure 21 (a)～(d), there is being the train of impulses of giving 1 row address and a plurality of (being 4 addresses among the figure) row address to read the round-robin sequential shown in 1 time the access.Read sequential relatively with common, get final product because need not all to give row address at every turn, so, can carry out the data input and output at high speed.

Main points of the present invention are exactly when use can be carried out the DRAM composing images storer of aforesaid burst accesses, constitute the piece of two dimension by the data of utilizing same row address, in same, can carry out burst accesses, provide no matter the video memory that the access direction how can both zero access to the integral body of transverse direction, longitudinal direction or piece.

Below, utilize Figure 22, Figure 23 to illustrate to constitute the pixel of original image and constitute the corresponding relation of the storage unit of DRAM (image-region 28a).

Shown in Figure 22 is the pixel formation of original image.

Pixel constitutes

This routine original image is made of horizontal 256 pixels, vertical 256 pixels.

Be the position of remarked pixel, establishing is the x coordinate from left to right, is the y coordinate from top to bottom, and (x is y) as the point of representing the location of pixels on the original copy with P.In this example, the pixel of establishing the upper left corner is P (1,1), and the pixel in the upper right corner is P (256,1), and the pixel in the lower left corner is P (1,256), and the pixel in the lower right corner is P (256,256).

The formation of piece

If the zone that constitutes with horizontal 4 pixels, vertical 4 pixels is 1 piece, and original image is divided into horizontal 64, vertical 64.

Be the position of expression piece, establishing is the x coordinate from left to right, is the y coordinate from top to bottom, and (x is y) as the piece of representing the location of pixels on the original copy with B.In this example, the piece of establishing the upper left corner is B (1,1), and the piece in the upper right corner is B (64,1), and the piece in the lower left corner is B (1,64), and the piece in the lower right corner is B (64,64).

Shown in Figure 23 is the formation of the storage unit of DRAM.

This routine DRAM is made of the storage unit of 1024 of column directions, 1024 of line directions.Storage unit is to preserve when reading the least unit of appointment individually.

Be the position of expression storage unit, establishing is column direction from left to right, from top to bottom is line direction, with M (row, OK) position of expression storage unit.In this example, the storage unit of establishing the upper left corner is M (1,1), and the storage unit in the upper right corner is M (1024,1), and the storage unit in the lower left corner is M (1,1024), and the storage unit in the lower right corner is M (1024,1024).

Access to the storage unit of DRAM is to come particular storage is carried out access by setting the address by the order of row address, column address.

If set row address on DRAM, (M (1～1024, the content of storage unit OK)) is sent in the line data register 1007 in the DRAM all row in the then specified row together.Therefore, to the access of the unit of delegation as long as once be sent to line data register 1007, just can select the data of row address register 1007 by a specify columns address, so, can shorten processing time of unnecessary row address.

The location of pixels of original image, the relation of piece position and storage unit position

Among the figure, P (x, the y) location of pixels of the original image of expression Figure 22, B (x, y) expression piece position.

Original image as continuous storage unit, mates the piece that is made of 16 pixels by the order of column address direction, row address direction is corresponding.

At this moment, the pixel that constitutes piece need be mated by certain corresponding same row address.By such way, can be only specify beginning most to do a row address, only specify then the column address of respective pixel just can carry out to the consecutive access of the same corresponding pixel of pixel.In addition, even if other piece, so long as same row address equally also can carry out access by a specify columns address.

In this example, because corresponding 1 16 pixel, the number of memory cells of 1 row is 1024 (integral multiples of 1 pixel count), so, can not have shortcoming and do not have residue ground allocation block.

Image to DRAM writes, reads example

Image input by scanister 13

If read the original image of Figure 22, then can read in the view data of pixel in turn by the order of x direction, y direction with scanister 13.

If represent with location of pixels, then be at first to begin to read in P (1,1), sequentially read in P (from 2 to 256,1) by upper left to the bottom right then, P (from 1 to 256,2) ... Deng, read in P (256,256) at last.

The view data of the pixel of reading in is sequentially sent to DRAM, and is kept on the corresponding storage unit.

When write storage unit, the storage unit of same row address is being write continuously fashionable, can only do row address and specify, only when row address is different, just do row address once more and specify.

In this example, be simplified illustration, carry out row address when establishing the different piece of every beginning access and set.

The row address of [writing of the 1st row (begin column)] B (1,1) is set

The column address of P (1,1) is set, and data write (starting pixel)

The column address of P (2,1) is set, and data write

The column address of P (3,1) is set, and data write

The column address of P (4,1) is set, and data write the row address of B (2,1) and set

The column address of P (5,1) is set, and data write

The column address of P (6,1) is set, and data write

The column address of P (7,1) is set, and data write

The column address of P (8,1) is set, and data write

.

.

.B the row address of (64,1) is set

The column address of P (253,1) is set, and data write

The column address of P (254,1) is set, and data write

The column address of P (255,1) is set, and data write

The column address of P (256,1) is set, and data write the row address of [writing of the 2nd row] B (1,1) and set

The column address of P (1,2) is set, and data write

The column address of P (2,2) is set, and data write

The column address of P (3,2) is set, and data write

The column address of P (4,2) is set, and data write the row address of B (2,1) and set

The column address of P (5,2) is set, and data write

The column address of P (6,2) is set, and data write

The column address of P (7,2) is set, and data write

The column address of P (8,2) is set, and data write

.

.

.B the row address of (64,1) is set

The column address of P (253,2) is set, and data write

The column address of P (254,2) is set, and data write

The column address of P (255,2) is set, and data write

The column address of P (256,2) is set, and data write

.

.

.[the 256th row (final row) writes] row address of B (1,64) sets

The column address of P (1,256) is set, and data write

The column address of P (2,256) is set, and data write

The column address of P (3,256) is set, and data write

The column address of P (4,256) is set, and data write the row address of B (2,64) and set

The column address of P (5,256) is set, and data write

The column address of P (6,256) is set, and data write

The column address of P (7,256) is set, and data write

The column address of P (8,256) is set, and data write

.

.

.B the row address of (64,64) is set

The column address of P (253,256) is set, and data write

The column address of P (254,256) is set, and data write

The column address of P (255,256) is set, and data write

The column address of P (256,256) is set, and data write (final pixel) image output (single bundle mode) to duplicator 15

Non-rotating

From the storage unit of the view data of respective pixel, read in turn by scanister 13 by the order of the x direction of Figure 22 original copy, y direction and to be written to the image of DRAM and to export to duplicator 15.

If the location of pixels with original copy is represented, then is at first to begin to read P (1,1), in turn from upper left to the bottom right read P (from 2 to 256,1), P (from 1 to 256,2) ... Deng, read P (256,256) at last.

Duplicator 15 is read and exported to the corresponding view data that will read the storage unit of pixel from DRAM in turn.

When the reading of storage unit, in the reading continuously of the storage unit of same relatively row address, can only do a row address and specify, only when row address is different, just do row address once more and specify.

In this example, be simplified illustration, establish and when the different piece of beginning access, all carry out row address and set.

[reading of the 1st row (begin column)]

The row address of B (1,1) is set

The column address of P (1,1) is set, and data are read (starting pixel)

The column address of P (2,1) is set, and data are read

The column address of P (3,1) is set, and data are read

The column address of P (4,1) is set, and data are read

The row address of B (2,1) is set

The column address of P (5,1) is set, and data are read

The column address of P (6,1) is set, and data are read

The column address of P (7,1) is set, and data are read

The column address of P (8,1) is set, and data are read

.

.

.

The row address of B (64,1) is set

The column address of P (253,1) is set, and data are read

The column address of P (254,1) is set, and data are read

The column address of P (255,1) is set, and data are read

The column address of P (256,1) is set, and data are read the row address of [reading of the 2nd row] B (1,1) and set

The column address of P (1,2) is set, and data are read

The column address of P (2,2) is set, and data are read

The column address of P (3,2) is set, and data are read

The column address of P (4,2) is set, and data are read the row address of B (2,1) and set

The column address of P (5,2) is set, and data are read

The column address of P (6,2) is set, and data are read

The column address of P (7,2) is set, and data are read

The column address of P (8,2) is set, and data are read

.

.

.B the row address of (64,1) is set

The column address of P (253,2) is set, and data are read

The column address of P (254,2) is set, and data are read

The column address of P (255,2) is set, and data are read

The column address of P (256,2) is set, and data are read

.

.

.[the 256th row (final row) reads] row address of B (1,64) sets

The column address of P (1,256) is set, and data are read

The column address of P (2,256) is set, and data are read

The column address of P (3,256) is set, and data are read

The column address of P (4,256) is set, and data are read the row address of B (2,64) and set

The column address of P (5,256) is set, and data are read

The column address of P (6,256) is set, and data are read

The column address of P (7,256) is set, and data are read

The column address of P (8,256) is set, and data are read

.

.

.B the row address of (64,64) is set

The column address of P (253,256) is set, and data are read

The column address of P (254,256) is set, and data are read

The column address of P (255,256) is set, and data are read

The column address of P (256,256) is set, and data are read (final pixel)

Right 90 degree rotations

By from the storage unit of the view data of respective pixel, reading the image that is written to DRAM by scanister 13 in turn, original copy dextrorotation is turn 90 degrees and exports to duplicator 15 by the y opposite direction of Figure 22 original copy, the order of x direction.

If the location of pixels with original copy is represented, then is at first to begin to read P (1,256), in turn by the lower-left to read upper rightly P (1, from 255 to 1), P (2, from 256 to 1) ... Deng, read P (256,1) at last.

Duplicator 15 is read and be exported to the corresponding view data that will read the storage unit of pixel sequentially from DRAM.

When the reading of storage unit, in the storage unit of same row address is read continuously, can only do a row address and specify, only when row address is different, just do row address once more and specify.

In this example, be simplified illustration, establish and when the different piece of beginning access, all carry out row address and set.

[reading of the 1st row (begin column)]

The row address of B (1,64) is set

The column address of P (1,256) is set, and data are read (starting pixel)

The column address of P (1,255) is set, and data are read

The column address of P (1,254) is set, and data are read

The column address of P (1,253) is set, and data are read the row address of B (1,63) and set

The column address of P (1,252) is set, and data are read

The column address of P (1,251) is set, and data are read

The column address of P (1,250) is set, and data are read

The column address of P (1,249) is set, and data are read

.

.

.B the row address of (1,1) is set

The column address of P (1,4) is set, and data are read

The column address of P (1,3) is set, and data are read

The column address of P (1,2) is set, and data are read

The column address of P (1,1) is set, and data are read the row address of [reading of the 2nd row] B (1,64) and set

The column address of P (2,256) is set, and data are read

The column address of P (2,255) is set, and data are read

The column address of P (2,254) is set, and data are read

The column address of P (2,253) is set, and data are read the row address of B (1,63) and set

The column address of P (2,252) is set, and data are read

The column address of P (2,251) is set, and data are read

The column address of P (2,250) is set, and data are read

The column address of P (2,249) is set, and data are read

.

.

.B the row address of (1,1) is set

The column address of P (2,4) is set, and data are read

The column address of P (2,3) is set, and data are read

The column address of P (2,2) is set, and data are read

The column address of P (2,1) is set, and data are read

.

.

.[the 256th row (final row) reads] row address of B (64,64) sets

The column address of P (256,256) is set, and data are read

The column address of P (226,255) is set, and data are read

The column address of P (256,254) is set, and data are read

The column address of P (256,253) is set, and data are read the row address of B (64,63) and set

The column address of P (256,252) is set, and data are read

The column address of P (256,251) is set, and data are read

The column address of P (256,250) is set, and data are read

The column address of P (256,249) is set, and data are read

.

.

.B the row address of (64,1) is set

The column address of P (256,4) is set, and data are read

The column address of P (256,3) is set, and data are read

The column address of P (256,2) is set, and data are read

The column address of P (256,1) is set, and data are read (final pixel)

Right 180 degree rotations

By by the x of Figure 22 original copy in the other direction, the reciprocal order of y reads the image that is written to DRAM by scanister 13 in turn from the storage unit of the view data of respective pixel, original copy dextrorotation turnback and export to duplicator 15.

If the location of pixels with original copy is represented, then is at first to begin to read P (256,256), in turn by the bottom right to read upper leftly P (from 255 to 1,256), P (from 256 to 1,255) ... Deng, read P (1,1) at last.

Duplicator 15 is read and be exported to the corresponding view data that will read the storage unit of pixel sequentially from DRAM.

When the reading of storage unit, in the reading continuously of the storage unit of same relatively row address, can only do a row address and specify, only when row address is different, just do row address once more and specify.

In this example, be simplified illustration, establish and when the different piece of beginning access, all carry out row address and set.

The row address of [reading of the 1st row (begin column)] B (64,64) is set

The column address of P (256,256) is set, and data are read (starting pixel)

The column address of P (255,256) is set, and data are read

The column address of P (254,256) is set, and data are read

The column address of P (253,256) is set, and data are read the row address of B (63,64) and set

The column address of P (252,256) is set, and data are read

The column address of P (251,256) is set, and data are read

The column address of P (250,256) is set, and data are read

The column address of P (249,256) is set, and data are read

.

.

.B the row address of (1,64) is set

The column address of P (4,256) is set, and data are read

The column address of P (3,256) is set, and data are read

The column address of P (2,256) is set, and data are read

The column address of P (1,256) is set, and data are read the row address of [reading of the 2nd row] B (64,64) and set

The column address of P (256,255) is set, and data are read

The column address of P (255,255) is set, and data are read

The column address of P (254,255) is set, and data are read

The column address of P (253,255) is set, and data are read the row address of B (63,64) and set

The column address of P (252,255) is set, and data are read

The column address of P (251,255) is set, and data are read

The column address of P (250,255) is set, and data are read

The column address of P (249,255) is set, and data are read

.

.

.B the row address of (1,64) is set

The column address of P (4,255) is set, and data are read

The column address of P (3,255) is set, and data are read

The column address of P (2,255) is set, and data are read

The column address of P (1,255) is set, and data are read the row address of [reading of the 256th row (final row)] B (64,1) and set

The column address of P (256,1) is set, and data are read

The column address of P (255,1) is set, and data are read

The column address of P (254,1) is set, and data are read

The column address of P (253,1) is set, and data are read the row address of B (63,1) and set

The column address of P (252,1) is set, and data are read

The column address of P (251,1) is set, and data are read

The column address of P (250,1) is set, and data are read

The column address of P (249,1) is set, and data are read

.

.

.B the row address of (1,1) is set

The column address of P (4,1) is set, and data are read

The column address of P (3,1) is set, and data are read

The column address of P (2,1) is set, and data are read

The column address of P (1,1) is set, and data are read (final pixel)

Right 270 degree rotations

Read the image that is written to DRAM by scanister 13 by the reciprocal order of y direction, x in turn from the storage unit of the view data of respective pixel, original copy right rotation 270 degree and export to duplicator 15 by Figure 22 original copy.

If the location of pixels with original copy is represented, then is at first to begin to read P (256,1), in turn by upper right read to left down P (256, from 2 to 256), P (2 55, from 1 to 256) ... Deng, read P (1,256) at last.

Duplicator 15 is read and be exported to the corresponding view data that will read the storage unit of pixel sequentially from DRAM.

When the reading of storage unit, in the reading continuously of the storage unit of same relatively row address, can only do a row address and specify, only when row address is different, just do row address once more and specify.

In this example, be simplified illustration, establish and when the different piece of beginning access, all carry out row address and set.

[reading of the 1st row (begin column)]

The row address of B (64,1) is set

The column address of P (256,1) is set, and data are read (starting pixel)

The column address of P (256,2) is set, and data are read

The column address of P (256,3) is set, and data are read

The column address of P (256,4) is set, and data are read

The row address of B (64,2) is set

The column address of P (256,5) is set, and data are read

The column address of P (256,6) is set, and data are read

The column address of P (256,7) is set, and data are read

The column address of P (256,8) is set, and data are read

.

.

.B the row address of (64,64) is set

The column address of P (256,253) is set, and data are read

The column address of P (256,254) is set, and data are read

The column address of P (256,255) is set, and data are read

The column address of P (256,256) is set, and data are read the row address of [reading of the 2nd row] B (64,1) and set

The column address of P (255,1) is set, and data are read

The column address of P (255,2) is set, and data are read

The column address of P (255,3) is set, and data are read

The column address of P (255,4) is set, and data are read the row address of B (64,2) and set

The column address of P (255,5) is set, and data are read

The column address of P (255,6) is set, and data are read

The column address of P (255,7) is set, and data are read

The column address of P (255,8) is set, and data are read

.

.

.B the row address of (64,64) is set

The column address of P (255,253) is set, and data are read

The column address of P (255,254) is set, and data are read

The column address of P (255,255) is set, and data are read

The column address of P (255,256) is set, and data are read

.

.

.[the 256th row (final row) reads] row address of B (1,1) sets

The column address of P (1,1) is set, and data are read

The column address of P (1,2) is set, and data are read

The column address of P (1,3) is set, and data are read

The column address of P (1,4) is set, and data are read the row address of B (1,2) and set

The column address of P (1,5) is set, and data are read

The column address of P (1,6) is set, and data are read

The column address of P (1,7) is set, and data are read

The column address of P (1,8) is set, and data are read

.

.

.B the row address of (1,64) is set

The column address of P (1,253) is set, and data are read

The column address of P (1,254) is set, and data are read

The column address of P (1,255) is set, and data are read

The column address of P (1,256) is set, and data are read (final pixel)

Image output (multi beam mode: 4 bundles) to duplicator 15

Non-rotating

Read the image that is written to DRAM by scanister 13 by order in turn from the storage unit of the view data of corresponding 4 row pixels, and export to duplicator 15, simultaneously to 4 line printings of advancing by the x direction of Figure 22 original copy, y direction.

If the location of pixels with original copy is represented, then is at first to begin to read P (1, from 1～4), in turn by upper left to the bottom right read P (2) from 1～4 ..., P (256) etc. from 1～4, read P (256) at last from 253～256.

Duplicator 15 is read and be exported to the corresponding view data that will read the storage unit of pixel sequentially from DRAM.

When the reading of storage unit, in the storage unit of same row address is read continuously, can only do a row address and specify, only when row address is different, just do row address once more and specify.

In this example, be simplified illustration, establish and when the different piece of beginning access, all carry out row address and set.

[reading of the 1st～4 row (begin column)]

The row address of B (1,1) is set

The column address of P (1,1～4) is set, and data are read (starting pixel, 4 row)

The column address of P (2,1～4) is set, and data are read

The column address of P (3,1～4) is set, and data are read

The column address of P (4,1～4) is set, and data are read

The row address of B (2,1) is set

The column address of P (5,1～4) is set, and data are read

The column address of P (6,1～4) is set, and data are read

The column address of P (7,1～4) is set, and data are read

The column address of P (8,1～4) is set, and data are read

.

.

.

The row address of B (64,1) is set

The column address of P (253,1～4) is set, and data are read

The column address of P (254,1～4) is set, and data are read

The column address of P (255,1～4) is set, and data are read

The column address of P (256,1～4) is set, and data are read

[reading of the 5th～8 row]

The row address of B (1,2) is set

The column address of P (1,5～8) is set, and data are read

The column address of P (2,5～8) is set, and data are read

The column address of P (3,5～8) is set, and data are read

The column address of P (4,5～8) is set, and data are read the row address of B (2,2) and set

The column address of P (5,5～8) is set, and data are read

The column address of P (6,5～8) is set, and data are read

The column address of P (7,5～8) is set, and data are read

The column address of P (8,5～8) is set, and data are read

.

.

.B the row address of (64,2) is set

The column address of P (253,5～8) is set, and data are read

The column address of P (254,5～8) is set, and data are read

The column address of P (255,5～8) is set, and data are read

The column address of P (256,5～8) is set, and data are read

.

.

.[the 25 3～256 row (final row) reads] row address of B (1,64) sets

The column address of P (1,253～256) is set, and data are read

The column address of P (2,253～256) is set, and data are read

The column address of P (3,253～256) is set, and data are read

The column address of P (4,253～256) is set, and data are read the row address of B (2,64) and set

The column address of P (5,253～256) is set, and data are read

The column address of P (6,253～256) is set, and data are read

The column address of P (7,253～256) is set, and data are read

The column address of P (8,253～256) is set, and data are read

.

.

.B the row address of (64,64) is set

The column address of P (253,253～256) is set, and data are read

The column address of P (254,253～256) is set, and data are read

The column address of P (255,253～256) is set, and data are read

The column address of P (256,253～256) is set, and data are read (final pixel, 4 row)

Right 90 degree rotations

By reading the image that is written to DRAM by scanister 13 in turn from the storage unit of the view data of corresponding 4 row pixels by the y opposite direction of Figure 22 original copy, the order of x direction, and export to duplicator 15, print simultaneously at every turn 4 row to right rotation the images of 90 degree.

If the location of pixels with original copy represents, then be at first to begin to read (4 row) P (1～4,256), in turn by the lower-left to read upper rightly P (1～4,255) ..., P (1～4,1) etc., read P (256～253,1) at last.

Correspondence is read the view data of the storage unit of pixel and is sequentially read and be exported to duplicator 15 from DRAM.

When the reading of storage unit, in the reading continuously of the storage unit of same relatively row address, can only do a row address and specify, only when row address is different, just do row address once more and specify.

In this example, be simplified illustration, establish and when the different piece of beginning access, all carry out row address and set.

[reading of the 1st～4 row (begin column)]

The row address of B (1,64) is set

The column address of P (1～4,256) is set, and data are read (starting pixel, 4 row)

The column address of P (1～4,255) is set, and data are read

The column address of P (1～4,254) is set, and data are read

The column address of P (1～4,253) is set, and data are read

The row address of B (1,63) is set

The column address of P (1～4,252) is set, and data are read

The column address of P (1～4,251) is set, and data are read

The column address of P (1～4,250) is set, and data are read

The column address of P (1～4,249) is set, and data are read

.

.

.B the row address of (1,1) is set

The column address of P (1～4,4) is set, and data are read

The column address of P (1～4,3) is set, and data are read

The column address of P (1～4,2) is set, and data are read

The column address of P (1～4,1) is set, and data are read the row address of [reading of the 5th～8 row] B (2,64) and set

The column address of P (5～8,256) is set, and data are read

The column address of P (5～8,255) is set, and data are read

The column address of P (5～8,254) is set, and data are read

The column address of P (5～8,253) is set, and data are read the row address of B (2,63) and set

The column address of P (5～8,252) is set, and data are read

The column address of P (5～8,251) is set, and data are read

The column address of P (5～8,250) is set, and data are read

The column address of P (5～8,249) is set, and data are read

.

.

.B the row address of (2,1) is set

The column address of P (5～8,4) is set, and data are read

The column address of P (5～8,3) is set, and data are read

The column address of P (5～8,2) is set, and data are read

The column address of P (5～8,1) is set, and data are read

.

.

.

[reading of the 253rd～256 row (final row)]

The row address of B (64,64) is set

The column address of P (253～256,256) is set, and data are read

The column address of P (253～226,255) is set, and data are read

The column address of P (253～256,254) is set, and data are read

The column address of P (253～256,253) is set, and data are read

The row address of B (64,63) is set

The column address of P (253～256,252) is set, and data are read

The column address of P (253～256,251) is set, and data are read

The column address of P (253～256,250) is set, and data are read

The column address of P (253～256,249) is set, and data are read

.

.

.

The row address of B (64,1) is set

The column address of P (253～256,4) is set, and data are read

The column address of P (253～256,3) is set, and data are read

The column address of P (253～256,2) is set, and data are read

The column address of P (253～256,1) is set, and data are read (final pixel, 4 row)

Right 180 degree rotations

By by the x of Figure 22 original copy in the other direction, the reciprocal order of y reads the image that is written to DRAM by scanister 13 in turn from the storage unit of the view data of corresponding 4 row pixels, the images of 180 degree of at every turn having printed 4 row right rotations simultaneously.

If the location of pixels with original copy represents, then be at first to begin to read (4 row) P (256,256～253), in turn from the bottom right to read upper leftly P (255,256～253) ..., P (1,256～253) etc., read P (1,4～1) at last.

Correspondence is read the view data of the storage unit of pixel and is sequentially read and be exported to duplicator 15 from DRAM.

When the reading of storage unit, in the storage unit of same row address is read continuously, can only do a row address and specify, only when row address is different, just do row address once more and specify.

In this example, be simplified illustration, establish and when the different piece of beginning access, all carry out row address and set.The row address of [reading of the 1st～4 row (begin column)] B (64,64) is set

The column address of P (256,256～253) is set, and data are read (starting pixel, 4 row)

The column address of P (255,256～253) is set, and data are read

The column address of P (254,256～253) is set, and data are read

The column address of P (253,256～253) is set, and data are read the row address of B (63,64) and set

The column address of P (252,256～253) is set, and data are read

The column address of P (251,256～253) is set, and data are read

The column address of P (250,256～253) is set, and data are read

The column address of P (249,256～253) is set, and data are read

.

.

.B the row address of (1,64) is set

The column address of P (4,256～253) is set, and data are read

The column address of P (3,256～253) is set, and data are read

The column address of P (2,256～253) is set, and data are read

The column address of P (1,256～253) is set, and data are read the row address of [reading of the 5th～8 row] B (64,63) and set

The column address of P (256,252～248) is set, and data are read

The column address of P (255,252～248) is set, and data are read

The column address of P (254,252～248) is set, and data are read

The column address of P (253,252～248) is set, and data are read the row address of B (63,63) and set

The column address of P (252,252～248) is set, and data are read

The column address of P (251,252～248) is set, and data are read

The column address of P (250,252～248) is set, and data are read

The column address of P (249,252～248) is set, and data are read

.

.

.B the row address of (1,64) is set

The column address of P (4,252～248) is set, and data are read

The column address of P (3,252～248) is set, and data are read

The column address of P (2,252～248) is set, and data are read

The column address of P (1,252～248) is set, and data are read

.

.

.[the 253rd～256 row (final row) reads] row address of B (64,1) sets

The column address of P (256,4～1) is set, and data are read

The column address of P (255,4～1) is set, and data are read

The column address of P (254,4～1) is set, and data are read

The column address of P (253,4～1) is set, and data are read the row address of B (63,1) and set

The column address of P (252,4～1) is set, and data are read

The column address of P (251,4～1) is set, and data are read

The column address of P (250,4～1) is set, and data are read

The column address of P (249,4～1) is set, and data are read

.

.

.B the row address of (1,1) is set

The column address of P (4,4～1) is set, and data are read

The column address of P (3,4～1) is set, and data are read

The column address of P (2,4～1) is set, and data are read

The column address of P (1,4～1) is set, and data are read (final pixel, 4 row)

Right 270 degree rotations

By reading the image that is written to DRAM by scanister 13 in turn from the storage unit of the view data of corresponding 4 row pixels by the reciprocal order of y direction, x of Figure 22 original copy, the images of 270 degree of at every turn having printed 4 row right rotations simultaneously.

If the location of pixels with original copy represents, then be at first to begin to read (4 row) P (256～253,1), in turn by upper right read to left down P (256～253,2) ..., P (256～253,256) etc., read P (4～1,256) at last.

Duplicator 15 is read and be exported to the corresponding view data that will read the storage unit of pixel sequentially from DRAM.

When the reading of storage unit, in the storage unit of same row address is read continuously, can only do a row address and specify, only when row address is different, just do row address once more and specify.

In this example, be simplified illustration, establish and when the different piece of beginning access, all carry out row address and set.

[reading of the 1st～4 row (begin column)]

The row address of B (64,1) is set

The column address of P (256～253,1) is set, and data are read (starting pixel, 4 row)

The column address of P (256～253,2) is set, and data are read

The column address of P (256～253,3) is set, and data are read

The column address of P (256～253,4) is set, and data are read

The row address of B (64,2) is set

The column address of P (256～253,5) is set, and data are read

The column address of P (256～253,6) is set, and data are read

The column address of P (256～253,7) is set, and data are read

The column address of P (256～253,8) is set, and data are read

.

.

.

The row address of B (64,64) is set

The column address of P (256～253,253) is set, and data are read

The column address of P (256～253,254) is set, and data are read

The column address of P (256～253,255) is set, and data are read

The column address of P (256～253,256) is set, and data are read the row address of [reading of the 5th～8 row] B (63,1) and set

The column address of P (252～248,1) is set, and data are read

The column address of P (252～248,2) is set, and data are read

The column address of P (252～248,3) is set, and data are read

The column address of P (252～248,4) is set, and data are read the row address of B (63,2) and set

The column address of P (252～248,5) is set, and data are read

The column address of P (252～248,6) is set, and data are read

The column address of P (252～248,7) is set, and data are read

The column address of P (252～248,8) is set, and data are read

.

.

.B the row address of (63,64) is set

The column address of P (252～248,253) is set, and data are read

The column address of P (252～248,254) is set, and data are read

The column address of P (252～248,255) is set, and data are read

The column address of P (252～248,256) is set, and data are read

.

.

.[the 253rd～256 row (final row) reads] row address of B (1,1) sets

The column address of P (4～1,1) is set, and data are read

The column address of P (4～1,2) is set, and data are read

The column address of P (4～1,3) is set, and data are read

The column address of P (4～1,4) is set, and data are read

The row address of B (1,2) is set

The column address of P (4～1,5) is set, and data are read

The column address of P (4～1,6) is set, and data are read

The column address of P (4～1,7) is set, and data are read

The column address of P (4～1,8) is set, and data are read

.

.

.

The row address of B (1,64) is set

The column address of P (4～1,253) is set, and data are read

The column address of P (4～1,254) is set, and data are read

The column address of P (4～1,255) is set, and data are read

The column address of P (4～1,256) is set, and data are read (final pixel, 4 row)

Below, to the image construction in the above-mentioned explanation being generalized to the present invention's that n piece * m piece constitutes video memory (DRAM: image-region 28a) describe.

Shown in Figure 24 is the formation of the video memory of two dimension.

In this example, video memory uses the high speed page-mode of DRAM, not that row address and column address are all set in access each time, thereby but omit the burst accesses that the setting cycle of column address is realized the high speed access by only set column address for data with same row address.

Video memory amounts to (nm-1) individual piece 3002 and constitutes by horizontal n, vertical m.

Piece then is made of the word 3001 as storage access unit.

In common access (image that is read by scanister 13 being sent to the situation of video memory etc.), from upper left word, main scanning direction from left to right, sub scanning direction access video memory sequentially line by line from top to bottom.

Shown in Figure 25 is the configuration example of the word in the piece.In this embodiment, by 4 words on 4 words, the line direction on the column direction totally 16 words constitute a piece.Offset address in the numeral piece.Therefore, the storage address of specific word for, in the value on each piece address foremost, after adding piece bias internal address.For example, if the left comer of establishing in the upper left hand block is a storage address 0, just then right adjacent word is a storage address 1, the lower right corner is a storage address 15 in the piece, and the upper left corner of its right adjacent piece is storage address 16.

Also have, the data in same must have the same row address, and the expression number of words of column address is the integral multiple of 1 number of words.In the DRAM of Figure 19 example, column address can be shown with 1024 word tables, is 16 o'clock one number of words, can divide exactly the number of words of representing of row with the number of words that constitutes 1.So the number of words in the piece must be same column address.

Therefore, if the consecutive access in same then just can at high speed any word carry out access as long as once set 1 row address by only setting column address.

In the common access of Figure 24, the access of column direction generates the address of the piece left end of the row that will visit as IP address, carried out respectively with respect to this column address+0 ,+1 ,+2 ,+value after 3 sets the DRAM address as column address, carries out the consecutive access of 4 words.

After this, IP address is moved on the right adjacent left end address carry out same consecutive access.The number of words MD that adds lastblock on IP address that moves through of this IP address carries out.

Finish access if arrive right-hand member, then IP address is moved to the piece left end of next line.When the IP address of next line moved, the amount of movement of its address was different because of the situation that moves to the situation on the same row and move on the row of different masses, is respectively SD1, SD2.

The relation of the address for piece position and piece bias internal and DRAM shown in Figure 26 (row address is the situation of low level for high-order, column address).

Piece is dispensed on continuous storage address left to bottom right.In addition, also be assigned with continuous address in same according to the piece bias internal.

Therefore, above-mentioned MD is that skew 0 by piece 0 is to the displacement the skew 0 of piece 1, so the number of words in the piece equates.If the number of words of establishing 1 is 16 words, then MD=16.

Because SD1 is by the skew 0 of piece (n-1) displacement to the skew 4 of piece 0, thus SD1=-MD * (n-1)+4.Here, can think-MD * (n-1) be the piece of skew between 0 displacement ,+the 4th, the displacement from same skew 0 to skew 4.

Because SD2 is by the skew 12 of piece (n-1) displacement to the skew 0 of piece n, so SD2=MD-12.Here, can think that MD is the displacement, the-the 12nd from piece (n-1) to piece n, displacement from the skew 12 of piece n to skew 0.

Below, with reference to flowchart text shown in Figure 27 above-mentioned from upper left storage address calculated example when the bottom right is sequentially carried out the common access of access line by line.

MA represents continuous storage address.The figure place that is equivalent to the column address of storage address is dispensed on the low level position of storage address, and the high-order position of storage address is distributed by row address.In addition, the part that surpasses the figure place of row address in the high address is used for the selection to a plurality of memory devices.

The piece position of SBLOCK vice direction of scanning.

LINE represents the line position in the piece.

MBLOCK represents the piece position of main scanning direction.

Line number in B (being 4 in this example) the expression piece.

Usually under the situation of access main scanning direction for from left to right, sub scanning direction is for from top to bottom.

Usually during access, MA (storage address) expression is used to carry out the address of reading the capable left end word of reading of piece of burst accesses.It is that starting point is set row address that the high speed page-mode of DRAM is read with this address, and is accessed in continuously and has added 0,1,2,3 column address on the represented column address of MA.

Read row if main scanning direction arrives final piece (MBLOCK=N) and advance to next row, main sweep piece position turns back to left end (MBLOCK ← O).

If reading row arrives the lower end (LINE=B) in the piece then read a piece piece (SBLOCK ← SBLOCK+1) that advances on sub scanning direction.

(SBLOCK=M) then the reading of all pieces of finishing one page if reading of the final row of bottom right piece is over.

Below, the rotation of image read describe.For image rotating, need once launch one page image on the video memory and on sense of rotation, read.

Shown in Figure 28 is access sequence when the image right side is turn 90 degrees.

As shown in figure 28, by from the word of lower-left to upper right word, promptly main scanning direction from the bottom to top, sub scanning direction calls over the video memory image rotating from left to right.

Beginning is that the skew 12 of piece (the m-1) * n with left comer is that IP address is set row address, on the column address of IP address, add respectively+0 ,-4 ,-8 ,-12 value is set it as column address, and 4 interior words of consecutive access piece.

Then, IP address is moved on the address of lower-left of lastblock similarly carry out consecutive access.

Finish access if arrive the upper end, then IP address is moved to the piece lower end of next row.The amount of movement of its address is different with the situation about listing that moves to different masses because of moving to same situation about listing when the IP address of next one row moves, and is respectively SD1, SD2.

Therefore, because above-mentioned MD is that skew 12 by lower-left piece (m-1) * n is to the displacement the skew 12 of a last piece (m-2) * n, so the number of words of n piece is equal.If establish the number of words of 1 piece is 16 words, then MD=16 * n.

Because SD1 is by the skew 12 of piece 0 displacement to the skew 13 of piece (m-1) * n, thus SD1=-MD * (m-1)+1.

Here, can think-MD * (m-1) be (m-1) * n from piece 0 to piece displacement ,+the 1st, from same skew 12 to skew 13 displacement.

Because SD2 is by the skew 15 of piece 0 displacement to the skew 12 of piece (m-1) * n+1, thus SD2=-MD * (m-1)+13.Here, can think-MD * (m-1) be piece (the m-1) * n from piece 0 to the lower-left displacement ,+the 13rd, the displacement from the skew 15 of piece (the m-1) * n of lower-left to right adjacent piece (m-1) * n+1 skew 12.

Like this, but by utilizing the piece composing images storer of consecutive access, the access of needed above-below direction also can realize zero access by consecutive access during to the rotation do not accomplished in the past.

Below, the storage address calculated example during with reference to the above-mentioned right side 90 degree rotation accesses of enterprising line access to the right of flowchart text shown in Figure 29 from the lower-left.

MA represents continuous storage address.The figure place that is equivalent to the column address of storage address is dispensed on the low level position of storage address, and row address is distributed in the high-order position of storage address.In addition, the part that surpasses the figure place of row address in the high address is used for the selection to a plurality of memory devices.

The piece position of SBLOCK vice direction of scanning.

LINE represents the line position in the piece.

MBLOCK represents the piece position of main scanning direction.

Columns in A (being 4 in this example) the expression piece.

Under the situation of right 90 degree rotation accesses, that main scanning direction is served as reasons down is supreme, sub scanning direction is for from left to right.

During right 90 degree rotation accesses, MA (storage address) expression is used to carry out the address that the lower end row of reading piece of burst accesses is read the word of row (position of the left and right directions that piece is interior).It is that to read with this address be that starting point is set row address that the high speed page-mode of DRAM is read, and is accessed in continuously and has added 0 ,-4 ,-8 ,-12 column address (be video memory by upwards consecutive access in piece) on the represented column address of MA.

Read row if main scanning direction arrives final piece (MBLOCK=M) and advance to the right one and be listed as, main sweep piece position turns back to lower end (MBLOCK ← 0).

If reading row arrives the left end (COL=A) in the piece then read a piece piece (SBLOCK ← SBLOCK+1) that advances on sub scanning direction.

(SBLOCK=N) then the reading of all pieces of finishing one page if reading of upper right final row is over.

Below, the configuration example of concrete storage address generating unit (being shown in the address generating unit 612 of above-mentioned Figure 10) of above-mentioned common access and rotation access is described.

Shown in Figure 30 is the formation of IP address (start address that the train of impulses transmits) generating unit of storage access.

The IP address generating unit is made of following equipment, promptly comprises: the subscan piece is counted configuration part 3801; Line number (columns) configuration part 3802 in the piece; The main sweep piece is counted configuration part 3803; Sub scanning direction piece counter 3804; Line number (columns) counter 3805 in the piece; Main scanning direction piece counter 3806; Selector switch 3807,3808,3811; Page start address configuration part 3809; Storage address save register 3813; Musical instruments used in a Buddhist or Taoist mass 3810 and OR-gate 3812.Counting will repeat setting numerical value periodically.

The piece number of main scanning direction piece counter 3806 statistics main scanning directions is if arrive final piece (N piece) then produce carry signal EOMB (the final block signal of main sweep).This calculated value is set main sweep piece number by page initializing signal (PINIT).Statistics generates signal (NEXT) by next address and carries out.

Line number or columns in expert counter 3805 statistics block of piece produce carry signal EOL (final row) if arrival is finally gone (A or B).Calculated value is set line number in the piece by page initializing signal (PINIT).Statistics is at input carry signal EOMB, and imported simultaneously when next address generates signal (NEXT) and carried out.Calculating will repeat the setting number periodically.

The piece number of sub scanning direction piece counter 3801 statistics sub scanning directions is if arrive final piece (M piece) then produce carry signal EOSB (the final block signal of subscan).Calculated value is set subscan piece number by page initializing signal (PINIT).Statistics is at input carry signal EOL, and imported simultaneously when next address generates signal (NEXT) and carried out.Calculating will repeat the setting number periodically.

Storage address save register 3813 is preserved present storage address.By adding in turn that on present storage address the incremental computations of next signal address goes out the IP address of each burst accesses.Address register is set start address by page initialization (PINIT).In addition, by switching selector switch 3807,3808 with carry signal, can utilize 3810 pairs of totalizers at every turn movable block additive operation MD on the main scanning direction, to move row additive operation SD1 at every turn, to movable block additive operation SD2 on sub scanning direction at every turn.The additive operation result of totalizer 3810 is switched selector switch 3811 by utilizing next address signal calculated (NEXT), and load signal offered storage address save register 3813 (via OR-gate 3812), upgrade and preserve storage address save register 3813.

Shown in Figure 31 is the configuration example that 1 piece is of a size of the common access video memory of 2 * 2 words, 2 of main sweeps, 2 of subscans.

It shown in Figure 32 (a)～(i) the generation sequential example of the starting point storage address when the enterprising line access of video memory of Figure 31.

Shown in Figure 33 is the formation of DRAM control signal generating unit (above-mentioned DRAM control part 614 shown in Figure 10).

DRAM control signal generating unit is used for generating the clock signal carry out burst accesses DRAM and row address, column address by starting point storage address (MA).

DRAM control signal generating unit is upgraded timer 3902, address offset table 3903, address offset counter 3904, selector switch 3905,3907 and totalizer 3906 by sequential control portion 3901, circulation and is constituted.

Sequential control portion 3901 utilizes memory access control signal to begin store access cycle, and produces the RAS signal of setting DRAM and going up row address, the CAS signal of setting column address, the statistical signal of address offset counter 3904.

Circulation refresh timer 3902 produces DRAM circulation the refreshing commencing signal of some cycles, generates by sequential control portion 3901 to be used to carry out RAS, the CAS signal that the DRAM circulation refreshes.

Address offset table 3903 is set the skew on the column address that is added in the starting point storage address when carrying out burst accesses.The value of address offset table 3903 is set according to the access sequence of the word in the piece.For example, when piece is of a size of 4 * 4 words, in the access of order direction, set 0,1,2,3, in right 90 degree rotations, set 0 ,-4 ,-8 ,-12.

Selector switch 3905 is according to the value of the select progressively address offset table of address offset.

Totalizer 3906 is in the column address levels arithmetic address skew of storage address.

Selector switch 3907 carries out the row address in the storage address and the selection of column address.Selected address is imported into the address port of DRAM, divides row address, column address to set the address of DRAM for twice according to RAS, CAS signal.

Below, the 2nd example of the present invention is described, the utilization example of the zero access of carrying out as the consecutive access by above-mentioned video memory serves as to handle the high speed that high speed that coding and decoding that unit carries out access handles and the corresponding multirow that utilizes laser explosure device can print the duplicator 15 of multirow simultaneously read to describe to the piece with two dimension.

At first illustrate with the piece to be coding, the decoding that unit handles.Be encoded to the example explanation as coded system with JPEG (Joint Photographic Coding Experts Group).

JPEG coding resembles that the gradation data with the monochrome information that pixel was had one by one is that object carries out the photograph image.

In this example, because be with 1 pixel of 8 bit representations, so, can show 256 gray scales (2 ⁸=256) brightness.Among the DCT (Discrete CosineTransform) and inverse transformation thereof that is carried out when JPEG coding, decoding, need be divided into rectangle to integral image is unit with the piece, and is that unit handles with the piece.

Shown in Figure 34 is that 8 of every pixels, processing block are the video memory configuration example of 8 pixels * 8 pixels.In addition, with each storage address of 32 data storage therefore, the piece of 8 pixels * 8 pixels is made of capable 16 words in horizontal 2 words * vertical 8 totally.As described above, because 16 words of same are configured on the same row address in DRAM inside, so, can carry out burst accesses.

(a)～(g) of Figure 35 is depicted as and uses the JPEG coding that utilizes of this video memory to carry out the synoptic diagram of image preservation, transcriber.

At first, the view data of the input media of the reading images of order line by line of coming scanister 13 freely or TV video camera and so on line by line sequentially (situation of Figure 35 is to the bottom right by upper left) write video memory.At this moment, if the storage address that writes in proper order is the same row address of DRAM line by line, then can carries out high speed and write (with reference to Figure 35 (a)) by burst accesses.

Because JPEG coding is that Flame Image Process is become with the piece is unit, so, be that the image on the video memory of input is read by unit with the piece.As this be the feature of this video memory, the storage address that constitutes the word of piece is the formation that resembles the same row address of having of DRAM.Therefore, can read into JPEG code device (with reference to Figure 35 (b)) to the view data of 1 piece in batch at high speed by burst accesses.

Utilize JPEG code device image data amount can be compressed to 1/10th, and be stored in ((d)) in the coded stack with reference to Figure 35 (c).

Select the image stored as required, can read number of times arbitrarily, utilize the JPEG decoding device can reproduce original image ((e)) with reference to Figure 35 (d) by order arbitrarily.

The situation of JPEG decoding and coding is the same to be the unit reproduced image with the piece.As this be the feature of this video memory, the storage address that constitutes the word of piece has the formation that resembles the same row address of having of DRAM.Therefore, can be written to video memory (with reference to Figure 35 (f)) to the view data of 1 piece from the JPEG decoding device at high speed in batch by burst accesses.

The image that reproduces is sequentially read line by line, for example outputs on the equipment series that order is exported line by line such as laser duplicator or CRT monitor.At this moment, if the storage address of reading in proper order has same row address in DRAM line by line, then can carry out high speed and read (with reference to Figure 35 (g)) by burst accesses.

Like this,, make that what can not carry out is that the DRAM burst accesses of unit becomes possibility with the piece over, and the data of carrying out at high speed with video memory are transmitted become possibility by using this video memory.

Secondly, the high speed that the multirow that utilizes laser explosure device 4500 can print the duplicator 15 of multirow is simultaneously read describes.

The laser explosure device 4500 of Figure 36 is by 4 laser instruments 4501,4502,4502,4503,4 Electronic Speculum 4504,4505,4506,4507,4 laser pumping devices 4508,4509,4510,4511,4512,4513,4514,4515,2 half-reflecting half mirrors 4516,4517 of 4 Electronic Speculum driving circuits, polygon mirror 4518, polygonal motor 4519, polygonal motor driver 4520, bundle detecting sensor 4521, bundle detecting sensor output processing circuit 4522 constitutes.To be benchmark make lasing fluorescence according to the data of separately row to the bundle detection signal of detecting sensor 4521 since each laser pumping device 4508,4509,4510,4511.Half-reflecting half mirror synthesizes a plurality of laser beam, and can utilize a polygon mirror 4518 scanning photosensitive drums 4523.Electronic Speculum 4504,4505,4506,4507 is by Electronic Speculum driving circuit 4512,4513,4514,4515 control, is used to carry out exposure position is changed to the adjustment of desired position relation when separately laser beam flying is on photosensitive drums 4523.Shown in Figure 37 is the state that utilizes a plurality of laser beam to expose on photosensitive drums 4523.On photosensitive drums 4523, form image by 4 behavior units by 4 laser beam.At this moment, inching is equally spaced carried out by Electronic Speculum 4504,4505,4506,4507 in laser beam lithography position separately on sub scanning direction.

(a) of Figure 38 is to carry out memory copy (when duplicating many parts by the sequential access line by line in past shown in (b), after the image from scanister 13 once had been taken into video memory, read the video memory output image later on repeatedly) time the state of storage access.

View data from scanister 13 sequentially is read into video memory (with reference to (a) of Figure 38) line by line.

Printing to duplicator 15 is sequentially to read video memory line by line, is sent to the translation circuit (with reference to (b) of Figure 38) that is used to drive 4 row laser again.

Shown in Figure 39 is the formation that the data that will call over line by line are used to drive the translation circuit of 4 row laser.

Because video memory in the past can not carry out between different rows the DRAM burst accesses of (so owing to needing the image of multirow need be on above-below direction continuous data), so, after calling over line by line, need on the basis of the last images that form 4 row of externally high-speed memory the view data between could the zero access different rows.

For preparing the view data of 4 row, the memory read data that calls over line by line is written into line buffer 4601,4602.If got all the 4 row view data ready, then read from word ground of word of row separately.Line buffer 4601,4602 has 2 groups, is storing 4 row line by line in the view data process of order at one group, and another group then has been ready for 4 row the reading of view data.The write operation of line buffer 4601,4602 and read operation are carried out with staggering mutually alternately, can carry out continuous operation.

The data of being read are taken into data buffer 4603, by parallel → serial converted portion 4604 digital data are transformed into 1 serial data and generate each laser pumping device drive signal voluntarily.

That is, in order to prepare to be used for sequentially carrying out line by line 4 view data of going of reading of image, also need prepare the high-speed buffer of 2 group of 4 row in the video memory outside, so, aggrandizement apparatus scale or cost wanted inevitably.

Memory access operations when being to use video memory of the present invention shown in Figure 40.

Totally 16 words that this example is gone by the piece that is used for burst accesses DRAM and horizontal (main scanning direction) 4 words, vertical (line direction) 4 constitute.

By scanister 13 read line by line the order view data by writing (have same row address if face the DRAM address of piece mutually, then can also stride the burst accesses of piece) in the burst accesses piece at high speed.

Video memory read the feature that can utilize this video memory, on line direction in the burst accesses piece and the view data of reading 4 words (4 row) at high speed.

The view data of 4 words of reading continuously (4 row) is taken into data buffer 4611, utilizes parallel → serial converted portion 4612 that digital data is transformed into 1 serial data and generates each laser driver drive signal voluntarily again.(Figure 41)

Therefore, do not use over such expensive line buffer memory also can read at a high speed the laser pumping device drive needed 4 the row view data.

Below, to be that unit carries out the video memory train of impulses and reads with the piece, after the processing that finishes expectation, be that unit carries out the example that is treated to that train of impulses writes again with the piece, to being that the rotation processing of unit describes with the piece.

(a) of Figure 42 is the formation of video memory of preserving the image of available every pixel 1 bit representation (as black white image) shown in (b).

The piece formation is gone by 1 word (32) * 32, and totally 32 words constitute.The rotation of image is that the train of impulses that is shown in the original image piece of Figure 42 (a) is read, once storing the image of reading with rotating part, again the pattern pulse string of the data after the image pixel of scrambling transformation on the sense of rotation storage order after as the processing of (b) that be shown in Figure 42 write in the video memory.

(a) of Figure 43 is the formation of video memory of preserving the image of available every pixel 8 bit representations (as gray level image, coloured image) shown in (b).The piece formation is gone by 1 word (32) * 4, and totally 4 words constitute.The rotation of image is that the train of impulses that is shown in the original image piece of Figure 43 (a) is read, once storing the image of being read with rotating part, the pattern pulse string of the data after the image pixel order of again scrambling transformation on sense of rotation being stored after as (b) processing that is shown in Figure 43 writes in the video memory.

Be to use the rotation processing of page integral body of rotation of the piece image of above-mentioned Figure 42, Figure 43 shown in Figure 44 (a)～(d).

What be shown in Figure 44 (a) is unit rotation processing original image with the piece, and shown in Figure 44 (b), is that unit carries out the rotation processing from the video memory to the video memory with the piece by writing other zone.

What be shown in Figure 44 (a) is unit rotation processing original image with the piece, and shown in Figure 44 (c), forms the image of crossing for the unit rotation processing with the piece by the same piece that writes original image.

Because the image crossed for the unit rotation processing with the piece is exactly the rotation carried out of unit according to pixels, so output image carries out with continuous order that word in the piece is read by the row unit and image rotating is outputed to duplicator etc. (with reference to Figure 44 (d)) on the output unit of order output line by line.

If use video memory of the present invention, then be that the access of unit can utilize burst accesses to carry out rotation processing at a high speed to read, write to realize high speed with the piece.In addition, though be the rotation processing of carrying out in this example, also can be adapted to utilize scramble processing that craspedodrome conversion such as filtering or DCT, image scrambling transformation carry out etc. is all processing of unit with the piece.

As described above, by integral image is divided into piece, but and constitute separately piece with the data of the storage address of burst accesses, if in same, it can carry out burst accesses to the data arbitrarily of one one of transverse direction, longitudinal direction, piece integral body, piece, no matter how the access direction can both carry out the zero access to video memory.

As above detailed description, according to the present invention, can carry out burst accesses to video memory, can provide can zero access image memory access method, image processing system, image form save set, address generating method and address generating device.

Claims (16)

1. image memory access method is characterized in that: by the memory array of being made up of the position of a plurality of row, a plurality of row;

Corresponding with this memory array, can read and write in batch data register 1 row bit data, that keep 1 row bit data in batch;

The row address selecting arrangement to the row of the above-mentioned memory array of reading in batch and writing in batch of 1 row bit data of this data register is carried out in selection;

Selection keeps in the video memory that the column address selecting arrangement of the certain bits of reading and writing of the data register of above-mentioned 1 row bit data constitutes:

Original image is divided into the piece that is made of a plurality of pixels,

Same view data is saved in the same delegation of above-mentioned memory array,

If the pixel data in same is carried out access, then only specify the once row address of above-mentioned memory array, then, come a plurality of pixel datas in same of the access by the column address of only specifying above-mentioned data register.

2. image memory access method as claimed in claim 1 is characterized in that: above-mentioned is to constitute for the integral multiple that constitutes above-mentioned bit data number according to the bit data number that above-mentioned memory array 1 is gone.

3. image memory access method is characterized in that: by the memory array of being made up of the position of a plurality of row, a plurality of row;

Corresponding with this memory array, can read and write in batch data register 1 row bit data, that keep 1 row bit data in batch;

The row address selecting arrangement to the row of the above-mentioned memory array of reading and writing of 1 row bit data of this data register is carried out in selection;

Selection keeps in the video memory that the column address selecting arrangement of the certain bits of reading in batch and writing in batch of the data register of above-mentioned 1 row bit data constitutes:

Original image is divided into the piece that is made of a plurality of pixels,

Same view data is saved in the same delegation of above-mentioned memory array,

If the pixel data in same is carried out access, promptly, if in above-mentioned data register, there is the bit data of eligible row address that is comprised, then come a plurality of pixel datas in same of the access by the column address of only specifying above-mentioned data register.

4. image memory access method as claimed in claim 3 is characterized in that: above-mentioned is to constitute for the integral multiple that constitutes above-mentioned bit data number according to the bit data number that above-mentioned memory array 1 is gone.

5. an image processing system is characterized in that: using the memory array of being made up of the position of a plurality of row, a plurality of row;

Corresponding with this memory array, can read and write in batch data register 1 row bit data, that keep 1 row bit data in batch;

The row address selecting arrangement to the row of the above-mentioned memory array of reading in batch and writing in batch of 1 row bit data of this data register is carried out in selection;

Selection keeps having in the image processing system of the video memory that the column address selecting arrangement of the certain bits of reading and writing of the data register of above-mentioned 1 row bit data constitutes:

Read the reading device of the pixel data of original image,

Being divided into the piece of forming by a plurality of pixels, and same pixel data is saved in save set in the same delegation of above-mentioned memory array by the view data that this reading device read,

If the pixel data in same is read, then only specify the once row address of above-mentioned memory array, then, read the readout device of a plurality of pixel datas in same by the column address of only specifying above-mentioned data register,

The corresponding pixel data of being read by this readout device forms the image processing system that forms image on the medium at image.

6. image processing system as claimed in claim 5, it is characterized in that: above-mentioned readout device is kept at the order of reading of original image pixel data in the above-mentioned video memory by change, read the images that original image rotated 0 degree or 90 degree or 180 degree or 270 degree, and the corresponding pixel data of being read by this readout device forms at image and to form image on the medium.

7. an image processing system is characterized in that: using the memory array of being made up of the position of a plurality of row, a plurality of row;

Corresponding with this memory array, can read and write in batch data register 1 row bit data, that keep 1 row bit data in batch;

The row address selecting arrangement to the row of the above-mentioned memory array of reading in batch and writing in batch of 1 row bit data of this data register is carried out in selection;

Selection keeps having in the image processing system of the video memory that the column address selecting arrangement of the certain bits of reading in batch and writing in batch of the data register of above-mentioned 1 row bit data constitutes:

Read the reading device of the pixel data of original image,

To be divided into the piece of forming by a plurality of pixels by the view data that this reading device read, and same pixel data will be saved in the save set in the same delegation of above-mentioned memory array,

If the pixel data in same is read, promptly, if in above-mentioned data register, there is the bit data of qualified row address that is comprised, then read the readout device of a plurality of pixel datas in same by the column address of only specifying above-mentioned data register

The corresponding pixel data of being read by this readout device forms the image processing system that forms image on the medium at image.

8. image processing system as claimed in claim 7, it is characterized in that: above-mentioned readout device is kept at the order of reading of original image pixel data in the above-mentioned video memory by change, read the images that original image rotated 0 degree or 90 degree or 180 degree or 270 degree, and the corresponding pixel data of being read by this readout device forms at image and to form image on the medium.

9. an image processing system is characterized in that: using the memory array of being made up of the position of a plurality of row, a plurality of row;

Corresponding with this memory array, can read and write in batch data register 1 row bit data, that keep 1 row bit data in batch;

The row address selecting arrangement to the row of the above-mentioned memory array of reading in batch and writing in batch of 1 row bit data of this data register is carried out in selection;

Selection keeps having in the image processing system of the video memory that the column address selecting arrangement of the certain bits of reading in batch and writing in batch of the data register of above-mentioned 1 row bit data constitutes:

Read the reading device of the pixel data of original image,

Be divided into the piece of forming by a plurality of pixels by the view data that this reading device read, make and when forming image, the pixel data that forms image simultaneously is included in same, and same pixel data is saved in save set in the same delegation of above-mentioned memory array

If the pixel data in same is read, promptly, if in above-mentioned data register, there is the bit data of qualified row address that is comprised, then by the column address of only specifying above-mentioned data register read a plurality of pixel datas in same, to read out in the readout device that side by side forms the pixel data of image when forming image continuously

The corresponding pixel data of being read by this readout device forms the image processing system that on the medium a plurality of pixels is formed simultaneously image at image.

10. an image processing system is characterized in that: using the memory array of being made up of the position of a plurality of row, a plurality of row;

Corresponding with this memory array, can read and write in batch data register 1 row bit data, that keep 1 row bit data in batch;

The row address selecting arrangement to the row of the above-mentioned memory array of reading in batch and writing in batch of 1 row bit data of this data register is carried out in selection;

Selection keeps having in the image processing system of the video memory that the column address selecting arrangement of the certain bits of reading and writing of the data register of above-mentioned 1 row bit data constitutes:

Read the reading device of the pixel data of original image,

Be divided into the piece of forming by a plurality of pixels by the view data that this reading device read, make and when forming image, the pixel data that forms image simultaneously is included in same, and same pixel data is saved in save set in the same delegation of above-mentioned memory array

If the pixel data in same is read, promptly, if in above-mentioned data register, there is the bit data of qualified row address that is comprised, then the column address by only specifying above-mentioned data register, read the readout device that when forming image, side by side forms the pixel data of image continuously with a plurality of pixel datas in same

The corresponding pixel data of being read by this readout device forms the image processing system that on the medium a plurality of pixels is formed simultaneously image at image.

11. an image processing system is characterized in that: using the memory array of forming by the position of a plurality of row, a plurality of row;

Corresponding with this memory array, can read and write in batch data register 1 row bit data, that keep 1 row bit data in batch;

Selection carry out to this data register 1 the row bit data row that read in batch and write in batch, above-mentioned memory array, the row address selecting arrangement;

Selection keeps having in the image processing system of the video memory that read in batch and write in batch, certain bits, the column address selecting arrangement of the data register of above-mentioned 1 row bit data constitutes:

Read the reading device of the pixel data of original image,

The image segmentation of utilizing this reading device to read is become the piece of being made up of a plurality of pixels that constitute encoding process unit, and same pixel data is saved in the save set in the same delegation of above-mentioned memory array,

If the pixel data in same is read, then only specify the once row address of above-mentioned memory array, then, the column address by only specifying above-mentioned data register, read the readout device of a plurality of pixel datas of the piece that constitutes encoding process unit in batch.

The code device that the pixel data of the piece of being read by this readout device is encoded, will be that the coded data that is encoded of unit is decoded with the piece,

Preservation utilizes the coded data save set of the coded data that above-mentioned code device encodes,

By sequence of pages arbitrarily, read be kept at coded data in the coded data save set, more than 1 page, coded data readout device and will be the decoding device that the coded data that is encoded of unit is decoded with the piece.

What only specify once decoding is the row address that the pixel data of unit lists at above-mentioned memory array with the piece, then, writes writing station as a plurality of pixel datas of the piece of decoding processing unit in batch by the column address of only specifying above-mentioned data register;

The corresponding pixel data that is write by this above-mentioned writing station forms the image processing system that forms image on the medium at image.

12. an address generating method is characterized in that: for a plurality of words on a plurality of words, the column direction on the line direction as 1 piece, and there are a plurality of in this piece, have a plurality of video memory at column direction on line direction,

When video memory is carried out two-dimentional access,

On the row of regulation, generate the address of the burst accesses of the column direction number of words that constitutes 1 piece,

Whenever carry out the address after the access of pulsatile once string just generates the number of words that adds 1 of formation,

Whenever carry out a plurality of burst accesses of a column direction, just multiply by with the value of the number of words that constitutes 1 piece and from a plurality of numbers of column direction, deduct a value behind the piece, and add on the value after deducting this value and the value of the number of words of the column direction in 1 again its end value is generated as the address

Whenever carry out the burst accesses of a plurality of of column directions of a plurality of numbers of words of line direction, just the value of the number of words that deducts the column direction that constitutes 1 piece from the number of words that constitutes 1 piece is produced as the address.

13. an address generating device is characterized in that: for a plurality of words of line direction, a plurality of words of column direction as 1 piece, and there are a plurality of in this piece, have a plurality of video memory at column direction on line direction,

When carrying out two-dimentional access video memory,

On the row of regulation, generate the address of the burst accesses of the column direction number of words that constitutes 1 piece,

Whenever carry out the address after the access of pulsatile once string just generates the number of words that adds 1 of formation,

Whenever carry out a plurality of burst accesses of a column direction, just multiply by with the value of the number of words that constitutes 1 piece and from a plurality of numbers of column direction, deduct a value behind the piece, and add on the value after deducting this value and the value of the number of words of the column direction in 1 again its end value is generated as the address

Whenever carry out the burst accesses of a plurality of of column directions of a plurality of numbers of words of line direction, just the address generating device that the value of the number of words that deducts the column direction that constitutes 1 piece from the number of words that constitutes 1 piece is produced as the address.

14. a storage address generating apparatus is characterized in that: in the memory array of forming by the position of a plurality of row, a plurality of row;

Corresponding with this memory array, can read and write in batch data register 1 row bit data, that keep 1 row bit data in batch;

The row address selecting arrangement to the row that read in batch and write in batch, above-mentioned memory array of 1 row bit data of this data register is carried out in selection;

Selection keeps the column address selecting arrangement that read and write, certain bits of the data register of above-mentioned 1 row bit data to constitute, and is

Original image is divided into the piece of being made up of a plurality of pixels,

Same pixel data is saved in the same delegation of above-mentioned memory array,

If, then only specify the once row address of above-mentioned memory array to the access of the pixel data in same, then, come by the column address of only specifying above-mentioned data register in the video memory of a plurality of pixel datas of access in constituting same,

The address of representing as low order address as high address, column address with the row address of above-mentioned video memory as the one dimension storage address,

The a plurality of words of line direction, a plurality of words of column direction as a piece, the block structure of original image is divided into a plurality of on line direction, be divided into a plurality of on the column direction, and when carrying out two-dimentional access,

Calculate the flat address that each piece carries out the word of access at first,

The value of the row address that is equivalent to this flat address is specified once as the row address of above-mentioned memory array,

On the value of the column address that is equivalent to above-mentioned flat address, add that the value after the off-set value of the plus or minus that each consecutive access is general sets in proper order as the column address of above-mentioned memory array, and only consecutive access in the piece is carried out in the specify columns address,

The above-mentioned address generating device that is used to carry out consecutive access comprises:

Preserve the storage address save set of present consecutive access start address;

The first address increment specified device;

The second address increment specified device;

Three-address increment specified device;

A consecutive access as the 1st counting assembly that once calculates the consecutive access number of times;

A consecutive access as the 2nd counting assembly that once calculates the consecutive access number of times;

The 1st count cycle specified device of above-mentioned the 1st counting assembly;

The 2nd count cycle specified device of above-mentioned the 2nd counting assembly;

With the consecutive access start address is starting point, specifies the specified device to the displacement of the storage address of each word of carrying out consecutive access,

The access start address of each consecutive access is calculated as follows: promptly the flat address with the word that carries out access at first of the page is an initial value, with respect to the above-mentioned storage address save set of preserving present consecutive access start address, just add the 1st address increment by whenever carrying out the one-time continuous access, whenever the consecutive access that carries out one the 1st count cycle just adds the 2nd address increment, whenever the consecutive access that carries out one the 2nd count cycle adds that just the 3rd address increment calculates

Carry out the storage address of the word of each consecutive access,, add that the displacement meter of the storage address of each word that carries out above-mentioned consecutive access calculates by start address with respect to above-mentioned consecutive access.

15. storage address generating apparatus as claimed in claim 14, it is characterized in that: above-mentioned the 1st address increment, the 2nd address increment, the 3rd address increment, the 1st count cycle, the 2nd count cycle and can come out according to the access direction calculating of the video memories of the piece number of the column direction that constitutes above-mentioned 1 page, the piece number that constitutes the line direction of above-mentioned 1 page, the number of words that constitutes the column direction of 1 piece, the number of words of line direction that constitutes 1 piece and 0 degree, 90 degree, 180 degree, 270 degree to the displacement of the storage address of each word that carries out above-mentioned consecutive access.

16. an image processing system is characterized in that: in the memory array of forming by the position of a plurality of row, a plurality of row;

Corresponding with this memory array, can read and write in batch data register 1 row bit data, that keep 1 row bit data in batch;

The row address selecting arrangement to the row that read in batch and write in batch, above-mentioned memory array of 1 row bit data of this data register is carried out in selection;

Selection keeps the data register, that column address selecting arrangement that read and write, certain bits constitutes of above-mentioned 1 row bit data and is

Original image is divided into the piece of being made up of a plurality of pixels,

Same pixel data is saved in the same delegation of above-mentioned memory array,

If the pixel data in same is carried out access, then only specify the once row address of above-mentioned memory array, come in the video memory of a plurality of pixel datas of access in constituting same by the column address of only specifying above-mentioned data register again,

Use the storage address generating apparatus of following formation, that is:

The address that the row address of above-mentioned video memory is represented as low order address as high address, column address is as the one dimension storage address,

The a plurality of words of line direction, a plurality of words of column direction as a piece, are divided into a plurality of to the block structure of original image on line direction, are divided into a plurality of on the column direction, and when carrying out two-dimentional access,

Calculate the flat address of word of the initial access of each piece,

The value of the row address that is equivalent to this flat address is specified once as the row address of above-mentioned memory array,

On the value of the column address that is equivalent to above-mentioned flat address, add that the value after the off-set value of the plus or minus that each consecutive access is general sets in proper order as the column address of above-mentioned memory array, and only consecutive access in the piece is carried out in the specify columns address,

The address generating device that is used to carry out above-mentioned consecutive access comprises:

Preserve the storage address save set of present consecutive access start address;

The first address increment specified device;

The second address increment specified device;

Three-address increment specified device;

A consecutive access as the 1st counting assembly that once calculates the consecutive access number of times;

A consecutive access as the 2nd counting assembly that once calculates the consecutive access number of times;

The 1st count cycle specified device of above-mentioned the 1st counting assembly;

The 2nd count cycle specified device of above-mentioned the 2nd counting assembly;

With the consecutive access start address is starting point, specifies the specified device to the displacement of the storage address of each word of carrying out consecutive access,

The access start address of each consecutive access is calculated as follows: promptly, flat address with the word of the initial access of the page is an initial value, with respect to the above-mentioned storage address save set of preserving present consecutive access start address, just add the 1st address increment by whenever carrying out the one-time continuous access, whenever carry out the consecutive access of one the 1st count cycle, just add the 2nd address increment, whenever carry out the consecutive access of one the 2nd count cycle, just add that the 3rd address increment calculates

Use the storage address generating apparatus to calculate the storage address of the word of each consecutive access, this address is by the start address with respect to above-mentioned consecutive access, adds that the displacement meter of the storage address of each word that carries out above-mentioned consecutive access calculates,

The corresponding pixel data of reading from above-mentioned video memory forms medium at image and forms image.

Images