CN104091762A - Method for preparing bipolar transistor - Google Patents
Method for preparing bipolar transistor Download PDFInfo
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- CN104091762A CN104091762A CN201410339420.2A CN201410339420A CN104091762A CN 104091762 A CN104091762 A CN 104091762A CN 201410339420 A CN201410339420 A CN 201410339420A CN 104091762 A CN104091762 A CN 104091762A
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- bipolar transistor
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- wet etching
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- 238000000034 method Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 238000001039 wet etching Methods 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 230000007797 corrosion Effects 0.000 claims abstract description 16
- 238000005260 corrosion Methods 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000002360 preparation method Methods 0.000 claims description 34
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 30
- 230000008569 process Effects 0.000 claims description 10
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 239000002253 acid Substances 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical group [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 239000008367 deionised water Substances 0.000 claims description 3
- 229910021641 deionized water Inorganic materials 0.000 claims description 3
- 229910017604 nitric acid Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 230000001105 regulatory effect Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 abstract 7
- 230000003647 oxidation Effects 0.000 abstract 7
- 238000007254 oxidation reaction Methods 0.000 abstract 7
- 230000003321 amplification Effects 0.000 abstract 1
- 238000003199 nucleic acid amplification method Methods 0.000 abstract 1
- 239000002344 surface layer Substances 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Weting (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a method for preparing a bipolar transistor. The method includes the steps that a semi-conductor substrate is provided, and a first oxidation layer is deposited on the substrate; the first oxidation layer is selectively etched until the substrate is exposed so that a through hole can be formed; the substrate in the through hole is oxidized to form a second oxidation layer, wherein the second oxidation layer is thinner than the first oxidation layer; first wet etching is carried out to remove the second oxidation layer and a part of the first oxidation layer on the side wall of the through hole, wherein the corrosion rate of the first wet etching is smaller than or equal to 60 micro amperes per minute, selective etching is carried out, and the surface layer of the substrate in the through hole is processed; a metal electrode is prepared and covers the through hole. According to the method for preparing the bipolar transistor, leakage currents and amplification gain of the bipolar transistor can be regulated.
Description
Technical field
The present invention relates to semiconductor device processing technology field, particularly relate to a kind of preparation method of bipolar transistor.
Background technology
Bipolar transistor (Bipolar transistor), includes the transistors such as Schottky diode (SKY diode), NPN triode etc., has the advantages such as high speed, high transconductance, low noise and higher current driving ability.The development of bipolar transistor is very fast in recent years.Wherein, NPN triode on gain amplifier and the leakage current of Schottky diode be the important parameter that affects the performance of bipolar transistor.Therefore in the preparation technology of bipolar transistor, need to be to the regulating and controlling of gain amplifier and leakage current, make the leakage current of Schottky diode little, the gain amplifier of NPN triode is large.
Summary of the invention
The object of the invention is to, a kind of preparation method of bipolar transistor is provided, the gain amplifier of the leakage current to Schottky diode and NPN triode regulates and controls.
In order to achieve the above object, the invention provides a kind of preparation method of bipolar transistor, it is characterized in that, comprising:
Semiconductor substrate is provided, on described substrate, deposits one first oxide layer;
The first oxide layer described in selective etch is until expose described substrate, to form through hole;
Oxidized formation one second oxide layer of described substrate in described through hole, the thickness of described the second oxide layer is less than the thickness of described the first oxide layer;
Carry out the first wet etching, remove part first oxide layer of described the second oxide layer and described through-hole side wall, the corrosion rate of described the first wet etching is less than or equal to
Carry out selective etch, process the top layer of the described substrate in described through hole;
Prepare metal electrode, described metal electrode covers described through hole.
Further, the corrosion rate of described the first wet etching is
Further, described the first wet etching adopts hydrofluoric acid solution, and the concentration of described hydrofluoric acid solution is 0.1%～1.0%.
Further, described the first wet etching adopts hydrofluoric acid solution, and the concentration of described hydrofluoric acid solution is 0.5%.
Further, described bipolar transistor is Schottky diode.
Further, adopt the second wet etching to carry out selective etch.
Further, the corrosion rate of the second wet etching is
Further, described the second wet etching adopts Compound-acid solution, and the etching time of described the second wet etching is 10s～15s.
Further, described Compound-acid solution comprises nitric acid, phosphoric acid, acetic acid and deionized water.
Further, described bipolar transistor is NPN triode.
Further, adopt dry etching to carry out selective etch.
Further, described metal electrode is platinum electrode.
Compared with prior art, the preparation method of bipolar transistor provided by the invention, has following beneficial effect:
The preparation method of bipolar transistor provided by the invention, comprising: Semiconductor substrate is provided, deposits one first oxide layer on described substrate; The first oxide layer described in selective etch is until expose described substrate, to form through hole; Oxidized formation one second oxide layer of described substrate in described through hole, the thickness of described the second oxide layer is less than the thickness of described the first oxide layer; Carry out the first wet etching, remove part first oxide layer of described the second oxide layer and described through-hole side wall, the corrosion rate of described the first wet etching is less than or equal to
carry out selective etch, process the top layer of the described substrate in described through hole; Prepare metal electrode, described metal electrode covers described through hole.The preparation method of bipolar transistor of the present invention, can regulate and control leakage current and the gain amplifier of bipolar transistor.
Brief description of the drawings
Fig. 1 is the preparation method's of the bipolar transistor in one embodiment of the invention flow chart;
Fig. 2 to Fig. 7 is the profile of the each step corresponding construction of the preparation method of the bipolar transistor in one embodiment of the invention.
Embodiment
Below in conjunction with schematic diagram, the preparation method of bipolar transistor of the present invention is described in more detail, the preferred embodiments of the present invention are wherein represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example, according to about system or about the restriction of business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, with way of example, the present invention is more specifically described with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Core of the present invention is, the preparation method of the bipolar transistor providing, comprising: Semiconductor substrate is provided, deposits one first oxide layer on described substrate; The first oxide layer described in selective etch is until expose described substrate, to form through hole; Oxidized formation one second oxide layer of described substrate in described through hole, the thickness of described the second oxide layer is less than the thickness of described the first oxide layer; Carry out the first wet etching, remove part first oxide layer of described the second oxide layer and described through-hole side wall, the corrosion rate of described the first wet etching is less than or equal to
carry out selective etch, process the top layer of the described substrate in described through hole; Prepare metal electrode, described metal electrode covers described through hole.The preparation method of bipolar transistor of the present invention, can regulate and control leakage current and the gain amplifier of bipolar transistor.
Concrete, in conjunction with above-mentioned core concept, the preparation method of bipolar transistor provided by the invention, flow chart is with reference to figure 1, and concrete comprises:
Step S1, provides Semiconductor substrate, deposits one first oxide layer on described substrate;
Step S2, the first oxide layer described in selective etch is until expose described substrate, to form through hole;
Step S3, oxidized formation one second oxide layer of described substrate in described through hole, the thickness of described the second oxide layer is less than the thickness of described the first oxide layer;
Step S4, carries out the first wet etching, removes part first oxide layer of described the second oxide layer and described through-hole side wall, and the corrosion rate of described the first wet etching is less than or equal to
Step S5, carries out selective etch, processes the top layer of the described substrate in described through hole;
Step S6, prepares metal electrode, and described metal electrode covers described through hole.
Below enumerate several embodiment of the preparation method of described bipolar transistor, to clearly demonstrate content of the present invention, will be clear that, content of the present invention is not restricted to following examples, and other improvement by those of ordinary skill in the art's routine techniques means are also within thought range of the present invention.
The first embodiment
Below in conjunction with Fig. 2 to Fig. 6, illustrate the preparation method of bipolar transistor of the present invention.In the present embodiment, taking described bipolar junction transistor as Schottky diode as example specifically describes.
Shown in figure 2, carry out step S1, Semiconductor substrate 11 is provided, on described substrate 11, deposit one first oxide layer 12.Described substrate 11 can be silicon substrate, and comprising well region, buried regions etc., this is what it will be appreciated by those skilled in the art that, in Fig. 2, does not specifically illustrate.
Shown in figure 3, carry out step S2, the first oxide layer 12 described in selective etch is until spill described substrate 11, to form through hole 13.In the preparation method of described bipolar transistor, described through hole 13 is as the passage that connects described substrate and metal electrode.
Shown in figure 4, carry out step S3, oxidized formation one second oxide layer 14 on the described substrate 11 in described through hole 13, the thickness of described the second oxide layer 14 is less than the thickness of described the first oxide layer 12.Described the second oxide layer 14 is non-artificial generation in technical process, and is difficult to avoid.
Shown in figure 5, carry out step S4, carry out the first wet etching, remove part first oxide layer of described the second oxide layer 14 and described through hole 13 sidewalls, the corrosion rate of described the first wet etching is less than or equal to
the width of described through hole 13 is than carrying out large before described step S4.Preferably, the corrosion rate of described the first wet etching is
in the present embodiment, described the first wet etching adopts hydrofluoric acid solution, and the concentration of described hydrofluoric acid solution is preferably 0.1%～1.0%.Preferably, the concentration of described hydrofluoric acid solution is 0.5%.In actual process, adopt the new hydrofluoric acid solution of opening, the new hydrofluoric acid solution of opening is clean, and new hydrofluoric acid solution corrosion rate of opening is stable.The hydrofluoric acid solution of low concentration, the speed of corrosion is slow, more in short-term, can guarantee at described the first wet etching course at etching time, described the second oxide layer 14 is removed, thereby made to have conductive communication better between metal electrode and Semiconductor substrate 11; And described the first oxide layer 12 has only been corroded the sidewall at described through hole 13, make the diameter of described through hole 13 become large, be conducive to regulate the performance of described bipolar transistor.
Shown in figure 6, carry out step S5, carry out selective etch, process the top layer of the described substrate 11 in described through hole 13.What in the present embodiment, described selective etch adopted is the second wet etching.The corrosion rate of described the second wet etching is
preferably, described the second wet etching adopts Compound-acid solution, and the etching time of described the second wet etching is 10s～15s, and described Compound-acid solution comprises nitric acid, phosphoric acid, acetic acid and deionized water.While carrying out step S2, form in the process of through hole 13 described the first oxide layer 12 being carried out to selective etch, can introduce defect on the top layer of described substrate 11, the performance impact of the described Schottky diode of described defect to preparation is larger, and especially the impact of the leakage current on described Schottky diode is larger.But, adopt described the second wet etching by after the top layer processing of the described substrate 11 in described through hole 13, can remove the defect on described top layer, the leakage current of described Schottky diode is significantly reduced, improve the performance of described Schottky diode.
Shown in figure 7, carry out step S6, prepare metal electrode 15, described metal electrode covers described through hole 13, and preferred, described metal electrode 15 is platinum electrode.
The second embodiment
In the present embodiment, described bipolar transistor is NPN triode, the preparation method of the bipolar transistor of the preparation method of the bipolar transistor of described the second embodiment and described the first embodiment is basic identical, its difference is: in step S5, what described selective etch adopted is dry etching.The top layer atom of substrate 11 described in plasma bombardment for described dry etching, these top layer atoms react with the active particle in plasma, forming volatility product is removed, improve the performance of described substrate surface, contribute to improve significantly the gain amplifier of described NPN triode, improve the performance of described NPN triode.
Described bipolar transistor is not limited to above-mentioned two kinds of Schottky diodes and NPN triode, the bipolar transistor of other types, and for example PNP triode, also within thought range of the present invention.
In sum, the preparation method of bipolar transistor provided by the invention, comprising: Semiconductor substrate is provided, deposits one first oxide layer on described substrate; The first oxide layer described in selective etch is until expose described substrate, to form through hole; Oxidized formation one second oxide layer of described substrate in described through hole, the thickness of described the second oxide layer is less than the thickness of described the first oxide layer; Carry out the first wet etching, remove part first oxide layer of described the second oxide layer and described through-hole side wall, the corrosion rate of described the first wet etching is less than or equal to
carry out selective etch, process the top layer of the described substrate in described through hole; Prepare metal electrode, described metal electrode covers described through hole.The preparation method of bipolar transistor of the present invention, can regulate and control leakage current and the gain amplifier of bipolar transistor.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (12)
1. a preparation method for bipolar transistor, is characterized in that, comprising:
Semiconductor substrate is provided, on described substrate, deposits one first oxide layer;
The first oxide layer described in selective etch is until expose described substrate, to form through hole;
Oxidized formation one second oxide layer of described substrate in described through hole, the thickness of described the second oxide layer is less than the thickness of described the first oxide layer;
Carry out the first wet etching, remove part first oxide layer of described the second oxide layer and described through-hole side wall, the corrosion rate of described the first wet etching is less than or equal to
Carry out selective etch, process the top layer of the described substrate in described through hole;
Prepare metal electrode, described metal electrode covers described through hole.
2. the preparation method of a kind of bipolar transistor as claimed in claim 1, is characterized in that, the corrosion rate of described the first wet etching is
3. the preparation method of a kind of bipolar transistor as claimed in claim 1, is characterized in that, described the first wet etching adopts hydrofluoric acid solution, and the concentration of described hydrofluoric acid solution is 0.1%～1.0%.
4. the preparation method of a kind of bipolar transistor as claimed in claim 3, is characterized in that, described the first wet etching adopts hydrofluoric acid solution, and the concentration of described hydrofluoric acid solution is 0.5%.
5. the preparation method of a kind of bipolar transistor as claimed in claim 1, is characterized in that, described bipolar transistor is Schottky diode.
6. the preparation method of a kind of bipolar transistor as claimed in claim 5, is characterized in that, adopts the second wet etching to carry out selective etch.
7. the preparation method of a kind of bipolar transistor as claimed in claim 6, is characterized in that, the corrosion rate of described the second wet etching is
8. the preparation method of a kind of bipolar transistor as claimed in claim 6, is characterized in that, described the second wet etching adopts Compound-acid solution, and the etching time of described the second wet etching is 10s～15s.
9. the preparation method of a kind of bipolar transistor as claimed in claim 8, is characterized in that, described Compound-acid solution comprises nitric acid, phosphoric acid, acetic acid and deionized water.
10. the preparation method of a kind of bipolar transistor as claimed in claim 1, is characterized in that, described bipolar transistor is NPN triode.
The preparation method of 11. a kind of bipolar transistors as claimed in claim 8, is characterized in that, adopts dry etching to carry out selective etch.
The preparation method of 12. a kind of bipolar transistors as claimed in claim 1, is characterized in that, described metal electrode is platinum electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410339420.2A CN104091762A (en) | 2014-07-16 | 2014-07-16 | Method for preparing bipolar transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410339420.2A CN104091762A (en) | 2014-07-16 | 2014-07-16 | Method for preparing bipolar transistor |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6020254A (en) * | 1995-11-22 | 2000-02-01 | Nec Corporation | Method of fabricating semiconductor devices with contact holes |
| CN1574290A (en) * | 2003-05-21 | 2005-02-02 | 海力士半导体有限公司 | Method of manufacturing semiconductor device |
| CN103346126A (en) * | 2013-06-26 | 2013-10-09 | 上海宏力半导体制造有限公司 | Method for forming flash memory storage unit |
-
2014
- 2014-07-16 CN CN201410339420.2A patent/CN104091762A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6020254A (en) * | 1995-11-22 | 2000-02-01 | Nec Corporation | Method of fabricating semiconductor devices with contact holes |
| CN1574290A (en) * | 2003-05-21 | 2005-02-02 | 海力士半导体有限公司 | Method of manufacturing semiconductor device |
| CN103346126A (en) * | 2013-06-26 | 2013-10-09 | 上海宏力半导体制造有限公司 | Method for forming flash memory storage unit |
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