CN104079014B - A kind of UPS parallel system and method for transmitting signals - Google Patents
A kind of UPS parallel system and method for transmitting signals Download PDFInfo
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- CN104079014B CN104079014B CN201310097917.3A CN201310097917A CN104079014B CN 104079014 B CN104079014 B CN 104079014B CN 201310097917 A CN201310097917 A CN 201310097917A CN 104079014 B CN104079014 B CN 104079014B
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Abstract
Embodiments provide a kind of UPS parallel system and method for transmitting signals, during in order to solve to use the logic circuit built by ancillary equipment based on the control chip in UPS to carry out communication present in prior art, the problem that these Logic Circuit Design are complicated, debugging difficulty is bigger.This system includes multiple UPS and the bus of parallel connection, wherein, comprises a control chip and receive transmission chip in each UPS；Control chip in each UPS connects the reception in this UPS and sends chip, and the reception in each UPS sends chip and is all connected with described bus.
Description
Technical field
The present invention relates to technical field of electronic control, particularly relate to a kind of UPS parallel system and signal transmission
Method.
Background technology
UPS(Uninterruptible Power Supply, uninterrupted power source) refer to when alternating current input power supplying (is practised
Used it is referred to as civil power) when there is exception or power-off, moreover it is possible to continue to power to the load, and can guarantee that power supply quality,
Make the impregnable device of load supplying, it is possible to ensure the reliability of power supply.At some, power supply reliability is wanted
Ask in higher occasion, it will usually use mode in parallel for multiple UPS to improve power supply reliability further.
At present, can be by based on the ancillary equipment in the control chip in UPS between each UPS in parallel
The logic circuit built carries out communication, and wherein, the ancillary equipment in control chip refers in control chip except place
Miscellaneous equipment beyond reason device and random access memory (RAM, Random Access Memory),
Such as pin etc..But, these Logic Circuit Design are got up more complicated, and debugging difficulty is big.
In sum, when carrying out communication between each UPS in parallel, prior art also exists employing and passes through
When the logic circuit that ancillary equipment based on the control chip in UPS is built carries out communication, these logic electricity
The problem that road design is complicated, debugging difficulty is bigger.
Summary of the invention
Embodiments provide a kind of UPS parallel system and method for transmitting signals, existing in order to solve
The logic circuit built by ancillary equipment based on the control chip in UPS is used to enter present in technology
During row communication, the problem that these Logic Circuit Design are complicated, debugging difficulty is bigger.
Based on the problems referred to above, a kind of UPS parallel system that the embodiment of the present invention provides, including in parallel many
Individual UPS and bus, wherein, comprise a control chip and receive transmission chip in each UPS；
Control chip in each UPS connects the reception in this UPS and sends chip, connecing in each UPS
Transmit and receive chip and be all connected with described bus；
Control chip in each UPS, at the signal sending time determined according to the mark of this UPS self,
Chip is sent by the reception in the ancillary equipment transmission serial signal in this control chip to this UPS, with
And receive receiving in this UPS by the ancillary equipment in this control chip and send the serial sent of chip and believe
Number；
Reception in each UPS sends chip, and the serial received by the control chip from this UPS is believed
Number carry out logical operations with the signal in bus, and by the signal that obtains after logical operations by described bus
Send to each UPS in parallel system, and the signal received in described bus is converted into serial letter
Number send to the control chip in this UPS.
The embodiment of the present invention also provides for the method for transmitting signals of a kind of UPS parallel system, including:
The control chip in each UPS in parallel system is at the letter determined according to the mark of this UPS self
Number send the time, send serial signal to the reception in this UPS by ancillary equipment in this control chip
Send chip, and received the reception transmission chip in this UPS by the ancillary equipment in this control chip
The serial signal sent；
Receiving in each UPS in parallel system sends chip and is received by the control chip from this UPS
To serial signal and bus on signal carry out logical operations, and the signal obtained after logical operations is led to
Cross described bus to send to each UPS in parallel system, and the signal received in described bus is turned
Turn to serial signal and send the control chip to this UPS.
The beneficial effect of the embodiment of the present invention includes:
Embodiments provide a kind of UPS parallel system and method for transmitting signals, when in parallel system
Each UPS between when communicating, the UPS sending signal can be at the letter determined according to the mark of self
Number send the time, by self receive send chip serial signal that the control chip of self is sent with should
The signal in bus that UPS connects carries out logical operations, and by the signal obtained after logical operations by being somebody's turn to do
Bus sends each UPS to parallel system, and the UPS receiving the signal in bus passes through self
Signal in bus is converted to serial signal and sends the control chip to self by reception transmission chip, thus real
The communication between each UPS in existing parallel system.A kind of UPS parallel system that the embodiment of the present invention provides
In each UPS in control chip send, receive signal time be by with connecing that this control chip is connected
Transmit and receive chip and send what the bus that is connected of chip completed with this reception, it is not necessary to again based on control chip
In ancillary equipment remove to build corresponding logic circuit, thus solve present in prior art use logical
Cross the logic circuit that ancillary equipment based on the control chip in UPS builds when carrying out communication, these logics
The problem that complex circuit designs, debugging difficulty are bigger.
Accompanying drawing explanation
The structure chart of a kind of UPS parallel system that Fig. 1 provides for the embodiment of the present invention；
The flow chart of the method for transmitting signals of a kind of UPS parallel system that Fig. 2 provides for the embodiment of the present invention；
Control chip in the UPS parallel system that Fig. 3 provides for the embodiment of the present invention is the most true
Determine the flow chart of signal sending time.
Detailed description of the invention
Embodiments provide a kind of UPS parallel system and method for transmitting signals, in this parallel system
Each UPS in control chip by the reception that is connected with this control chip send chip and with this reception
Send the connected bus of chip and complete transmission and the acceptance of signal, without by based in control chip
The corresponding logic circuit that ancillary equipment is built completes to go to build phase based on the ancillary equipment in control chip
The logic circuit answered, thus solve in prior art in parallel system for carrying out communication between UPS
The problem that Logic Circuit Design is complicated, debugging difficulty is bigger.
Below in conjunction with Figure of description, a kind of UPS parallel system that the embodiment of the present invention is provided and signal
The detailed description of the invention of transmission method illustrates.
A kind of UPS parallel system that the embodiment of the present invention provides, including multiple UPS in parallel and bus,
Wherein, each UPS comprises a control chip and receives transmission chip；Control core in each UPS
Sheet connects reception in this UPS and sends chip, the reception in each UPS send chip be all connected with described always
Line；Control chip in each UPS, at the signal sending time determined according to the mark of this UPS self,
Chip is sent by the reception in the ancillary equipment transmission serial signal in this control chip to this UPS, with
And receive receiving in this UPS by the ancillary equipment in this control chip and send the serial sent of chip and believe
Number；Reception in each UPS sends chip, and the serial received by the control chip from this UPS is believed
Number carry out logical operations with the signal in bus, and by the signal that obtains after logical operations by described bus
Send to each UPS in parallel system, and the signal received in described bus is converted into serial letter
Number send to the control chip in this UPS.
In concrete application scenarios one, as it is shown in figure 1, this UPS parallel system include UPS1, UPS2,
UPS3 and bus 11, UPS1 includes control chip CC1 and receives transmission chip TRC1, in UPS2
Send chip TRC2, UPS3 including control chip CC2 and reception and include control chip CC3 and reception
Send chip TRC3；Wherein, receive transmission chip TRC1 and connect control chip CC1 and bus 11 respectively,
Receive transmission chip TRC2 and connect control chip CC2 and bus 11 respectively, receive and send chip TRC3
Connect control chip CC3 and bus 11 respectively.
More specifically, the signal of control chip CC1 sends pin connects the signal receiving transmission chip TRC1
Receiving pin, the signal of control chip CC1 receives the signal of pin connection reception transmission chip TRC1 and sends
Pin；The signal of control chip CC2 sends pin and connects the signal reception pin receiving transmission chip TRC2,
The signal of control chip CC2 receives pin and connects the signal transmission pin receiving transmission chip TRC2；Control
The signal of chip CC3 sends pin and connects the signal reception pin receiving transmission chip TRC3, control chip
The signal of CC3 receives pin and connects the signal transmission pin receiving transmission chip TRC3.Receive and send chip
High level signal pin in TRC1 connects the holding wire for transmitting high level signal in bus 11, connects
Transmit and receive low level signal pin in chip TRC1 connect in bus 11 for transmitting low level signal
Holding wire；Receive being used in the high level signal pin connection bus 11 sent in chip TRC2 to pass
The holding wire of defeated high level signal, receives the low level signal pin sent in chip TRC2 and connects bus 11
In for transmitting the holding wire of low level signal；Receive the high level signal pin sent in chip TRC3
Connect the holding wire for transmitting high level signal in bus 11, receive send in chip TRC3 low
Level signal pin connects the holding wire for transmitting low level signal in bus 11.
According to the mark of UPS1, control chip CC1 in UPS1 determines that UPS1 sends the time of signal,
And the ancillary equipment in the signal sending time determined is by control chip CC1 sends serial signal to connecing
Transmit and receive chip TRC1, and received by receiving transmission chip by the ancillary equipment in control chip CC1
The serial signal that TRC1 sends；Reception in UPS1 sends chip TRC1 and will connect from control chip CC1
Signal in the serial signal received and bus 11 carries out logical operations, and will obtain after logical operations
Signal sent to UPS1, UPS2 and UPS3 by bus 11, and will receive in bus 11
Signal is converted into serial signal and sends to control chip CC1.
According to the mark of UPS2, control chip CC2 in UPS2 determines that UPS2 sends the time of signal,
And the ancillary equipment in the signal sending time determined is by control chip CC2 sends serial signal to connecing
Transmit and receive chip TRC2, and received by receiving transmission chip by the ancillary equipment in control chip CC2
The serial signal that TRC2 sends；Reception in UPS2 sends chip TRC2 and will connect from control chip CC2
Signal in the serial signal received and bus 11 carries out logical operations, and will obtain after logical operations
Signal sent to UPS1, UPS2 and UPS3 by bus 11, and will receive in bus 11
Signal is converted into serial signal and sends to control chip CC2.
According to the mark of UPS3, control chip CC3 in UPS3 determines that UPS3 sends the time of signal,
And the ancillary equipment in the signal sending time determined is by control chip CC3 sends serial signal to connecing
Transmit and receive chip TRC3, and received by receiving transmission chip by the ancillary equipment in control chip CC3
The serial signal that TRC3 sends；Reception in UPS3 sends chip TRC3 and will connect from control chip CC3
Signal in the serial signal received and bus 11 carries out logical operations, and will obtain after logical operations
Signal sent to UPS1, UPS2 and UPS3 by bus 11, and will receive in bus 11
Signal is converted into serial signal and sends to control chip CC3.
Wherein, the mark of the mark of UPS1, the mark of UPS2 and UPS3 respectively with UPS1, UPS2 and
UPS3 one_to_one corresponding.
Further, the control chip of each UPS in parallel system specifically for: comprising this control core
The UPS of sheet power on after to bus monitoring preset duration, if the string received after the preset duration monitored terminates
During row signal error, determine signal sending time according to the mark of the UPS comprising this control chip, if connecing
After receiving correct serial signal, then receive, according to be connected with this control chip, the string that transmission chip is sent
The mark of UPS sending this signal comprised in row signal and the mark of the UPS comprising this control chip,
Determine the signal sending time of this control chip；And at the signal sending time determined, by this control chip
In ancillary equipment send serial signal to the reception that is connected with this control chip and send chip, and by should
Ancillary equipment in control chip receives the reception being connected with this control chip and sends the serial letter that chip is sent
Number.
In concrete application scenarios one, as it is shown in figure 1, the control chip CC1 of UPS1 powers at UPS1
Afterwards to bus 11 preset monitored duration, if the serial letter that UPS1 receives after the preset duration monitored terminates
Time number wrong, determine the signal sending time of control chip CC1 according to the mark of UPS1；If just receiving
After true serial signal, then sending, according to reception, the transmission comprised in the serial signal that chip TRC1 sends should
The mark of the UPS of serial signal and the mark of UPS1 determine the signal sending time of control chip CC1；
And at the signal sending time determined, send serial signal extremely by the ancillary equipment in control chip CC1
Receive and send chip TRC1, and sent chip by the ancillary equipment reception in control chip CC1 by reception
The serial signal that TRC1 sends.Bus 11 is monitored after UPS2 powers on by the control chip CC2 of UPS2
Preset duration, if monitor preset duration terminate after UPS2 receive serial signal mistake time, according to
The mark of UPS2 determines the signal sending time of control chip CC2；If after receiving correct serial signal,
Then according to receiving the UPS sending this serial signal of transmission comprised in the serial signal that chip TRC2 sends
Mark and the mark of UPS2 determine the signal sending time of control chip CC2；And send out at the signal determined
Send the time, send serial signal by the ancillary equipment in control chip CC2 and send chip TRC2 to reception,
And received by receiving the serial letter that transmission chip TRC2 sends by the ancillary equipment in control chip CC2
Number.The control chip CC3 of UPS3 after UPS3 powers on to bus 11 preset monitored duration, if monitor
Preset duration when terminating the serial signal mistake that rear UPS3 receives, determine control according to the mark of UPS3
The signal sending time of coremaking sheet CC3；If after receiving correct serial signal, then according to receiving transmission
The mark of the UPS sending this serial signal comprised in the serial signal that chip TRC3 sends is with UPS3's
Mark determines the signal sending time of control chip CC3；And at the signal sending time determined, by control
Ancillary equipment in coremaking sheet CC3 sends serial signal to reception and sends chip TRC3, and by controlling core
Ancillary equipment in sheet CC3 receives by receiving the serial signal that transmission chip TRC3 sends.
Each UPS in parallel system after the power-up, to bus monitoring a period of time, and will determine at prison
After not receiving signal in the time listened, the most just determine signal sending time according to the mark of self.So may be used
During to prevent from UPS parallel system has newly increased UPS, new UPS is i.e. had to join this UPS after powering on
In parallel system, new UPS mono-power on begin to send signal, thus in former parallel system
The signal of the UPS transmission sending signal interferes, and causes signal to send mistake.
If the multiple UPS in parallel system power on simultaneously, then when each UPS monitors bus one section
Between, if it is determined that after not receiving signal within the time monitored, system may there is multiple UPS send out simultaneously
The number of delivering letters, then the signal that each UPS in system receives is the logic fortune of the signal that multiple UPS sends
The signal obtained after calculation, the signal sent due to each UPS in system has verification, then in system
By check bit, each UPS upon receipt of the signals, can judge that the signal received is the most correct, owing to connecing
The signal received is the signal obtained after the logical operations of the signal that multiple UPS sends, and passes through check bit
May determine that the signal received is wrong.Now, each UPS in system start according to self
Mark determines signal sending time respectively.Each UPS in system determine monitor time in do not receive letter
After number, it is also possible to only one of which UPS sends signal, and now each UPS in system is upon receipt of the signals,
Mark and the mark of self according to the UPS sending this signal comprised in the signal received determine letter
Number send the time.
In practice, each UPS in parallel system can be made by hardware dial-up identification or additive method
Have and oneself uniquely identify.
It is possible to further the mark of each UPS in parallel system is arranged in order, the most each UPS's
The arrangement sequence number that mark is corresponding.Now, for the UPS, this UPS in UPS parallel system
Control chip after this UPS powers on to bus monitoring preset duration, and determine in the preset duration monitored
During the serial signal mistake received after end, determine what the time that the first delay duration terminates sent as signal
Initial time, the first delay duration be arrangement sequence number corresponding to the mark of the UPS that comprises this control chip with
The product of the time span set；If receiving correct serial signal, it is determined that the mark of this UPS is right
The arrangement sequence number corresponding to mark of the UPS comprised in the serial signal that the arrangement sequence number answered receives with this
Difference；If it is determined that difference be positive number, it is determined that the time that the second delay duration terminates sends as signal
Initial time, the second delay duration is the product of time span and the described difference set；If it is determined that difference
For non-positive number, it is determined that the initial time that the time that the 3rd delay duration terminates sends as signal, the 3rd prolongs
The quantity sum of the UPS in the most a length of described difference and parallel system and the time span of described setting
Product.
In concrete application scenarios 1, it is assumed that the arrangement serial number 1 of the mark correspondence of UPS1, the mark of UPS1
Know corresponding arrangement serial number 2, the arrangement serial number 3 that the mark of UPS3 is corresponding, the time span set as
T0。
As it is shown in figure 1, the control chip CC1 of UPS1 after UPS1 powers on to bus monitoring preset duration,
And when determining the serial signal mistake received after the preset duration monitored terminates, determine the first delay duration knot
The initial time that the time of bundle sends as signal, this first delay duration is the row of the mark correspondence of UPS1
The product of the time span of row sequence number and setting；Assume that control chip CC1 determines in the preset duration monitored
The serial signal mistake received after end, owing to the time span that sets is as T0, then control chip CC1 is true
The time that fixed first delay duration terminates is the initial time that signal sends, and the first delay duration is T0.Control
Coremaking sheet CC1 after receiving correct serial signal, determine arrangement sequence number corresponding to the mark of UPS1 and
The reception being connected with control chip CC1 sends the UPS's comprised in the serial signal that chip TRC1 sends
The difference of the arrangement sequence number that mark is corresponding；Assume the row of the mark correspondence of the UPS comprised in this serial signal
Row serial number 2, i.e. this serial signal are that UPS2 sends, then the difference that control chip CC1 determines is-1,
And determining the initial time that the time that the 3rd delay duration terminates sends as signal, the 3rd delay duration is institute
State the product of the difference quantity sum with the UPS in parallel system and the time span of setting, owing to setting
Time span be T0, the 3rd delay duration that control chip CC1 determines is 2*T0.
As it is shown in figure 1, the control chip CC2 of UPS2 after UPS2 powers on to bus monitoring preset duration,
And determine the serial signal mistake received after the preset duration monitored terminates；And determine monitor default time
During the serial signal mistake that length receives after terminating, determine that the time that the first delay duration terminates sends as signal
Initial time, this first delay duration is that the time of arrangement sequence number corresponding to the mark of UPS2 and setting is long
The product of degree；Assume the serial signal mistake that control chip CC2 receives after the preset duration monitored terminates,
Owing to the time span that sets is as T0, then the first delay duration that control chip CC2 determines is 2*T0.Control
Coremaking sheet CC2, after receiving correct serial signal, determines the arrangement sequence number that the mark of UPS2 is corresponding
With receiving of being connected with control chip CC2 sends the UPS comprised in the serial signal that chip TRC2 sends
The difference of arrangement sequence number corresponding to mark；The mark of the UPS assuming to comprise in this serial signal is corresponding
Arrangement serial number 2, i.e. this serial signal are that UPS2 sends, then the difference that control chip CC2 determines is
0, therefore control chip CC2 determines that the time that the 3rd delay duration terminates is the initial time that signal sends,
3rd delay duration be described difference with the quantity sum of the UPS in parallel system and described setting time
Between the product of length, owing to the time span set is as T0, then the 3rd time delay that control chip CC2 determines
Shi Changwei 3*T0.
As it is shown in figure 1, the control chip CC3 of UPS3 after UPS3 powers on to bus monitoring preset duration,
And when determining the serial signal mistake received after the preset duration monitored terminates, determine the first delay duration knot
The initial time that the time of bundle sends as signal, this first delay duration is the row of the mark correspondence of UPS3
The product of the time span of row sequence number and setting；Assume that control chip CC3 determines in the preset duration monitored
The serial signal mistake received after end, owing to the time span that sets is as T0, then control chip CC3 is true
The first fixed delay duration is 3*T0.Control chip CC3 is after receiving correct serial signal, really
Arrangement sequence number and the reception being connected with control chip CC3 of determining the mark correspondence of UPS3 send chip TRC3
The difference of the arrangement sequence number of the mark correspondence of the UPS comprised in the serial signal sent；Assume that this serial is believed
The arrangement serial number 2 of the mark correspondence of the UPS comprised in number, i.e. this serial signal are that UPS2 sends,
The difference that then control chip CC3 determines is 1, and therefore, control chip CC3 determines the second delay duration knot
The initial time that the time of bundle sends as signal, the second delay duration is the time span and described difference set
The product of value, owing to the time span set is as T0, then the 3rd delay duration that control chip CC3 determines
For T0.
In actual applications, hardware dial-up identification or additive method can be passed through by UPS parallel system
The mark of each UPS be set to numeral, these numerals are arranged in order.Such as, at concrete application scenarios one
In, the mark of UPS1 is set to 1, the mark of UPS2 is set to 2, the mark in UPS3 is set
It is set to 3, now can determine the letter of each UPS not in use by the arrangement sequence number that the mark of each UPS is corresponding
Number send the time, and directly use the mark of each UPS to determine the signal sending time of each UPS.
Further, the control core of each UPS in a kind of UPS parallel system that the embodiment of the present invention provides
Ancillary equipment in sheet is serial communication interface (SCI, Serial Communication Interface) equipment.
Further, the control core of each UPS in a kind of UPS parallel system that the embodiment of the present invention provides
Ancillary equipment in sheet is asynchronous serial communication interface (UART, Universal Asynchronous
Receiver-Transmitter) equipment.
Further, the control core of each UPS in a kind of UPS parallel system that the embodiment of the present invention provides
Ancillary equipment in sheet is local interconnect network interface (LIN, Local Interconnect Network) equipment
The embodiment of the present invention additionally provides the method for transmitting signals of a kind of UPS parallel system, and this signal transmits
Method can apply to the UPS parallel system that the aforesaid embodiment of the present invention provides, the method and aforementioned UPS
Repeat no more in place of the repetition of parallel system.
For any one UPS in parallel UPS system, a kind of UPS that the embodiment of the present invention provides is also
The method for transmitting signals of contact system, as in figure 2 it is shown, include:
Control chip in S201, this UPS determines signal sending time according to the mark of this UPS self；
Control chip in S202, this UPS, at the signal sending time determined, is set by the periphery of self
Preparation send serial signal to send chip to the reception in this UPS；
Receiving in S203, this UPS sends the serial that the control chip from this UPS is received by chip
Signal carries out logical operations with the signal in bus；
Receiving in S204, this UPS send chip by the signal that obtains after logical operations by described always
Line sends to each UPS in parallel system；
Receiving in S205, this UPS sends chip and the signal received in described bus is converted into string
Row signal；
Receiving in S206, this UPS sends chip and the serial signal converted is sent the control to this UPS
Coremaking sheet；
The reception that control chip in S207, this UPS is received in this UPS by the ancillary equipment of self is sent out
Send the serial signal that chip is sent.
Wherein, S201～S204 and S205～S207 there is no temporal sequencing, can first carry out
S201～S204, it is also possible to first carry out S205～S207, it is also possible to S201～S204 and S205～S207 is simultaneously
Perform.
Further, for any one UPS in parallel UPS system, in this UPS in S201
Control chip determines signal sending time according to the mark of this UPS self, as it is shown on figure 3, specifically include:
S2011, after this UPS powers on to bus monitoring preset duration；
When S2012, the serial signal mistake that this UPS receives after the preset duration monitored terminates, according to bag
Mark containing the UPS of described control chip determines signal sending time；
S2013, after receiving correct serial signal, then according to the reception that is connected with described control chip
Send the mark of the UPS sending this signal comprised in the serial signal that chip is sent and comprise described control
The mark of the UPS of chip, determines the signal sending time of described control chip.
Wherein, S2013 receives correct serial signal, can be to terminate in the preset duration monitored
After receive correct serial signal, it is also possible to be monitor preset duration in receive correct serial signal.
It is to say, S2013 and S2011 the most directly contact, S2011 and S2012 is only at this UPS
Just performing when just powering on, S2013 both can perform when this UPS just powers on, it is also possible in parallel system
Each UPS proceed-to-send signal in turn after perform.
Further, for any one UPS in parallel UPS system, in S2012 according to this UPS
The mark of self determines signal sending time, specifically includes:
The product of the arrangement sequence number determining the mark correspondence of this UPS and the time span set is as the first time delay
Duration, the initial time that the time the first delay duration terminated sends as signal.
Further, S2013 receives, according to be connected with described control chip, the serial that transmission chip is sent
The mark of UPS sending this signal comprised in signal and the mark of the UPS comprising described control chip,
Determine the signal sending time of described control chip, specifically include:
Determine that the arrangement sequence number of the mark correspondence of the UPS comprising described control chip connects with described control chip
The difference of the arrangement sequence number of the mark correspondence of the UPS comprised in the serial signal received；
If it is determined that difference be positive number, it is determined that the time that the second delay duration terminates as signal send rise
Time beginning, the second delay duration is the product of time span and the described difference set；
If it is determined that difference be non-positive number, it is determined that the time that the 3rd delay duration terminates sends as signal
Initial time, the 3rd delay duration is that the described difference quantity sum with the UPS in parallel system is with described
The product of the time span set.
The invention described above embodiment sequence number, just to describing, does not represent the quality of embodiment.
Obviously, those skilled in the art can carry out various change and modification without deviating from this to the present invention
Bright spirit and scope.So, if the present invention these amendment and modification belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprise these change and modification.
Claims (7)
1. a UPS parallel system, including multiple UPS in parallel and bus, it is characterised in that each
UPS comprises a control chip and receives transmission chip；
Control chip in each UPS connects the reception in this UPS and sends chip, connecing in each UPS
Transmit and receive chip and be all connected with described bus；
Control chip in each UPS, at signal sending time, outside in this control chip
Peripheral equipment sends serial signal and sends chip to the reception in this UPS, and by this control chip
Ancillary equipment receives receiving in this UPS and sends the serial signal that chip is sent；Described signal sending time
Mark according to this UPS self determines；Specifically for: after the UPS comprising described control chip powers on
To described bus monitoring preset duration, if the serial letter that this UPS receives after the preset duration monitored terminates
Time number wrong, determine signal sending time according to the mark of the UPS comprising described control chip, receiving
After correct serial signal, then receive, according to be connected with described control chip, the serial that transmission chip is sent
The mark of UPS sending this correct serial signal that comprises in signal and comprise described control chip
The mark of UPS, determines the signal sending time of described control chip；
Reception in each UPS sends chip, for the string received by the control chip from this UPS
Row signal and the signal in bus carry out logical operations, and pass through described by the signal obtained after logical operations
Bus sends to each UPS in parallel system, and the signal received in described bus is converted into string
Row signal sends the control chip to this UPS.
2. the system as claimed in claim 1, it is characterised in that described control chip specifically for:
To described bus monitoring preset duration after the UPS comprising described control chip powers on, and monitoring
Preset duration terminate after receive serial signal mistake time, determine the time conduct that the first delay duration terminates
The initial time that signal sends, described first delay duration is the mark of the UPS comprising described control chip
Corresponding arrangement sequence number and the product of the time span of setting；
After receiving correct serial signal, determine that the mark of the UPS comprising described control chip is corresponding
Arrangement sequence number and receiving of being connected with described control chip send and the serial signal sent of chip comprise
The difference of the arrangement sequence number of the mark correspondence of UPS；If it is determined that difference be positive number, it is determined that during the second time delay
The initial time that the long time terminated sends as signal, described second delay duration is the time span set
Product with described difference；If it is determined that difference be non-positive number, it is determined that the time that the 3rd delay duration terminates
The initial time sent as signal, described 3rd delay duration is described difference and the UPS in parallel system
Quantity sum again with the product of the time span of described setting.
3. the system as described in as arbitrary in claim 1～2, it is characterised in that outside in described control chip
Peripheral equipment be serial communication interface SCI equipment or asynchronous serial communication interface UART equipment or local mutual
Network interface LIN equipment.
4. the system as described in as arbitrary in claim 1～2, it is characterised in that described reception sends chip and is
The serial signal received by control chip from this UPS carries out logic and operation with the signal in bus
Or the reception carrying out logic or computing sends chip.
5. the method for transmitting signals of a UPS parallel system, it is characterised in that including:
The control chip in each UPS in parallel system is at signal sending time, by this control chip
In ancillary equipment send serial signal to the reception in this UPS and send chip, and by this control core
Ancillary equipment in sheet receives receiving in this UPS and sends the serial signal that chip is sent；Described signal is sent out
The time is sent to determine according to the mark of this UPS self；Described signal sending time is the most true
Fixed: to bus monitoring preset duration after the UPS comprising described control chip powers on and pre-monitor
If duration terminate after this UPS receive serial signal mistake time, according to the UPS comprising described control chip
Mark determine signal sending time；After receiving correct serial signal, then basis and described control core
This correct serial signal of transmission comprised in the serial signal that the reception transmission chip that sheet connects is sent
The mark of UPS and comprise the mark of UPS of described control chip, determines that the signal of described control chip is sent out
Send the time；
Receiving in each UPS in parallel system sends chip and is received by the control chip from this UPS
To serial signal and bus on signal carry out logical operations, and the signal obtained after logical operations is led to
Cross described bus to send to each UPS in parallel system, and the signal received in described bus is turned
Turn to serial signal and send the control chip to this UPS.
6. method as claimed in claim 5, it is characterised in that described basis comprises described control chip
The mark of UPS determine signal sending time, specifically include:
Determine arrangement sequence number and the time span of setting of the mark correspondence of the UPS comprising described control chip
Product be the first delay duration, the time that the first delay duration is terminated as signal send initial time
Between.
7. method as claimed in claim 5, it is characterised in that described basis is with described control chip even
Receiving of connecing sends the mark of the UPS sending this signal comprised in the serial signal that chip is sent and comprises
The mark of the UPS of described control chip, determines the signal sending time of described control chip, specifically includes:
Determine that the arrangement sequence number of the mark correspondence of the UPS comprising described control chip connects with described control chip
The difference of the arrangement sequence number of the mark correspondence of the UPS comprised in the serial signal received；
If it is determined that difference be positive number, it is determined that the time that the second delay duration terminates as signal send rise
Time beginning, described second delay duration is the product of time span and the described difference set；
If it is determined that difference be non-positive number, it is determined that the time that the 3rd delay duration terminates sends as signal
Initial time, described 3rd delay duration is described difference with the quantity sum of the UPS in parallel system again
Product with the time span of described setting.
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| CN101312302A (en) * | 2007-05-24 | 2008-11-26 | 力博特公司 | Parallel signal transmission method of uninterrupted power source |
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| US20050043859A1 (en) * | 2003-08-13 | 2005-02-24 | Chia-Ming Tsai | Modular uninterruptible power supply system and control method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101312302A (en) * | 2007-05-24 | 2008-11-26 | 力博特公司 | Parallel signal transmission method of uninterrupted power source |
Non-Patent Citations (1)
| Title |
|---|
| CAN总线通信技术在UPS中的应用;李尊;《中国优秀硕士论文全文数据库》;20120831;正文第6-41页 * |
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