CN104078415A - Method for manufacturing interconnecting structures - Google Patents
Method for manufacturing interconnecting structures Download PDFInfo
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- CN104078415A CN104078415A CN201310105947.4A CN201310105947A CN104078415A CN 104078415 A CN104078415 A CN 104078415A CN 201310105947 A CN201310105947 A CN 201310105947A CN 104078415 A CN104078415 A CN 104078415A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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Abstract
A method for manufacturing interconnecting structures comprises the steps that a substrate is provided, an interlevel dielectric layer with a first opening is arranged on the substrate, the first opening is filled with a conductive layer to form a first interconnecting structure, the conductive layer is subjected to chemical mechanical polishing until the interlevel dielectric layer, and chemical mechanical polishing residues are formed on the surface of the interlevel dielectric layer; the interlevel dielectric layer is subjected to ultraviolet processing to remove the residues on the surface of the interlevel dielectric layer; after the interlevel dielectric layer is subjected to ultraviolet processing, a porous medium layer is formed on the interlevel dielectric layer; a graphical hard mask layer is formed on the porous medium layer, the porous medium layer is etched with the graphical hard mask layer as a mask, a second opening is formed in the porous medium layer and is communicated with the first opening, and the second opening is filled with a conductive layer to form a second interconnecting structure. The method can improve the electric connection effect of the interconnecting structures, and improve electric connection reliability of the interconnecting structures.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of manufacture method of interconnection structure.
Background technology
The challenge that integrated circuit (IC) design and manufacture field run into is now how to reduce signal transmission RC to postpone (Resistive Capacitive delay), to this, a kind of method that technology has adopted is now that aluminum metal layer is replaced with to copper metal layer, reduces metal level series resistance; Also having a kind of method is the parasitic capacitance reducing between metal level, and this can realize by constructing (Porous) low-k (Low K) material or the air-gap (Air Gap) of porous in the dielectric layer between metal level.
At publication number, be US7279427B2, in the american documentation literature that open day is on October 9th, 2007, can also find more to adopt porous low-K dielectric layer to manufacture the information of interconnection structure.
The manufacture method of a kind of interconnection structure of the prior art is: with reference to figure 1, substrate 100 is provided, in substrate 100, form interlayer dielectric layer 101, on this interlayer dielectric layer 101, form patterned mask layer (not shown), take described patterned mask layer as mask etching interlayer dielectric layer 101, at interior formation the first through hole of interlayer dielectric layer 101, plated metal copper layer in the first through hole, then adopt the method for chemico-mechanical polishing that metal copper layer is planarized to interlayer dielectric layer 101, at the interior formation conductive plunger 102 of interlayer dielectric layer 101.
In conjunction with reference to figure 1 and Fig. 2, be formed with metallization medium layer 103 ' on the interlayer dielectric layer 101 of conductive plunger 102, the method that then adopts ultraviolet ray 105 to process becomes dielectric layer 103 ' into porous low-K dielectric layer 103.Then on porous low-K dielectric layer 103, form hard mask layer 104, material is tetraethoxysilane.
In conjunction with referring to figs. 2 and 3, then on hard mask layer 104, form patterned photoresist (not shown), take patterned photoresist as mask etching hard mask layer 104, form patterned hard mask layer, then, take patterned hard mask layer as mask etching porous low-K dielectric layer 103, and at interior formation the second through hole of porous low-K dielectric layer 103, described the second via bottoms communicates with the first through hole; Filled conductive layer in described the second through hole, forms conductive plunger 108.
Yet it is poor that the interconnection structure forming in prior art is electrically connected effect, affect the performance of the semiconductor device of follow-up formation.
Summary of the invention
The technical problem that the present invention solves is that the interconnection structure electric connection effect forming in prior art is poor, affects the performance of the semiconductor device of follow-up formation.
For addressing the above problem, the present invention proposes a kind of manufacture method of interconnection structure, comprising:
Substrate is provided, in described substrate, form the interlayer dielectric layer with the first opening, in described the first opening, filled conductive layer forms the first interconnection structure, described conductive layer is chemically mechanically polished to described interlayer dielectric layer, and described interlayer dielectric layer surface has chemico-mechanical polishing residue;
Described interlayer dielectric layer is carried out to UV treatment, remove the described residue on described interlayer dielectric layer surface;
Described interlayer dielectric layer is carried out, after UV treatment, on described interlayer dielectric layer, forming porous medium layer;
On described porous medium layer, form graphical hard mask layer, take described patterned hard mask layer as porous medium layer described in mask etching, in porous medium layer, form the second opening, described the second opening communicates with the first opening, and in described the second opening, filled conductive layer forms the second interconnection structure.
The method of optionally, described interlayer dielectric layer being carried out to UV treatment comprises:
With ultraviolet ray, irradiate described interlayer dielectric layer, described ultraviolet wavelength is 200nm～400nm, and the power of ultraviolet irradiation device is 50W～100W, and ultraviolet ray is 63s～77s to the irradiation time of described interlayer dielectric layer.
Optionally, after described interlayer dielectric layer being carried out to the step of UV treatment, on described interlayer dielectric layer, form and also comprise step before the step of porous medium layer:
Described interlayer dielectric layer is carried out to ozone treatment.
Optionally, described interlayer dielectric layer is carried out to ozone treatment and in chamber, carry out, design parameter comprises: chamber pressure is 0.5torr～7torr, and the flow of ozone gas is 50sccm～1500sccm, the time of processing is 25s～100s, and chamber power is 100W～1000W.
Optionally, the described method that forms porous medium layer on described interlayer dielectric layer comprises:
On described interlayer dielectric layer, form dielectric layer;
Described dielectric layer is carried out to UV treatment, form porous medium layer.
Optionally, the described method that described dielectric layer is carried out to UV treatment comprises:
Adopt ultraviolet ray to irradiate described dielectric layer, ultraviolet wave-length coverage is 200nm～400nm, and the power of ultraviolet irradiation device is 50W～100W, and ultraviolet ray is 63s～77s to the irradiation time of described dielectric layer.
Optionally, described the first opening comprises at least one in through hole or groove.
Optionally, described conductive layer is copper or tungsten.
Optionally, described interlayer dielectric layer is carried out after ozone treatment, form porous medium layer on described interlayer dielectric layer before, also comprise step: on described interlayer dielectric layer surface, form barrier layer, described barrier layer is for preventing the conductive layer diffusion of described interlayer dielectric layer.
Optionally, the carborundum that described barrier layer is nitrating.
Optionally, described interlayer dielectric layer is individual layer or laminated construction, and when described interlayer dielectric layer is single layer structure, the material of described interlayer dielectric layer is SiO
2, a kind of in SiOF, SiCOH, SiO, SiCO, SiCON; When described interlayer dielectric layer is laminated construction, described interlayer dielectric layer is SiO
2, SiOF, SiCOH, SiO, SiCO, SiCON layer combination in any laminated construction.
Optionally, described porous medium layer is individual layer or laminated construction, and when described porous medium layer is single layer structure, the material of described porous medium layer is SiO
2, a kind of in SiOF, SiCOH, SiO, SiCO, SiCON; When described porous medium layer is laminated construction, the material of described porous medium layer is SiO
2, SiOF, SiCOH, SiO, SiCO, SiCON layer combination in any laminated construction.
Optionally, described hard mask layer is single layer structure or laminated construction, and when hard mask layer is single layer structure, the material of described hard mask layer is SiCOH; When hard mask layer is double-decker, described hard mask layer primer is SiCOH, and quilting material is tetraethoxysilane.
Compared with prior art, technical scheme of the present invention has the following advantages:
The present invention forms the interlayer dielectric layer with the first opening in substrate, filled conductive layer in described the first opening, described conductive layer is chemically mechanically polished to described interlayer dielectric layer, described interlayer dielectric layer surface has chemico-mechanical polishing residue, with ultraviolet ray, interlayer dielectric layer is processed, make the removing residues on interlayer dielectric layer surface clean, be specially, ultraviolet frequency is identical with the vibration frequency of residue, the energy that ultraviolet ray produces makes the chemical bond rupture in residue, the heat that ultraviolet ray produces can make the residue volatilization of chemical bond rupture.Directly after forming interlayer dielectric layer, remove residue, make after follow-up porous low-K dielectric layer forms, avoid this residue to enter and rest in the hard mask layer of follow-up formation through porous low-K dielectric layer,, avoid the inside of hard mask layer to produce hole, avoid the upper surface of hard mask layer to produce bulge defect.Follow-uply can on this hard mask layer, form smooth patterned photoresist, then, form accurate patterned hard mask layer, take described patterned hard mask layer as porous medium layer described in mask etching, in porous medium layer, form the second opening, described the second open bottom communicates with the first opening, filled conductive layer in described the second opening.In above-mentioned steps, the present invention can form the second high opening figure of accuracy in the inside of porous medium layer, and then the conductive plunger forming in raising porous medium layer or the accuracy of shape of interconnection line, improve the electrical connection effect of the interconnection structure of follow-up formation, improved interconnection structure and be electrically connected reliability.
Accompanying drawing explanation
Fig. 1 to Fig. 3 is the schematic diagram of the manufacture method of interconnection structure in prior art;
Fig. 4 is the schematic flow sheet of interconnection structure manufacture method of the present invention;
Fig. 5 to Figure 10 is the cross-sectional view of interconnection structure manufacture method one embodiment of the present invention.
Embodiment
Inventor finds and analyzes, and it is poor that the interconnection structure forming in prior art is electrically connected effect, affect follow-up formation semiconductor device performance former because:
In conjunction with reference to figure 1 and Fig. 2, adopt the method for chemico-mechanical polishing that metal copper layer is planarized to after interlayer dielectric layer 101, can form residue on the surface of interlayer dielectric layer 101, described residue is mainly after CMP (Chemical Mechanical Polishing) process finishes, polishing fluid does not clean up and produces, this residue is organic residue, more difficult cleaning up in actual process.When the method that adopts ultraviolet ray 105 to process becomes dielectric layer 103 ' after porous low-K dielectric layer 103, need to form at once hard mask layer 104 on the surface of porous low-K dielectric layer.Reason is as follows: porous low-K dielectric layer is porous material, easily water suction, and therefore, oversize if porous low-K dielectric layer exposes in air, airborne moisture can enter in the hole of porous low-K dielectric layer, causes the dielectric constant of porous low-K dielectric layer to increase.But, in prior art, form in the process of porous low-K dielectric layer 103, the energy that ultraviolet ray 105 produces makes the chemical bond rupture in residue, and the heat that ultraviolet ray produces can make the residue volatilization of chemical bond rupture, the residue of volatilization is easy to through the porous low-K dielectric layer 103 having formed, and rest in fine and close hard mask layer 104, make the inside of hard mask layer 104 produce hole 106, the hole 106 adjacent with hard mask layer 104 upper surfaces can make the upper surface of hard mask layer 104 produce bulge defect 107(bump defects).
In conjunction with referring to figs. 2 and 3, bulge defect 107 makes the upper surface out-of-flatness of hard mask layer 104, follow-up while forming patterned photoresist on hard mask layer 104, the patterned photoresist of formation also can out-of-flatness.In prior art, figure on this photoresist is transferred on hard mask layer 104, and the figure of hard mask layer 104 is continued to be transferred in the process of porous low-K dielectric layer 103, can make the shape of the second through hole in porous low-K dielectric layer 103 bad, accuracy is not high, and the follow-up connector shape forming in porous low-K dielectric layer 103 is also bad, thereby can affect the electrical connection effect of the interconnection structure of follow-up formation, more seriously, cannot realize conducting of interconnection structure.
Correspondingly, inventor provides a kind of manufacture method of interconnection structure, and Fig. 4 is the schematic flow sheet of interconnection structure manufacture method of the present invention, and Fig. 5 to Figure 10 is the cross-sectional view of interconnection structure manufacture method one embodiment of the present invention.Below Fig. 5 to Figure 10 and Fig. 4 are combined the manufacture method of interconnection structure of the present invention is elaborated.
First with reference to figure 5, step S11 in execution graph 4, substrate 200 is provided, in described substrate 200, form the interlayer dielectric layer 201 with the first opening, in described the first opening, filled conductive layer forms the first interconnection structure, described conductive layer is chemically mechanically polished to described interlayer dielectric layer 201, and described interlayer dielectric layer 201 surfaces have chemico-mechanical polishing residue 203.
In the present embodiment, described substrate 200 comprises: the basalis (not shown) that is formed with the semiconductor elements such as transistor, be formed at the metal level (not shown) on basalis, wherein said metal level is realized and being electrically connected to of other devices for the interconnection structure that forms by the present embodiment.Particularly, the material of metal level is copper or aluminium.In other embodiments, described substrate also can be only for being formed with the basalis of the semiconductor elements such as transistor.
Adopt the method for deposition in substrate, to form interlayer dielectric layer 201, interlayer dielectric layer 201 can be individual layer or laminated construction.When described interlayer dielectric layer is single layer structure, the material of this interlayer dielectric layer is a kind of in SiO2, SiOF, SiCOH, SiO, SiCO, SiCON; When interlayer dielectric layer is laminated construction, this interlayer dielectric layer be the laminated construction of SiO2, SiOF, SiCOH, SiO, SiCO, SiCON layer combination in any.
Form after interlayer dielectric layer 201, on interlayer dielectric layer 201, form patterned mask layer (not shown), then take patterned mask layer as mask etching interlayer dielectric layer 201, at interior formation the first opening of interlayer dielectric layer 201, described the first opening comprises at least one in through hole or groove.In the present embodiment, described patterned mask layer is photoresist, and described the first opening is through hole.Then, depositing conducting layer in through hole, is planarized to interlayer dielectric layer 201 to described conductive layer, therefore, and at the inner conductive plunger 202 that forms of interlayer dielectric layer 201.In the present embodiment, the material of conductive layer is metallic copper.In other embodiments, described the first opening can be also groove, and depositing conducting layer in this groove, is planarized to interlayer dielectric layer 201 to described conductive layer, in the inside of interlayer dielectric layer 201, forms interconnection line.Certainly, in other embodiments, also can form conductive plunger and interconnection line in the inside of interlayer dielectric layer 201 simultaneously.
In the present embodiment, the concrete technology of planarization is chemico-mechanical polishing.After the inner formation conductive plunger 202 of interlayer dielectric layer 201, can form on the surface of interlayer dielectric layer 201 chemico-mechanical polishing residue 203(hereafter residue 203), this residue 203 is mainly after CMP (Chemical Mechanical Polishing) process finishes, polishing fluid does not clean up and produces, and this residue 203 is organic residue.
Then,, with reference to figure 5 and Fig. 6, the step S12 in execution graph 4, carries out ultraviolet ray 204 to described interlayer dielectric layer 201 and processes, and removes the described residue 203 on described interlayer dielectric layer 201 surfaces.Be specially:
In the present embodiment, with ultraviolet ray 204, irradiate interlayer dielectric layer 201 and carry out in chamber.Ultraviolet wavelength is 200nm～400nm, and the power of ultraviolet irradiation device is 50W～100W, and ultraviolet ray is 63s～77s to the irradiation time of interlayer dielectric layer 201.With ultraviolet ray 204, irradiate in the process of interlayer dielectric layer 201, the frequency of ultraviolet ray 204 is identical with the vibration frequency of residue 203, the energy that ultraviolet ray 204 produces makes the chemical bond rupture in residue 203, and the heat that ultraviolet ray 204 produces can make the residue volatilization of chemical bond rupture.Therefore, in the present embodiment, adopt ultraviolet ray 204 to irradiate after interlayer dielectric layer 201, can directly the residue on interlayer dielectric layer 201 surfaces 203 be removed.
In the present embodiment, form after interlayer dielectric layer 201, with 204 pairs of interlayer dielectric layers 201 of ultraviolet ray, process, the residue 203 on interlayer dielectric layer 201 surfaces is removed, avoid after follow-up porous low-K dielectric layer forms, this residue 203, through the porous low-K dielectric layer of follow-up formation, enters and rests in the hard mask layer of follow-up formation, thereby avoid the inside of hard mask layer to produce hole, and then avoid the upper surface of hard mask layer to produce bulge defect.
With reference to figure 7, in the present embodiment, interlayer dielectric layer 201 is carried out after UV treatment, also interlayer dielectric layer 201 is carried out to ozone 205 and process, further remove the residue 203 that interlayer dielectric layer 201 surfaces are not cleaned out.
Interlayer dielectric layer 201 is carried out to ozone 205 processing and in chamber, carry out, the oxygen composition in ozone 205 reacts with the carbon component in organic residue and generates volatile carbon dioxide, further to remove this residue 203.Design parameter comprises: chamber pressure is 0.5torr～7torr, and the flow of ozone 205 is 50sccm～1500sccm, and the time of processing is 25s～100s, and chamber power is 100W～1000W.In the present embodiment, can in the chamber of UV treatment, to described interlayer dielectric layer 201, carry out ozone 205 processing of original position.
It should be noted that, by original position mode, carry out ozone treatment, the step of described ozone treatment can realize good integrated with existing equipment, in addition, when carrying out ozone treatment without interconnection structure to be formed is moved in other chambers from the chamber of UV treatment, can reduce processing step, simplify technique.But the present invention is not restricted this, in other embodiments, can also in the chamber of UV treatment, carry out the ozone treatment of original position, but in another reaction chamber, carry out described ozone treatment.
In other embodiments, interlayer dielectric layer 201 is carried out after UV treatment, can interlayer dielectric layer 201 not carried out to ozone treatment, also can realize the present invention, just remove the poor effect of residue 203.
Then, in the present embodiment, interlayer dielectric layer 201 is carried out after ozone treatment, on formation barrier layer, the surface of interlayer dielectric layer 201.Described barrier layer is on the one hand for preventing the conductive layer diffusion of interlayer dielectric layer 201, can also increase the adhesiveness of the porous low-K dielectric layer of conductive layer in interlayer dielectric layer 201 and follow-up formation simultaneously.The material on described barrier layer is the carborundum (Nitrogen Doped Silicon Carbon, NDC) of nitrating.But the present invention is not restricted the material on barrier layer.
In other embodiments, interlayer dielectric layer 201 is carried out after ozone treatment, on the surface of interlayer dielectric layer 201, do not form barrier layer, also can realize the present invention.
Then,, with reference to figure 8 and Fig. 9, the step S13 in execution graph 4, carries out, after ultraviolet ray 204 processing, on described interlayer dielectric layer 201, forming porous medium layer 206 to described interlayer dielectric layer 201.
First with reference to figure 8, in the present embodiment, on described interlayer dielectric layer 201, by diethoxymethyl silane and ATRP, form described dielectric layer 206 '.Particularly, can form by the mode of collosol and gel described dielectric layer 206 '.But the present invention is not restricted the material of dielectric layer 206 ', the generation type of dielectric layer 206 ' is not restricted yet.The material of dielectric layer 206 ' described herein can also be one or more in SiO2, SiOF, SiCOH, SiO, SiCO, SiCON, carbonado.In other embodiments, can also deposit by the mode of chemical vapour deposition (CVD) described dielectric layer 206 '.Be specially: described dielectric layer 206 ' can be single or multiple lift structure, when dielectric layer 206 ' is single layer structure, described dielectric layer 206 ' is a kind of in SiO2, SiOF, SiCOH, SiO, SiCO, SiCON; When dielectric layer 206 ' is laminated construction, described dielectric layer 206 ' is the laminated construction of SiO2, SiOF, SiCOH, SiO, SiCO, SiCON middle level combination in any.
In conjunction with reference to figure 8 and Fig. 9, form after dielectric layer 206 ', dielectric layer 206 ' is carried out to ultraviolet ray 204 and process, to form porous medium layer 206.Particularly, by the auxiliary heat of ultraviolet ray 204, process and can in dielectric layer 206 ', form loose structure, to form porous medium layer 206.In the present embodiment, the design parameter that dielectric layer 206 ' is carried out to UV treatment is, ultraviolet wave-length coverage is 200nm～400nm, and the power of ultraviolet irradiation device is 50W～100W, and ultraviolet ray is 63s～77s to the irradiation time of described dielectric layer.
Then, continuation is with reference to figure 9, step S14 in execution graph 3, on described porous medium layer 206, form graphical hard mask layer 207, take described patterned hard mask layer 207 as porous medium layer described in mask etching 206, at interior formation the second opening of porous medium layer 206, described the second opening communicates with the first opening, and in described the second opening, filled conductive layer forms the second interconnection structure.
To form after porous medium layer 206, in order not making porous medium layer 206 be exposed to for a long time to absorb moisture in air, the dielectric constant of porous medium layer 206 to be increased, need to after forming porous medium layer 206, form at once hard mask layer 207.The formation method of hard mask layer 207 is deposition.Hard mask layer 207 can be single layer structure or laminated construction, and when hard mask layer is single layer structure, the material of hard mask layer 207 is SiCOH; When hard mask layer 207 is double-decker, hard mask layer 207 primers are SiCOH, and quilting material is tetraethoxysilane.But the present invention is not restricted this, can form according to concrete structure the hard mask layer of different layers in other embodiments.
The present invention, form after interlayer dielectric layer 201, with ultraviolet ray, interlayer dielectric layer 201 is processed, make the residue 203 on interlayer dielectric layer 201 surfaces remove clean, then at the surface deposition porous medium layer 206 of interlayer dielectric layer 201, surface deposition hard mask layer 207 at porous medium layer 206, the surface of the hard mask layer 207 forming does not have bulge defect, smooth, follow-uply can on hard mask layer 207, form smooth patterned photoresist, then, take smooth patterned photoresist as the patterned hard mask layer 207 of mask etching hard mask layer 207 formation, with reference to Figure 10, take described patterned hard mask layer 207 as porous medium layer described in mask etching 206 again, in porous medium layer, form the second opening, described the second opening communicates with the first opening, filled conductive layer in described the second opening, form the second interconnection structure 208.In the present embodiment, described the second opening is through hole, and the second interconnection structure is conductive plunger.In other embodiments, described the second opening can be groove, and depositing conducting layer in this groove, is planarized to porous medium layer 206 to described conductive layer, at the inner interconnection line that forms of porous medium layer 206.Certainly, in other embodiments, also can form conductive plunger or interconnection line in the inside of porous medium layer simultaneously.Therefore the present invention can form the second high opening figure of accuracy in the inside of porous medium layer 206, and then the conductive plunger of raising porous medium layer 206 interior formation or the accuracy of shape of interconnection line, improve the electrical connection effect of the interconnection structure of follow-up formation, improved interconnection structure and be electrically connected reliability.
The above, be only preferred embodiment of the present invention, not the present invention done to any pro forma restriction.Any those of ordinary skill in the art, are not departing from technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (13)
1. a manufacture method for interconnection structure, is characterized in that, comprising:
Substrate is provided, in described substrate, form the interlayer dielectric layer with the first opening, in described the first opening, filled conductive layer forms the first interconnection structure, described conductive layer is chemically mechanically polished to described interlayer dielectric layer, and described interlayer dielectric layer surface has chemico-mechanical polishing residue;
Described interlayer dielectric layer is carried out to UV treatment, remove the described residue on described interlayer dielectric layer surface;
Described interlayer dielectric layer is carried out, after UV treatment, on described interlayer dielectric layer, forming porous medium layer;
On described porous medium layer, form graphical hard mask layer, take described patterned hard mask layer as porous medium layer described in mask etching, in porous medium layer, form the second opening, described the second opening communicates with the first opening, and in described the second opening, filled conductive layer forms the second interconnection structure.
2. the manufacture method of interconnection structure as claimed in claim 1, is characterized in that, the method for described interlayer dielectric layer being carried out to UV treatment comprises:
With ultraviolet ray, irradiate described interlayer dielectric layer, described ultraviolet wavelength is 200nm～400nm, and the power of ultraviolet irradiation device is 50W～100W, and ultraviolet ray is 63s～77s to the irradiation time of described interlayer dielectric layer.
3. the manufacture method of interconnection structure as claimed in claim 1, is characterized in that, after described interlayer dielectric layer being carried out to the step of UV treatment, forms and also comprise step before the step of porous medium layer on described interlayer dielectric layer:
Described interlayer dielectric layer is carried out to ozone treatment.
4. the manufacture method of interconnection structure as claimed in claim 3, it is characterized in that, described interlayer dielectric layer is carried out to ozone treatment to carry out in chamber, design parameter comprises: chamber pressure is 0.5torr～7torr, the flow of ozone gas is 50sccm～1500sccm, the time of processing is 25s～100s, and chamber power is 100W～1000W.
5. the manufacture method of interconnection structure as claimed in claim 1, is characterized in that, the described method that forms porous medium layer on described interlayer dielectric layer comprises:
On described interlayer dielectric layer, form dielectric layer;
Described dielectric layer is carried out to UV treatment, form porous medium layer.
6. the manufacture method of interconnection structure as claimed in claim 5, is characterized in that, the described method that described dielectric layer is carried out to UV treatment comprises:
Adopt ultraviolet ray to irradiate described dielectric layer, ultraviolet wave-length coverage is 200nm～400nm, and the power of ultraviolet irradiation device is 50W～100W, and ultraviolet ray is 63s～77s to the irradiation time of described dielectric layer.
7. the manufacture method of interconnection structure as claimed in claim 1, is characterized in that, described the first opening comprises at least one in through hole or groove.
8. the manufacture method of interconnection structure as claimed in claim 1, is characterized in that, described conductive layer is copper or tungsten.
9. the manufacture method of interconnection structure as claimed in claim 3, it is characterized in that, described interlayer dielectric layer is carried out after ozone treatment, form porous medium layer on described interlayer dielectric layer before, also comprise step: on described interlayer dielectric layer surface, form barrier layer, described barrier layer is for preventing the conductive layer diffusion of described interlayer dielectric layer.
10. the manufacture method of interconnection structure as claimed in claim 9, is characterized in that, the carborundum that described barrier layer is nitrating.
The manufacture method of 11. interconnection structures as claimed in claim 1, is characterized in that, described interlayer dielectric layer is individual layer or laminated construction, and when described interlayer dielectric layer is single layer structure, the material of described interlayer dielectric layer is SiO
2, a kind of in SiOF, SiCOH, SiO, SiCO, SiCON; When described interlayer dielectric layer is laminated construction, described interlayer dielectric layer is SiO
2, SiOF, SiCOH, SiO, SiCO, SiCON layer combination in any laminated construction.
The manufacture method of 12. interconnection structures as claimed in claim 1, is characterized in that, described porous medium layer is individual layer or laminated construction, and when described porous medium layer is single layer structure, the material of described porous medium layer is SiO
2, a kind of in SiOF, SiCOH, SiO, SiCO, SiCON; When described porous medium layer is laminated construction, the material of described porous medium layer is SiO
2, SiOF, SiCOH, SiO, SiCO, SiCON layer combination in any laminated construction.
The manufacture method of 13. interconnection structures as claimed in claim 1, is characterized in that, described hard mask layer is single layer structure or laminated construction, and when hard mask layer is single layer structure, the material of described hard mask layer is SiCOH; When hard mask layer is double-decker, described hard mask layer primer is SiCOH, and quilting material is tetraethoxysilane.
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| CN107703575A (en) * | 2017-11-29 | 2018-02-16 | 苏州晶鼎鑫光电科技有限公司 | A kind of multichannel integrated optical filter and its manufacture method |
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| US20110263117A1 (en) * | 2010-04-27 | 2011-10-27 | Samsung Electronics Co., Ltd. | Apparatus for manufacturing semiconductor device and method of manufacturing semiconductor device using the same |
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| US6043165A (en) * | 1996-10-28 | 2000-03-28 | Samsung Electronics Co., Ltd. | Methods of forming electrically interconnected lines using ultraviolet radiation as an organic compound cleaning agent |
| CN101045820A (en) * | 2006-03-30 | 2007-10-03 | 富士通株式会社 | Composition for forming insulated film and method for manufacturing semiconductor device |
| US20110263117A1 (en) * | 2010-04-27 | 2011-10-27 | Samsung Electronics Co., Ltd. | Apparatus for manufacturing semiconductor device and method of manufacturing semiconductor device using the same |
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| CN107703575A (en) * | 2017-11-29 | 2018-02-16 | 苏州晶鼎鑫光电科技有限公司 | A kind of multichannel integrated optical filter and its manufacture method |
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