CN104064635A - Preparation method for vertically structural LED chips - Google Patents
Preparation method for vertically structural LED chips Download PDFInfo
- Publication number
- CN104064635A CN104064635A CN201410183515.XA CN201410183515A CN104064635A CN 104064635 A CN104064635 A CN 104064635A CN 201410183515 A CN201410183515 A CN 201410183515A CN 104064635 A CN104064635 A CN 104064635A
- Authority
- CN
- China
- Prior art keywords
- preparation
- electrode
- gan layer
- layer
- led chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
Abstract
The invention provides a preparation method for vertically structural LED chips. The preparation method comprises the steps of: binding an epitaxial layer onto a high-resistance silicon substrate, removing a growth substrate and a buffer layer to expose an N-type GaN layer, and etching part area of the exposed GaN layer until a metal layer is exposed; the method also comprises the steps of: evaporating a P electrode metal on the metal layer to form a P electrode, and evaporating a N electrode metal on the GaN layer to form an N electrode. According to the preparation method, the epitaxial layer is bound onto a high-resistance silicon substrate, so that the P electrode of the chip is insulated from the bottom of the chip. The LED chips prepared by the preparation method retain the photoelectric characteristics of the vertically structural chips, and also overcome the problem that the common vertically structural chips are difficult to be connected in series due to the fact that routing needs to be performed on the chips for connecting when in packaging.
Description
Technical field
The present invention relates to LED technology field.More specifically, the present invention relates to a kind of preparation method of LED chip of vertical stratification.
Background technology
Current LED chip mainly contains same side structure and two kinds of structures of vertical stratification.For the LED chip of same side structure, its substrate is generally the Sapphire Substrate of printing opacity, even if the chip back side plates lighttight reflectance coating, also have the bright dipping simultaneously of 5 faces, thereby the uniform white light of the most difficult acquisition hot spot of the chip of this structure, can there is obvious yellow circle in sides of chip, cause the LED chip of same side structure to apply and be obstructed in white light LEDs field.And for the LED chip of vertical stratification, because light-emitting film is to transfer to new lighttight supporting substrate from epitaxial substrate, it is luminous that for the device of this structure, it only has a face, thereby it the most easily obtains the uniform white light of hot spot.Make the LED chip of vertical stratification more extensive in the application of white light LEDs field.But the LED chip of vertical stratification, because distribution of electrodes is in the both sides of chip, need to connect at the both sides of chip while routing in the time that encapsulation forms white light, has the problem that series connection is difficult.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of preparation method of LED chip of vertical stratification, and LED chip obtained by this method can simply be connected in series in the time of encapsulation.
In order to solve technical problem of the present invention, the invention provides a kind of preparation method of LED chip of vertical stratification, the method is included in growth substrates grown buffer layer, N-type GaN layer, multiple quantum well layer, P type GaN layer successively, form epitaxial loayer, described epitaxial loayer nation is fixed on High Resistivity Si substrate, remove growth substrates and resilient coating, expose N-type GaN layer, the subregion of the GaN layer exposing described in etching is to exposing metal level, the method is also included in evaporation P electrode metal on metal level and forms P electrode, and on N-type GaN layer, evaporation N electrode metal forms N electrode.
Preferably, described etching is to adopt ICP or RIE dry etching.
Preferably, described growth substrates is the one in following: sapphire, silicon, carborundum.
Preferably, the material of described P electrode metal and N electrode metal is respectively the one in following: Al/Pt/Au, Ag/Pt/Au, Ni/Ag/Pt/Au, TiW/Pt/Au, Ti/Ag/Pt/Au, Ni/Al/Pt/Au, Ti/Al/Pt/Au.
Beneficial effect of the present invention is as follows:
The invention provides a kind of preparation method of LED chip of vertical stratification, by epitaxial loayer nation is fixed on High Resistivity Si substrate, make the P electrode of chip and the bottom insulation of chip.Adopt LED chip prepared by method of the present invention both to retain the photoelectricity feature of thin-film LED, can solve again general vertical chip and be connected in series difficult problem at packaging and routing.
Brief description of the drawings
Fig. 1 is the plan structure schematic diagram of LED chip of the present invention;
Fig. 2-Fig. 5 is the manufacture process schematic diagram of one embodiment of the invention;
Identifier declaration in figure:
1 is sapphire growth substrate, and 2 is resilient coating, and 3 is N-type GaN layer, and 4 is multiple quantum well layer, and 5 is P type GaN layer, and 6 is metal barrier, and 7 is binding layer, and 8 is High Resistivity Si substrate, and 9 is P electrode, and 10 is N electrode.
Embodiment
Below in conjunction with drawings and Examples, the present invention is further described.
Fig. 1 is the plan structure schematic diagram of the LED chip of the vertical stratification prepared by method provided by the invention.
Epitaxial growth buffer 2 successively in sapphire growth substrate 1 as shown in Figure 2, N-type GaN layer 3, multiple quantum well layer 4, P type GaN layer 5, forms epitaxial loayer, splash-proofing sputtering metal barrier layer 6 on epitaxial loayer.As shown in Figure 3, epitaxial loayer is bonded on High Resistivity Si substrate 8 by nation's given layer 7.Adopt the method for laser lift-off to remove growth substrates 1, epitaxial loayer is transferred on High Resistivity Si substrate 8, remove resilient coating 2 by ICP etching method, expose N-type GaN layer 3, as shown in Figure 4.As shown in Figure 5, the subregion of the GaN layer exposing by ICP etching method etching is to exposing metal barrier 6, evaporation P electrode metal material on the metal barrier 6 exposing, form P electrode 9, form N electrode 10 at evaporation N electrode metal on N-type GaN layer 3, complete the preparation of LED chip.
The above; it is only the embodiment in the present invention; but protection scope of the present invention is not limited to this, any people who is familiar with this technology is in the disclosed technical scope of the present invention, within the conversion that can expect easily or replacement all should be encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claims.
Claims (4)
1. a preparation method for the LED chip of vertical stratification, comprising:
Grown buffer layer, N-type GaN layer, multiple quantum well layer, P type GaN layer successively in growth substrates, form epitaxial loayer;
It is characterized in that, described epitaxial loayer nation is fixed on High Resistivity Si substrate, remove growth substrates and resilient coating, expose N-type GaN layer;
The subregion of the GaN layer exposing described in etching is to exposing metal level;
On described metal level, evaporation P electrode metal forms P electrode, and on N-type GaN layer, evaporation N electrode metal forms N electrode.
2. the preparation method of the LED chip of vertical stratification according to claim 1, is characterized in that described etching is to adopt ICP or RIE dry etching.
3. the preparation method of the LED chip of vertical stratification according to claim 1, is characterized in that described growth substrates is the one in following: sapphire, silicon, carborundum.
4. the preparation method of the LED chip of vertical stratification according to claim 1, the material that it is characterized in that described P electrode metal and N electrode metal is respectively the one in following: Al/Pt/Au, Ag/Pt/Au, Ni/Ag/Pt/Au, TiW/Pt/Au, Ti/Ag/Pt/Au, Ni/Al/Pt/Au, Ti/Al/Pt/Au.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410183515.XA CN104064635A (en) | 2014-05-04 | 2014-05-04 | Preparation method for vertically structural LED chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410183515.XA CN104064635A (en) | 2014-05-04 | 2014-05-04 | Preparation method for vertically structural LED chips |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104064635A true CN104064635A (en) | 2014-09-24 |
Family
ID=51552259
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410183515.XA Pending CN104064635A (en) | 2014-05-04 | 2014-05-04 | Preparation method for vertically structural LED chips |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104064635A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105428502A (en) * | 2015-12-15 | 2016-03-23 | 江苏稳润光电有限公司 | White light LED wafer packaging structure and packaging method |
| US10141482B2 (en) | 2015-08-03 | 2018-11-27 | Alpad Corporation | Semiconductor light emitting device |
| WO2020087271A1 (en) * | 2018-10-30 | 2020-05-07 | 苏州晶湛半导体有限公司 | Semiconductor structure and manufacturing method therefor |
-
2014
- 2014-05-04 CN CN201410183515.XA patent/CN104064635A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10141482B2 (en) | 2015-08-03 | 2018-11-27 | Alpad Corporation | Semiconductor light emitting device |
| TWI663751B (en) * | 2015-08-03 | 2019-06-21 | 日商阿爾發得股份有限公司 | Semiconductor light emitting device |
| CN105428502A (en) * | 2015-12-15 | 2016-03-23 | 江苏稳润光电有限公司 | White light LED wafer packaging structure and packaging method |
| WO2020087271A1 (en) * | 2018-10-30 | 2020-05-07 | 苏州晶湛半导体有限公司 | Semiconductor structure and manufacturing method therefor |
| US11646345B2 (en) | 2018-10-30 | 2023-05-09 | Enkris Semiconductor, Inc. | Semiconductor structure and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103560193B (en) | Light emitting diode chip with vertical of low cost and preparation method thereof | |
| CN103682004B (en) | A kind of light emitting diode flip-chip for improving light emission rate and preparation method thereof | |
| US9159895B2 (en) | Vertical light emitting device and manufacturing method thereof | |
| CN104350613A (en) | Method of forming micro LED device with self-aligned metallization stack | |
| CN102354723B (en) | Flip semiconductor luminescent device and manufacturing method thereof | |
| CN101315959A (en) | High brightness luminescent diode | |
| WO2013159526A1 (en) | Light-emitting diode device and manufacturing method thereof | |
| TW201547058A (en) | Light emitting diode and method of fabricating the same | |
| CN102427107A (en) | High-power white light-emitting diode (LED) flip chip and manufacturing method thereof | |
| CN103178074A (en) | Light emitting diode array and forming method thereof | |
| CN102509731A (en) | Alternating current vertical light emitting element and manufacture method thereof | |
| EP2316138A1 (en) | Method for fabricating semiconductor light-emitting device with double-sided passivation | |
| CN105742450A (en) | Preparation method for LED chip capable of forming light spots with specific planar geometric patterns through illumination, and structure of LED chip | |
| CN106981497A (en) | A kind of high pressure flip LED chips structure and its manufacture method | |
| CN109638131B (en) | Manufacturing method of DBR flip chip | |
| CN104064635A (en) | Preparation method for vertically structural LED chips | |
| CN112635629A (en) | Light emitting diode and manufacturing method thereof | |
| TWI302038B (en) | Light emitting diode having an adhesive layer and heat paths | |
| CN105514230A (en) | GaN-base LED vertical chip structure and manufacture method thereof | |
| US20120261686A1 (en) | Light-emitting element and the manufacturing method thereof | |
| CN104103723A (en) | Gallium nitride light emitting diode and manufacturing method thereof | |
| CN203746848U (en) | Positive packaging LED chip of N-electrode extension-wire dotted distribution | |
| CN207977341U (en) | Led chip | |
| CN105428489A (en) | Method for preparing thin-film LED chip | |
| CN110556460A (en) | Ultrathin vertical-structure yellow-light LED and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140924 |
|
| RJ01 | Rejection of invention patent application after publication |