CN104051344A - Semiconductor arrangement and formation thereof - Google Patents

Semiconductor arrangement and formation thereof Download PDF

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Publication number
CN104051344A
CN104051344A CN201410095738.0A CN201410095738A CN104051344A CN 104051344 A CN104051344 A CN 104051344A CN 201410095738 A CN201410095738 A CN 201410095738A CN 104051344 A CN104051344 A CN 104051344A
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China
Prior art keywords
high pressure
region
grid
photoresist
low pressure
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CN201410095738.0A
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CN104051344B (en
Inventor
亚历克斯·卡尔尼茨基
郑光茗
周建志
朱振梁
段孝勤
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US14/184,900 external-priority patent/US9437494B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Abstract

A semiconductor arrangement and method of formation are provided. A method of semiconductor formation includes using a single photoresist to mask off an area where low voltage devices are to be formed as well as gate structures of high voltage devices while performing high energy implants for the high voltage devices. Another method of semiconductor fabrication includes performing high energy implants for high voltage devices through a patterned photoresist where the photoresist is patterned prior to forming gate structures for high voltage devices and prior to forming gate structures for low voltage devices. After the high energy implants are performed, subsequent processing is performed to form high voltage devices and low voltage devices. High voltage device and low voltage devices are thus formed in a CMOS process without need for additional masks.

Description

Semiconductor arrangement and formation thereof
Technical field
Present invention relates in general to semiconductor applications, more specifically, relate to a kind of semiconductor arrangement and forming method thereof.
Background technology
In such as transistorized semiconductor device, in the time that enough voltage or bias voltage are applied to the grid of device, electric current flows through the channel region between source area and drain region.In the time that electric current flows through channel region, device considered to be in " connection " state conventionally, and in the time that electric current does not flow through channel region, device considered to be in " closing " state conventionally.
Summary of the invention
According to an aspect of the present invention, a kind of semiconductor making method is provided, comprise: form and have multiple the first transistors of the first operating voltage, multiple the first transistors are included in multiple first grid structures, multiple low pressure shallow wells of contiguous multiple first grid structures and the multiple low pressure pockets injection region of contiguous multiple first grid structures on the first transistor region of substrate; And contiguous multiple the first transistors form multiple transistor secondses with the second operating voltage.Forming multiple transistor secondses comprises: on multiple first grid structures, on the first transistor region and on multiple second grid structures, form the first high pressure photoresist, multiple second grid structures, on the transistor seconds region of substrate, make to expose multiple high pressure injection region of substrate and multiple second grids top of multiple second grid structures of contiguous multiple second grid structures; Carry out high pressure LDD with the first high-energy and inject, so that the first high pressure alloy is injected in multiple high pressure injection region, thus multiple high pressure shallow wells of the contiguous multiple second grid structures of formation; And carry out high pressure pocket with the second high-energy and inject, so that the second high pressure alloy is injected in multiple high pressure injection region, thus multiple high pressure pockets injection region of the contiguous multiple second grid structures of formation.
Preferably, forming multiple the first transistors comprises: on transistor seconds region and on multiple second grid structures, form low pressure photoresist, make multiple low pressure injection region of the substrate that exposes multiple first grid structures and contiguous multiple first grid structures; Inject with the first low-yield execution low pressure LDD, so that the first voltage alloy is injected in multiple low pressure injection region, thereby form multiple low pressure shallow wells; And inject with the second low-yield execution low pressure pocket, so that the second low pressure alloy is injected in multiple low pressure injection region, thereby form multiple low pressure pockets injection region.
Preferably, the method comprises: on substrate, form ground floor grid dielectric material; Remove ground floor grid dielectric material from the first transistor region of substrate, the dielectric Part I of high pressure grid is stayed on the transistor seconds region of substrate; On substrate and on the dielectric Part I of high pressure grid, form second layer grid dielectric material, low pressure gate-dielectric is stayed on the first transistor region of substrate, and high pressure gate-dielectric is stayed on the transistor seconds region of substrate, wherein, high pressure gate-dielectric comprises Part I and the Part II from second layer grid dielectric material; On low pressure gate-dielectric and high pressure gate-dielectric, form layer of gate electrode material; And patterned layer layer of gate electrode material, low pressure gate-dielectric and high pressure gate-dielectric, to form multiple first grid structures and multiple second grid structure simultaneously.
Preferably, the method comprises: on multiple first grid structures, multiple second grid structure and substrate, form side-wall material layer; And patterned side wall material layer, to form multiple the first side wall spacers of contiguous multiple first grid structures and multiple second sidewall spacers of contiguous second grid structure simultaneously.
Preferably, carry out the injection of low pressure pocket and comprise: by selected rated voltage, be infused in the dosage using in device manufacture.
Preferably, multiple the first transistors are different from the type of multiple transistor secondses.
Preferably, carrying out high pressure LDD injection comprises: at least one of B Implanted, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon.
Preferably, carrying out the injection of high pressure pocket comprises: at least one of B Implanted, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon.
According to a further aspect in the invention, provide a kind of semiconductor making method, having comprised: on the first transistor region of substrate and the transistor seconds region of substrate, formed the first high pressure photoresist; Patterning the first high pressure photoresist, to form the residual photoresist of multiple high pressure on high pressure photoresist and the transistor seconds region on the first transistor region, makes multiple high pressure injection region of the substrate that exposes the residual photoresist of contiguous multiple high pressure; Carry out high pressure LDD with the first high-energy and inject, so that the first high pressure alloy is injected in multiple high pressure injection region, thus multiple high pressure shallow wells of the residual photoresist of the contiguous multiple high pressure of formation; And carry out high pressure pocket with the second high-energy and inject, so that the second high pressure alloy is injected in multiple high pressure injection region, thus multiple high pressure pockets injection region of the residual photoresist of the contiguous multiple high pressure of formation.
Preferably, the method comprises: the multiple first grid structures in formation the first transistor region and the multiple second grid structures in transistor seconds region; On multiple first grid structures and multiple second grid structure, form the first low pressure photoresist; Patterning the first low pressure photoresist, to form low pressure photoresist on transistor seconds region He on multiple second grid structures, makes multiple low pressure injection region of the substrate that exposes multiple first grid structures and contiguous multiple first grid structures; Inject with the first low-yield execution low pressure LDD, so that the first low pressure alloy is injected in multiple low pressure injection region, thus multiple low pressure shallow wells of the contiguous multiple first grid structures of formation; And inject with the second low-yield execution low pressure pocket, so that the second low pressure alloy is injected in multiple low pressure injection region, thus multiple low pressure pockets injection region of the contiguous multiple first grid structures of formation.
Preferably, the method comprises: on substrate, form ground floor grid dielectric material; Remove ground floor grid dielectric material from the first transistor region of substrate, the dielectric Part I of high pressure grid is stayed on the transistor seconds region of substrate; On substrate and on the dielectric Part I of high pressure grid, form second layer grid dielectric material, low pressure gate-dielectric is stayed on the first transistor region of substrate, and high pressure gate-dielectric is stayed on the transistor seconds region of substrate, wherein, high pressure gate-dielectric comprises Part I and the Part II from second layer grid dielectric material; On low pressure gate-dielectric He on high pressure gate-dielectric, form one deck gate material; And pattern gate electrode material layer, low pressure gate-dielectric and high pressure gate-dielectric, to form multiple first grid structures and multiple second grid structure simultaneously.
Preferably, the method comprises: on multiple first grid structures, multiple second grid structure and substrate, form side-wall material layer; And patterned side wall material layer, to form multiple the first side wall spacers of contiguous multiple first grid structures and multiple second sidewall spacers of contiguous multiple second grid structures simultaneously.
Preferably, carry out the injection of low pressure pocket and comprise: by selected rated voltage, be infused in the dosage using in device manufacture.
Preferably, multiple low pressure pockets injection region is different from the type of multiple high pressure pockets injection region.
Preferably, carrying out high pressure LDD injection comprises: at least one of B Implanted, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon; And/or the injection of execution high pressure pocket comprises: at least one of B Implanted, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon.
Preferably, carrying out high pressure LDD injection comprises: inject the first high pressure alloy to be basically perpendicular to the surperficial angle of substrate; And/or the injection of execution high pressure pocket comprises: inject the second high pressure alloy to be basically perpendicular to the surperficial angle of substrate.
According to another aspect of the invention, provide a kind of method of dopant implant thing, having comprised: on grid structure, deposit photoresist, grid structure has been positioned on substrate; Patterning photoresist, makes photoresist on the part end face instead of all end faces of grid structure, makes the photoresist width of photoresist be less than the grid structure width of grid structure; And in the time that photoresist is on grid structure, the first alloy is injected in substrate, in substrate, form the first doped region with adjacent gate structures.
Preferably, the method comprises: in the time that photoresist is on grid structure, the second alloy is injected in substrate, forms the second doped region with adjacent gate structures in substrate.
Preferably, injecting the first alloy comprises: at least one of injection phosphorus, arsenic, boron, nitrogen or carbon; And/or injection the second alloy comprises: at least one of injection phosphorus, arsenic, boron, nitrogen or carbon.
Preferably, injecting the first alloy comprises: the angle with the end face that is basically perpendicular to substrate is injected the first alloy; And/or inject the first alloy and comprise: the angle with the end face that is substantially not orthogonal to substrate is injected the first alloy.
Brief description of the drawings
In the time reading accompanying drawing, understand best many aspects of the present invention by following detailed description.Note, according to the standard practices in industry, multiple parts not to scale (NTS) is drawn.In fact, for discuss clear for the purpose of, the size of multiple parts can at random increase or reduce.
Fig. 1 is the flow chart illustrating according to the semiconductor making method of some embodiment.
Fig. 2 is the flow chart illustrating according to the semiconductor making method of some embodiment.
Fig. 3 is according to the diagram of the semiconductor arrangement of some embodiment.
Fig. 4 is according to the diagram of the semiconductor arrangement of some embodiment.
Fig. 5 is according to the diagram of the semiconductor arrangement of some embodiment.
Fig. 6 is according to the diagram of the semiconductor arrangement of some embodiment.
Fig. 7 is according to the diagram of the semiconductor arrangement of some embodiment.
Fig. 8 is according to the diagram of the semiconductor arrangement of some embodiment.
Fig. 9 is according to the diagram of the semiconductor arrangement of some embodiment.
Figure 10 is according to the diagram of the semiconductor arrangement of some embodiment.
Figure 11 is according to the diagram of the semiconductor arrangement of some embodiment.
Figure 12 is according to the diagram of the semiconductor arrangement of some embodiment.
Figure 13 is according to the diagram of the semiconductor arrangement of some embodiment.
Figure 14 is according to the diagram of the semiconductor arrangement of some embodiment.
Figure 15 is according to the diagram of the semiconductor arrangement of some embodiment.
Figure 16 is according to the diagram of the semiconductor arrangement of some embodiment.
Figure 17 is according to the diagram of the semiconductor arrangement of some embodiment.
Figure 18 is according to the diagram of the semiconductor arrangement of some embodiment.
Figure 19 is according to the diagram of the semiconductor arrangement of some embodiment.
Figure 20 is according to the diagram of the semiconductor arrangement of some embodiment.
Figure 21 is according to the diagram of the semiconductor arrangement of some embodiment.
Figure 22 is according to the diagram of the semiconductor arrangement of some embodiment.
Figure 23 is according to the diagram of the semiconductor arrangement of some embodiment.
Figure 24 is according to the diagram of the semiconductor arrangement of some embodiment.
Figure 25 is according to the diagram of the semiconductor arrangement of some embodiment.
Figure 26 is according to the diagram of the semiconductor arrangement of some embodiment.
Embodiment
Following discloses are provided for multiple different embodiment or the example of the different parts that the theme providing is provided.The particular instance of assembly and layout is below described, to simplify the disclosure.Certainly, these are only examples and are not used in restriction.For example, First Characteristic in following specification on second component or on form and can comprise the directly embodiment of contact of the first and second parts, and can comprise and can between the first and second parts, form optional feature, the embodiment that the first and second parts can directly not contacted.In addition, the disclosure can repeat reference numerals and/or letter in Multi-instance.This is recycled and reused for simple and object clearly, and itself does not indicate the relation between discussed multiple embodiment and/or structure.
And, such as " ... under ", " under ", " below ", " on ", the space relative terms of " above " etc. can be used to easy explanation at this, to describe element as shown in FIG. or the relation of parts and another element or parts.Except orientation shown in the figure, space relative terms is intended to comprise the difference orientation of the device using or operate.Device can be directed (90-degree rotation or for other orientations) in addition, and space relative descriptors is correspondingly explained in addition as used herein.
Be provided at this structure that forms one or more technology of semiconductor arrangement and form thus.
Fig. 1 illustrates the first method 100 of manufacturing according to the semiconductor of some embodiment, and in the one or more structures that form thus in multiple fabrication stages shown in Fig. 3 to Figure 15.According to some embodiment, as shown in Figure 15 all, semiconductor arrangement 300 comprises the multiple the first transistor 332a that are arranged in the first transistor region 321a and the multiple transistor seconds 332b that are arranged in the transistor seconds region 321b on substrate 302, and multiple the first transistors have the first operating voltage and contiguous multiple transistor seconds 332b with the second operating voltage that is greater than the first operating voltage.To expect, in zones of different described here, form its multiple transistors and parts, elements etc., and for simplicity, its single instance will only be shown in the drawings.Line 399 illustrates the first transistor 332a conventionally and the isolation of transistor seconds 332b electricity or decoupling.In certain embodiments, multiple the first transistor 332a comprise multiple the first side wall spacer 309a of multiple first grid structure 330a and contiguous multiple first grid structure 330a.In certain embodiments, multiple the first source drain district 344a are in the substrate 302 of contiguous multiple first grid structure 330a.In certain embodiments, contiguous multiple the first source drain district 344a of multiple low pressure pocket injection region 328a, make multiple low pressure pocket injection region 328a extend fartherly than multiple the first source drain district 344a below multiple first grid structure 330a.In certain embodiments, multiple transistor seconds 332b comprise multiple the second sidewall spacers 309b of multiple second grid structure 330b and contiguous multiple second grid structure 330b.In certain embodiments, multiple the second source drain district 344b are in the substrate 302 of contiguous multiple second grid structure 330b.In certain embodiments, contiguous multiple the second source drain district 344b of multiple high pressure pocket injection region 328b, make multiple high pressure pocket injection region 328b extend fartherly than multiple the second source drain district 344b below multiple second grid structure 330b.In one embodiment, multiple the first transistor 332a comprise at least one in low-voltage device or middle voltage device.In certain embodiments, multiple transistor seconds 332b comprise at least one in middle voltage device or high tension apparatus.In certain embodiments, multiple the first transistor 332a are dissimilar, such as, be different from the device voltage type of multiple transistor seconds 332b.In certain embodiments, low-voltage device has the operating voltage that is less than about 1.5V.In certain embodiments, middle voltage device has at about 3.3V to the operating voltage between about 10V.In certain embodiments, high tension apparatus has the operating voltage more than about 30V.In certain embodiments, the semiconductor arrangement 300 forming according to the first method 100 has than the thinner gate electrode of layout not forming according to the first method 100.In one embodiment, multiple the first transistor 332a and multiple transistor seconds 332b are formed a part for single CMOS manufacture processing and do not need additional masking.
According to some embodiment, method 100 102 in, on the 321a of the first transistor region of substrate 302, form multiple first grid structure 330a, and on the 321b of the transistor seconds region of substrate 302, form multiple second grid structure 330b, as shown in Figure 7.Forward Fig. 3 to, before Fig. 7, on the end face 302a of substrate 302, form ground floor grid dielectric material 304 according to some embodiment.In certain embodiments, substrate 302 comprises at least one in silicon or germanium.According to some embodiment, substrate 302 comprise epitaxial loayer, silicon-on-insulator (SOI) structure, wafer or the tube core that formed by wafer at least one.In certain embodiments, ground floor grid dielectric material 304 comprises at least one in oxide or nitride.In certain embodiments, ground floor grid dielectric material 304 has approximately extremely approximately between the first thickness 303a.In certain embodiments, such as by etching, remove ground floor grid dielectric material 304 from the end face 302a of the substrate 302 on the 321a of the first transistor region, the Part I 304b1 of high pressure gate-dielectric 304b is stayed on the transistor seconds region 321b of substrate 302, as shown in Figure 4.In certain embodiments, on the end face 302a of substrate 302 and on the Part I 304b1 of high pressure gate-dielectric 304d, form second layer grid dielectric material 305, low pressure gate-dielectric 304a is stayed on the first transistor region 231a of substrate 302, and high pressure gate-dielectric 304b stays on the transistor seconds region 321b of substrate 302, as shown in Figure 5.In certain embodiments, second layer grid dielectric material 305 comprises at least one in oxide or nitride.In certain embodiments, second layer grid dielectric material 305 has approximately extremely approximately between the second thickness 303b, make low pressure gate-dielectric 304a there is the second thickness 303b.In certain embodiments, high pressure gate-dielectric 304b comprises Part I 304b1 and the Part II 304b2 from second layer grid dielectric material 305.In certain embodiments, high pressure gate-dielectric 304b has approximately extremely approximately between the 3rd thickness 303c, wherein, the 3rd thickness 303c is generally equal to the summation of the first thickness 303a and the second thickness 303b.In certain embodiments, on low pressure gate-dielectric 304a and high pressure gate-dielectric 304b, form one deck gate material 310, as shown in Figure 6.In certain embodiments, this layer of gate material 310 has basic thickness uniformly.In certain embodiments, this layer of gate material 310 comprises at least one in polysilicon or metal.In certain embodiments, this layer of gate material 310, low pressure gate-dielectric 304a and high pressure gate-dielectric 304b are patterned, to form the multiple second grid structure 330b in multiple first grid structure 330a and the transistor seconds region 321b in the 321a of the first transistor region simultaneously, as shown in Figure 7.In certain embodiments, the respective gate structure of multiple first grid structure 330a has the first width 340a, and the respective gate structure of multiple second grid structure 330b has the second width 340b.In certain embodiments, the second width 340b is greater than the first width 340a.In certain embodiments, the multiple first grid structure 330a in the contiguous the first transistor region 321a of multiple low pressure injection region 311a.In certain embodiments, the multiple second grid structure 330b in the contiguous transistor seconds region 321b of multiple high pressure injection region 311b.
According to some embodiment, method 100 104 in, on multiple second grid structure 330b and transistor seconds region 321b, form low pressure photoresist 308a, expose thus multiple first grid structure 330a and multiple low pressure injection region 311a, as shown in Figure 9.Forward Fig. 8 to, according to some embodiment, before Fig. 9, such as by depositing and form the first low pressure photoresist 308 on multiple first grid structure 330a, multiple second grid structure 330b and substrate 302.In certain embodiments, the first low pressure photoresist 308 is patterned, to form low pressure photoresist 308a, as shown in Figure 9.
According to some embodiment, method 100 106 in, carry out low pressure LDD and inject, so that the first low pressure alloy 318a is injected in multiple low pressure injection region 311a, to form multiple low pressure shallow well 314a, as shown in figure 10.In certain embodiments, the first low pressure alloy 318a comprises at least one in boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon.In certain embodiments, by selected rated voltage, with the dosage and energy injection the first low pressure alloy 318a that use in device is manufactured.In certain embodiments, semiconductor arrangement 300 is carried out to the first annealing, multiple low pressure shallow well 314a are moved below multiple first grid structure 330a.In certain embodiments, low pressure photoresist 308a prevents that the first low pressure alloy 318a from entering in the region below low pressure photoresist 308a.In certain embodiments, by selected rated voltage, inject the first low pressure alloy 318a with the first angle using in device manufacture.
According to some embodiment, method 100 108 in, carry out low pressure pocket and inject, so that the second low pressure alloy 318b is injected in multiple low pressure injection region 311a, to form multiple low pressure pocket injection region 328a, as shown in figure 11.In certain embodiments, the second low pressure alloy 318b comprises at least one in boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon.In certain embodiments, by selected rated voltage, with the dosage and energy injection the second low pressure alloy 318b that use in device is manufactured.In certain embodiments, low pressure photoresist 308a prevents that the second low pressure alloy 318b from entering in the region below low pressure photoresist 308a.In certain embodiments, by selected rated voltage, inject the second low pressure alloy with the second angle using in device manufacture.In certain embodiments, multiple low pressure pocket injection region 328a are at least in part below multiple first grid structure 330a.In certain embodiments, semiconductor arrangement 300 is carried out to the second annealing, multiple low pressure shallow well 314a and multiple low pressure pocket injection region 328a are moved below multiple first grid structure 330a.In certain embodiments, such as by least one in pickling or etching, remove low pressure photoresist 308a from multiple second grid structure 330b and transistor seconds region 321b, as shown in figure 12.
According to some embodiment, method 100 110 in, on multiple first grid structure 330a, form high pressure photoresist 331a on the 321a of the first transistor region of substrate, and on multiple second grid structure 330b, form the residual photoresist 331b of multiple high pressure, thereby expose multiple high pressure injection region 311b of substrate 302 and multiple the second tops 326 of multiple second grid structure 330b, as shown in figure 13.In certain embodiments, by such as by deposition formation the first high pressure photoresist (not shown) on multiple first grid structure 330a, multiple second grid structure 330b and substrate 302 and such as by least one the patterning first high pressure photoresist in pickling or etching, form high pressure photoresist 331a and the residual photoresist 331b of multiple high pressure.In certain embodiments, the residual photoresist 331b of multiple high pressure is between multiple second grids top 326, wherein, the residual photoresist 331b of multiple high pressure and first grid edge 329a be at a distance of first apart from 324a, and with second grid edge 329b at a distance of second distance 324b.In certain embodiments, first is different distance apart from 324a and second distance 324b.In certain embodiments, first equals second distance 324b apart from 324a.In certain embodiments, first apart from 324a at about 30nm between about 90nm, or second distance 324b at about 30nm between about 90nm.
According to some embodiment, method 100 112 in, carry out high pressure LDD and inject, so that the first high pressure alloy 318c is injected in multiple high pressure injection region 311b, to form multiple high pressure shallow well 314b, as shown in Figure 13.In certain embodiments, the first high pressure alloy 318c comprises at least one in boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon.In certain embodiments, by selected rated voltage, with the dosage and energy injection the first high pressure alloy 318c that use in device is manufactured.In certain embodiments, semiconductor arrangement 300 is carried out to the 3rd annealing, multiple high pressure shallow well 314b are moved below multiple second grid structure 330b.In certain embodiments, high pressure photoresist 331a prevents that the first high pressure alloy 318c from entering in the region below high pressure photoresist 331a.In certain embodiments, the residual photoresist 331b of multiple high pressure protects multiple second grid structures not affected by the first high pressure alloy 318c similarly.In certain embodiments, by selected rated voltage, inject the first high pressure alloy 318c with the 3rd angle using in device manufacture.
According to some embodiment, method 100 114 in, carry out high pressure pocket and inject, so that the second high pressure alloy 318d is injected in multiple high pressure injection region 311b, to form multiple high pressure pocket injection region 318b, as shown in figure 14.In certain embodiments, the second high pressure alloy 318d comprises at least one in boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon.In certain embodiments, by selected rated voltage, with the dosage and energy injection the second high pressure alloy 318d that use in device is manufactured.In certain embodiments, high pressure photoresist 331a prevents that the second high pressure alloy 318d from entering in the region below high pressure photoresist 331a.In certain embodiments, the residual photoresist 331b of multiple high pressure protects multiple second grid structure 330b not affected by the second high pressure alloy 318d similarly.In certain embodiments, by selected rated voltage, inject the second high pressure alloy 318d with the 4th angle using in device manufacture.In certain embodiments, multiple high pressure pocket injection region 328b are at least in part below multiple second grid structure 330b.In certain embodiments, semiconductor arrangement 300 is carried out to the 4th annealing, multiple high pressure shallow well 314b and multiple high pressure pocket injection region 328b are moved below multiple second grid structure 330b.In certain embodiments, such as by least one in pickling or etching, remove high pressure photoresist 331a and the residual photoresist 331b of multiple high pressure from multiple second grid structure 330b, multiple first grid structure 330a and the first transistor region 321a, as shown in figure 15.
In certain embodiments, on multiple first grid structure 330a, multiple second grid structure 330b and substrate 302, form one deck side-wall material (not shown).In certain embodiments, this layer of side-wall material comprises nitride.In certain embodiments, this layer of side-wall material is patterned, to form multiple the first side wall spacer 309a of contiguous multiple first grid structure 330a and multiple the second sidewall spacers 309b of contiguous multiple second grid structure 330b simultaneously.
In certain embodiments, according to some embodiment, carry out low pressure deep trap associatedly with the photoresist (not shown) of corresponding pattern and inject, so that the 3rd low pressure alloy (not shown) is injected in multiple low pressure shallow well 314a, to form the first source drain district 344a, as shown in figure 15.In certain embodiments, the 3rd low pressure alloy comprises at least one in boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon.In certain embodiments, by selected rated voltage, with the dosage and energy injection the 3rd low pressure alloy that use in device is manufactured.In certain embodiments, according to some embodiment, carry out deep high voltage well associatedly with the photoresist (not shown) of corresponding pattern and inject, third high is pressed alloy (not shown) be injected in multiple high pressure shallow well 314b, to form the second source drain district 344b, as shown in figure 15.In certain embodiments, third high presses alloy to comprise at least one in boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon.In certain embodiments, by selected rated voltage, press alloy with the dosage and the energy injection third high that use in device is manufactured.
Suppose in certain embodiments, first is not equal to second distance 324b apart from 324a, such as owing to aiming at or forming the inaccurate of the residual photoresist 331b of multiple high pressure with respect to multiple second grid structure 330b, at least one in multiple high pressure shallow well 314b, multiple high pressure pocket injection region 328b or multiple the second source drain district 344b is asymmetric about corresponding second grid structure 330b.According to some embodiment, the size in the second source drain district in a side of second grid structure is different from the size in the second source drain district in another side of second grid structure.According to some embodiment, and be inverted when transistor seconds compared with when biasing, in the time that transistor seconds is forward biased, this asymmetric generation different characteristic curve of the alloy injecting at second grid structure periphery.
Fig. 2 illustrates the second method 200 of manufacturing according to the semiconductor of some embodiment, and locates in multiple fabrication stages the one or more structures that form thus shown in Figure 16 to 26.According to some embodiment, as shown in Figure 26 all, semiconductor arrangement 400 comprises the multiple the first transistor 432a that are arranged in the first transistor region 421a and the multiple transistor seconds 432b that are arranged in the transistor seconds region 421b on substrate 402, and described multiple the first transistors have the first operating voltage and contiguous multiple transistor seconds 432b with the second operating voltage that is greater than the first operating voltage.To expect, in zones of different described here, form its multiple transistors and feature, elements etc., and for simplicity, its single instance will only be shown.Line 499 illustrates the first transistor 432a conventionally and the isolation of transistor seconds 432b electricity or decoupling.In certain embodiments, multiple the first transistor 432a comprise multiple the first side wall spacer 409a of multiple first grid structure 430a and contiguous multiple first grid structure 430a.In certain embodiments, multiple the first source drain district 444a are in the substrate 402 of contiguous multiple first grid structure 430a.In certain embodiments, contiguous multiple the first source drain district 444a of multiple low pressure pocket injection region 428a, make multiple low pressure pocket injection region 428a extend fartherly than multiple the first source drain district 444a below multiple first grid structure 430a.In certain embodiments, multiple transistor seconds 432b comprise multiple the second sidewall spacers 409b of multiple second grid structure 430b and contiguous multiple second grid structure 430b.In certain embodiments, multiple the second source drain district 444b are in the substrate 402 of contiguous multiple second grid structure 430b.In certain embodiments, contiguous multiple the second source drain district 444b of multiple high pressure pocket injection region 428b, make multiple high pressure pocket injection region 428b extend fartherly than multiple the second source drain district 444b below multiple second grid structure 430b.In certain embodiments, multiple the first transistor 432a comprise at least one in low-voltage device or middle voltage device.In certain embodiments, multiple transistor seconds 432b comprise at least one in middle voltage device or high tension apparatus.In certain embodiments, multiple the first transistor 432a are dissimilar, such as, be different from the device voltage type of multiple transistor seconds 432b.In certain embodiments, low-voltage device has the operating voltage that is less than about 1.5V.In certain embodiments, middle voltage device has at about 3.3V to the operating voltage between about 10V.In certain embodiments, high tension apparatus has operating voltage more than about 30V.In certain embodiments, the semiconductor arrangement 400 forming according to the second method 200 has than the thinner gate electrode of layout not forming according to the second method 200.In certain embodiments, multiple the first transistor 432a and multiple transistor seconds 432b are formed single CMOS and manufacture a part of processing, and do not need additional masking.
According to some embodiment, method 200 202 in, on the first transistor region 421a of substrate 402 and the transistor seconds region 421b of substrate 402, form the first high pressure photoresist 431, as shown in Figure 16.In certain embodiments, substrate 402 comprises at least one in silicon or germanium.According to some embodiment, substrate 402 comprise epitaxial loayer, silicon-on-insulator (SOI) structure, wafer or the tube core that formed by wafer at least one.
According to some embodiment, method 200 204 in, patterning the first high pressure photoresist 431, to form high pressure photoresist 431a and form the residual photoresist 431b of multiple high pressure on the 421a of the first transistor region on the 421b of transistor seconds region, thereby expose multiple high pressure injection region 411b of the substrate 402 of the residual photoresist 431b of contiguous multiple high pressure, as shown in Figure 17.In certain embodiments, the residual photoresist 431b of multiple high pressure has about 350nm to the first residual photoresist width 413 between about 450nm.
According to some embodiment, method 200 206 in, carry out high pressure LDD and inject, so that the first high pressure alloy 418a is injected in multiple high pressure injection region 411b, to form multiple high pressure shallow well 414b, as shown in figure 17.In certain embodiments, the first high pressure alloy 418a comprises at least one in boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon.In certain embodiments, by selected rated voltage, with the dosage and energy injection the first high pressure alloy 418a that use in device is manufactured.In certain embodiments, semiconductor arrangement 400 is carried out to the first annealing, multiple high pressure shallow well 414b are moved below the residual photoresist 431b of multiple high pressure.In certain embodiments, high pressure photoresist 431a prevents that the first high pressure alloy 418a from entering in the region of the substrate 402 below high pressure photoresist 431a.In certain embodiments, the residual photoresist 431b of multiple high pressure prevents that substrate 402 from avoiding the first high pressure alloy 418a impact similarly.In certain embodiments, to incide first angle of surperficial 402a of substrate 402, inject the first high pressure alloy 418a, wherein, the first angle is basically perpendicular to the surperficial 402a of substrate 402.In certain embodiments, the first angle comprises the angle using in device is manufactured by selected rated voltage.
According to some embodiment, method 200 208 in, carry out high pressure pocket and inject, so that the second high pressure alloy 418b is injected in multiple high pressure injection region 411b, to form multiple high pressure pocket injection region 428b, as shown in figure 18.In certain embodiments, the second high pressure alloy 418b comprises at least one in boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon.In certain embodiments, by selected rated voltage, with the dosage and energy injection the second high pressure alloy 418b that use in device is manufactured.In certain embodiments, high pressure photoresist 431a prevents that the second high pressure alloy 418b from entering in the region of the substrate 402 below high pressure photoresist 431a.In certain embodiments, the residual photoresist 431b of multiple high pressure prevents that substrate 402 from avoiding the second high pressure alloy 418b impact similarly.In certain embodiments, inject the second high pressure alloy 418b with the second angle of the surperficial 402a that incides substrate 402, wherein, the second angle is basically perpendicular to the surperficial 402a of substrate 402.In certain embodiments, the second angle comprises the angle using in device is manufactured by selected rated voltage.In certain embodiments, multiple high pressure pocket injection region 428b are at least in part below the residual photoresist 431b of multiple high pressure.In certain embodiments, semiconductor arrangement 400 is carried out to the second annealing, multiple high pressure shallow well 414b and multiple high pressure pocket injection region 428b are moved below the residual photoresist 431b of multiple high pressure.In certain embodiments, such as by least one in pickling or etching, remove high pressure photoresist 431a and the residual photoresist 431b of multiple high pressure, as shown in figure 19.
According to some embodiment, method 200 210 in, on the 421a of the first transistor region of substrate 402, form multiple first grid structure 430a, and on the 421b of the transistor seconds region of substrate 402, form multiple second grid structure 430b, make the contiguous multiple low pressure shallow well 414b of multiple second grid structure 430b, as shown in figure 23.Forward Figure 19 to, according to some embodiment, before Figure 23, with the same way (for example as shown in Figure 3) of describing about ground floor grid dielectric material 304 above, on substrate 402, form ground floor grid dielectric material 404.In certain embodiments, with above all same way of describing about ground floor grid dielectric material 304 as shown in Figure 4, remove ground floor grid dielectric material 404 from the first transistor region 431a of substrate 402, as shown in figure 20.In certain embodiments, with the same way of describing with above all formation about low pressure gate-dielectric 304a and high pressure gate-dielectric 304b as shown in Figure 5, on ground floor grid dielectric material 404, form second layer grid dielectric material 405, to form low pressure gate-dielectric 404a and high pressure gate-dielectric 404b, as shown in figure 21.In certain embodiments, with above all same way of describing about this layer of gate material 310 as shown in Figure 6, on low pressure gate-dielectric 404a and high pressure gate-dielectric 404b, form one deck gate material 410, as shown in figure 22.In certain embodiments, this layer of gate material of patterning 410, low pressure gate-dielectric 404a and high pressure gate-dielectric 404b, to form the multiple second grid structure 430b in multiple first grid structure 430a and the transistor seconds region 421b in the 421a of the first transistor region simultaneously, as shown in figure 23.In certain embodiments, the respective gate structure of multiple first grid structure 430a has the first width 440a, and the respective gate structure of multiple second grid structure 430b has the second width 440b.In certain embodiments, the second width 440b is greater than the first width 440a.In certain embodiments, the second width 440b is greater than the first residual photoresist width 413, makes at least one at least some at least some or the multiple high pressure pocket injection region 428b in multiple high pressure shallow well 414b below multiple second grid structure 430b.
According to some embodiment, method 200 212 in, on multiple second grid structure 430b and transistor seconds region 421b, form low pressure photoresist 408a, thereby expose multiple low pressure injection region 411a of multiple first grid structure 430a and contiguous multiple first grid structure 430a, as shown in figure 24.In certain embodiments, according to some embodiment, on multiple first grid structure 430a, multiple second grid structure 430b and substrate 402, form the first low pressure photoresist (not shown).In certain embodiments, patterning the first low pressure photoresist, to form low pressure photoresist 408a.
According to some embodiment, method 200 214 in, carry out low pressure LDD and inject, so that the first low pressure alloy 418c is injected in multiple low pressure injection region 411a, to form multiple low pressure shallow well 414a, as shown in figure 24.In certain embodiments, the first low pressure alloy 418c comprises at least one in boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon.In certain embodiments, by selected rated voltage, with the dosage and energy injection the first low pressure alloy 418c that use in device is manufactured.In certain embodiments, semiconductor arrangement 400 is carried out to the 3rd annealing, multiple low pressure shallow well 414a are moved below multiple first grid structure 430a.In certain embodiments, low pressure photoresist 408a prevents that the first low pressure alloy 418c from entering the region below low pressure photoresist 408a.In certain embodiments, by selected rated voltage, with the 3rd angle using, inject the first low pressure alloy 418c in device is manufactured.
According to some embodiment, method 200 216 in, carry out low pressure pocket and inject, so that the second low pressure alloy 418d is injected in multiple low pressure injection region 411a, to form multiple low pressure pocket injection region 428a, as shown in figure 25.In certain embodiments, the second low pressure alloy 418d comprises at least one in boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon.In certain embodiments, by selected rated voltage, with the dosage and energy injection the second low pressure alloy 418d that use in device is manufactured.In certain embodiments, low pressure photoresist 408a prevents that the second low pressure alloy 418d from entering in the region below low pressure photoresist 408a.In certain embodiments, by selected rated voltage, inject the second low pressure alloy 418d with the 4th angle using in device manufacture.In certain embodiments, multiple low pressure pocket injection region 428a are at least in part below multiple first grid structure 430a.In certain embodiments, semiconductor arrangement 400 is carried out to the 4th annealing, multiple low pressure shallow well 414a and multiple low pressure pocket injection region 428a are moved below multiple first grid structure 430a.In certain embodiments, such as by least one in pickling or etching, remove low pressure photoresist 408a from multiple second grid structure 430a and substrate 402, as shown in figure 26.
In certain embodiments, on multiple first grid structure 430a, multiple second grid structure 430b and substrate 402, form one deck side-wall material (not shown).In certain embodiments, this layer of side-wall material comprises nitride.In certain embodiments, this layer of side-wall material of patterning, to form multiple the first side wall spacer 409a of contiguous multiple first grid structure 430a and multiple the second sidewall spacers 409b of contiguous multiple second grid structure 430b simultaneously.
In certain embodiments, according to some embodiment, carry out low pressure deep trap associatedly with the photoresist (not shown) of corresponding pattern and inject, so that the 3rd low pressure alloy (not shown) is injected in multiple low pressure shallow well 414a, to form the first source drain district 444a, as shown in figure 26.In certain embodiments, the 3rd low pressure alloy comprises at least one in boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon.In certain embodiments, by selected rated voltage, with the dosage and energy injection the 3rd low pressure alloy that use in device is manufactured.In certain embodiments, according to some embodiment, carry out deep high voltage well associatedly with the photoresist (not shown) of corresponding pattern and inject, third high is pressed alloy (not shown) be injected in multiple high pressure shallow well 414b, to form the second source drain district 444b, as shown in figure 26.In certain embodiments, third high presses alloy to comprise at least one in boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon.In certain embodiments, by selected rated voltage, with the dosage and the energy that use in device is manufactured, inject third high and press alloy.
In certain embodiments, suppose after forming multiple high pressure shallow well 414b and multiple high pressure pocket injection region 428b, on multiple high pressure shallow well 414b and multiple high pressure pocket injection region 428b, form multiple second grid structure 430b, it is asymmetric about corresponding second grid structure 430b that multiple high pressure shallow well 414b, multiple high pressure pocket inject at least one of 428b or multiple the second source drain district 444b.According to some embodiment, second grid structure is different from second grid structure with respect at least one the degree of overlapping in the high pressure shallow well on second grid structure opposite side, high pressure pocket injection region or the second source drain district with respect at least one the degree of overlapping in the high pressure shallow well in second grid structure one side, high pressure pocket injection region or the second source drain district.According to some embodiment, compared with in the time that transistor seconds is reverse biased, in the time that transistor seconds is forward biased, this asymmetric generation different characteristic curve of the alloy injecting at second grid structure periphery.
According to some embodiment, a kind of semiconductor making method comprises: form multiple the first transistors with the first operating voltage, multiple the first transistors are included in multiple first grid structures, multiple low pressure shallow wells of contiguous multiple first grid structures and the multiple low pressure pockets injection region of contiguous first grid structure on the first transistor region of substrate.According to some embodiment, semiconductor making method further comprises: contiguous multiple the first transistors form multiple transistor secondses with the second operating voltage.In certain embodiments, forming multiple transistor secondses comprises: on multiple first grid structures, on the first transistor region and on multiple second grid structures, form the first high pressure photoresist, and multiple second grid structures are on the transistor seconds region of substrate, thereby multiple high pressure injection region of substrate and multiple second grids top of multiple second grid structures of the contiguous multiple second grid structures of exposure.In certain embodiments, forming multiple transistor secondses further comprises: carry out high pressure LDD with the first high-energy and inject, so that the first high pressure alloy is injected in multiple high pressure injection region, to form multiple high pressure shallow wells of contiguous multiple second grid structures, and carrying out high pressure pocket with the second high-energy injects, so that the second high pressure alloy is injected in multiple high pressure injection region, to form multiple high pressure pockets injection region of contiguous multiple second grid structures.
According to some embodiment, a kind of semiconductor making method comprises: on the first transistor region of substrate and the transistor seconds region of substrate, form the first high pressure photoresist, and patterning the first high pressure photoresist, with the high pressure photoresist on formation the first transistor region and the residual photoresist of multiple high pressure on transistor seconds region, thus multiple high pressure injection region of the substrate of the residual photoresist of the contiguous multiple high pressure of exposure.According to some embodiment, semiconductor making method further comprises: carry out high pressure LDD with the first high-energy and inject, so that the first high pressure alloy is injected to multiple high pressure injection region, to form multiple high pressure shallow wells of the residual photoresist of contiguous multiple high pressure, and carrying out high pressure pocket with the second high-energy injects, so that the second high pressure alloy is injected in multiple high pressure injection region, to form multiple high pressure pockets injection region of the residual photoresist of contiguous multiple high pressure.
According to some embodiment, the method for dopant implant thing comprises: on grid structure, deposit photoresist, grid structure is on substrate; Patterning photoresist, makes photoresist on a part for the end face of grid structure instead of on all parts, makes the photoresist width of photoresist be less than the grid structure width of grid structure; And in the time that photoresist is on grid structure, the first alloy is injected to substrate, to form the first doped region in the substrate of adjacent gate structures.
More than summarize the feature of multiple embodiment, made those skilled in the art can understand better many aspects of the present disclosure.Those skilled in the art will expect, they can easily use the disclosure as for designing or revise for realizing the object identical with embodiment in this introduction and/or realizing other processing of the advantage identical with it and the basis of structure.Those of skill in the art also will appreciate that, such equivalent structure does not depart from spirit and scope of the present disclosure, and they can, in the situation that not departing from spirit and scope of the present disclosure, make multiple change, replacement and change at this.
Provide the multiple operation of embodiment at this.The order of describing some or all of operations should not be interpreted as implying that these operations must be order dependent.The optional sequence of the benefit with this specification will be expected.And, will understand, not all operation all must appear in the each embodiment providing at this.And, will understand, not all operation is all necessary in certain embodiments.
To expect, in certain embodiments, for example, for the simple and intelligible object of appearance, layer described here, feature, element etc. are illustrated by the specific dimensions about another, such as, physical dimension or orientation, and its actual size is different from the size shown in figure substantially.In addition, for example, multiple technologies exist and are used to form layer described herein, feature, element etc., such as, etching technique, injection technique, doping techniques, spin coating technique, the growing technology of growing such as the sputtering technology of magnetron or ion beam sputtering, such as heat or the deposition technique such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD) or ald (ALD).
And, use " exemplary " to mean as example, example, illustration etc. at this, and must be not favourable.As used in this application, " or " refer to inclusive " or " instead of exclusiveness " or ".In addition, unless in addition or clearly to indicate from context be singulative, " one (a) " and " one (an) " that in the application and claims, use are interpreted as referring to " one or more " conventionally.And at least one in A and B etc. typically refers to A or B or A and B.And, in some sense, use " comprising (include) ", " having (having) ", " having (has) ", " having (with) " or its variant, such term is in the mode that is similar to term and " comprises (comprising) " as inclusive.And unless otherwise noted, " first ", " second " etc. are not intended to imply time aspect, aspect, space, sequence etc.But such term is only by the identifier, the title etc. that act on feature, element, item etc.For example, the first element and the second element are conventionally corresponding to element A and element B or two differences or two similar elements or identity element.
And although illustrate and described the disclosure about one or more realizations, based on the reading and understand of this specification and accompanying drawing, equivalence change and amendment will occur for those skilled in the art.The disclosure comprises all such amendments and change, and is only limited by the scope of following claim.Particularly for example, about by said modules (, element, resource etc.) carry out several functions, unless otherwise noted, even if structurally inequivalence is in disclosed structure, be intended to any assembly (for example, equivalence in function) corresponding to the appointed function of the described assembly of execution for describing the term of such assembly.In addition, although described special characteristic of the present disclosure about the only one in multiple realization, in the time may expecting and be conducive to any given or application-specific, such feature can be combined with one or more other features of other realizations.

Claims (10)

1. a semiconductor making method, comprising:
Formation has multiple the first transistors of the first operating voltage, and described multiple the first transistors are included in multiple low pressure shallow wells of the multiple first grid structures on the first transistor region of substrate, contiguous described multiple first grid structures and multiple low pressure pockets injection region of contiguous described multiple first grid structures; And
Contiguous described multiple the first transistors form multiple transistor secondses with the second operating voltage, form described multiple transistor seconds and comprise:
On described multiple first grid structures, on described the first transistor region and on multiple second grid structures, form the first high pressure photoresist, described multiple second grid structure, on the transistor seconds region of described substrate, makes to expose multiple high pressure injection region of described substrate and multiple second grids top of described multiple second grid structures of contiguous described multiple second grid structures;
Carry out high pressure LDD with the first high-energy and inject, so that the first high pressure alloy is injected in described multiple high pressure injection region, thus multiple high pressure shallow wells of the contiguous described multiple second grid structures of formation; And
Carry out high pressure pocket with the second high-energy and inject, so that the second high pressure alloy is injected in described multiple high pressure injection region, thus multiple high pressure pockets injection region of the contiguous described multiple second grid structures of formation.
2. method according to claim 1, forms described multiple the first transistor and comprises:
On described transistor seconds region and on described multiple second grid structures, form low pressure photoresist, make multiple low pressure injection region of the described substrate that exposes described multiple first grid structure and contiguous described multiple first grid structures;
Inject with the first low-yield execution low pressure LDD, so that the first voltage alloy is injected in described multiple low pressure injection region, thereby form described multiple low pressure shallow well; And
Inject with the second low-yield execution low pressure pocket, so that the second low pressure alloy is injected in described multiple low pressure injection region, thereby form described multiple low pressure pockets injection region.
3. method according to claim 1, comprising:
On described substrate, form ground floor grid dielectric material;
Remove described ground floor grid dielectric material from the described the first transistor region of described substrate, the dielectric Part I of high pressure grid is stayed on the described transistor seconds region of described substrate;
On described substrate and on the dielectric described Part I of described high pressure grid, form second layer grid dielectric material, low pressure gate-dielectric is stayed on the described the first transistor region of described substrate, and described high pressure gate-dielectric is stayed on the described transistor seconds region of described substrate, wherein, described high pressure gate-dielectric comprises described Part I and the Part II from described second layer grid dielectric material;
On described low pressure gate-dielectric and described high pressure gate-dielectric, form layer of gate electrode material; And
Layer layer of gate electrode material, described low pressure gate-dielectric and described high pressure gate-dielectric described in patterning, to form multiple first grid structures and described multiple second grid structure simultaneously.
4. method according to claim 1, comprising:
On described multiple first grid structures, described multiple second grid structures and described substrate, form side-wall material layer; And
Side-wall material layer described in patterning, to form multiple the first side wall spacers of contiguous described multiple first grid structures and multiple second sidewall spacers of contiguous described second grid structure simultaneously.
5. method according to claim 1, carries out the injection of low pressure pocket and comprises: by selected rated voltage, be infused in the dosage using in device manufacture.
6. method according to claim 1, described multiple the first transistors are different from the type of described multiple transistor secondses.
7. method according to claim 1, carries out described high pressure LDD injection and comprises: at least one of B Implanted, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon.
8. method according to claim 1, carries out described high pressure pocket injection and comprises: at least one of B Implanted, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon.
9. a semiconductor making method, comprising:
On the first transistor region of substrate and the transistor seconds region of described substrate, form the first high pressure photoresist;
The first high pressure photoresist described in patterning, to form the residual photoresist of multiple high pressure on high pressure photoresist and the described transistor seconds region on described the first transistor region, make multiple high pressure injection region of the described substrate that exposes the residual photoresist of contiguous described multiple high pressure;
Carry out high pressure LDD with the first high-energy and inject, so that the first high pressure alloy is injected in described multiple high pressure injection region, thus multiple high pressure shallow wells of the residual photoresist of the contiguous described multiple high pressure of formation; And
Carry out high pressure pocket with the second high-energy and inject, so that the second high pressure alloy is injected in described multiple high pressure injection region, thus multiple high pressure pockets injection region of the residual photoresist of the contiguous described multiple high pressure of formation.
10. a method for dopant implant thing, comprising:
On grid structure, deposit photoresist, described grid structure is positioned on substrate;
Photoresist described in patterning, makes described photoresist on the part end face instead of all end faces of described grid structure, makes the photoresist width of described photoresist be less than the grid structure width of described grid structure; And
In the time that described photoresist is on described grid structure, the first alloy is injected in described substrate, in described substrate, form the first doped region with contiguous described grid structure.
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CN112002674B (en) * 2020-10-29 2021-02-09 晶芯成(北京)科技有限公司 Method for manufacturing semiconductor device

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CN109244035A (en) * 2017-07-06 2019-01-18 世界先进积体电路股份有限公司 The manufacturing method of semiconductor device
CN107919280A (en) * 2017-11-06 2018-04-17 上海华虹宏力半导体制造有限公司 The integrated manufacturing method of different voltages device
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CN112002674B (en) * 2020-10-29 2021-02-09 晶芯成(北京)科技有限公司 Method for manufacturing semiconductor device

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