CN104049687B - Embedded cube of star house keeping computer and its reconstructing method based on FPGA - Google Patents
Embedded cube of star house keeping computer and its reconstructing method based on FPGA Download PDFInfo
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Abstract
The invention provides a kind of embedded cube of star house keeping computer based on FPGA, including process chip, the process chip to be integrated with FPGA stones, FPGA logic cell and CPU core；The FPGA stones are used to be communicated with each subsystem of peripheral circuit and cube star；The FPGA logic cell is used to be controlled the peripheral circuit, while during to the Star Service local zone time school of cube star；The CPU core is used to carry out cube star whole star control algolithm realization, whole sing data management, the realization of attitude control algorithm, control command distribution and load data management.Using flexible of the present invention, performance optimization and integrated level is high, cost is low, reliability is high.
Description
Technical field
The present invention relates to Aero-Space and electronic science and technology field, is a kind of insertion based on FPGA specifically
Formula cube star house keeping computer and its startup method and in-orbit reconstructing method.
Background technology
With the fast development of Aero-Space and electronic science and technology in recent years, low cost, low weight, high functional density
Micro-nano satellite have been widely used for earth observation, electronic reconnaissance, communication, navigation, space science detection, space exploration and new
The various fields such as engineering test, and turned into the important component of space system.And cube star is then a kind of special micro-
Nano satellite, proposed in the Bob Twiggs by Stanford University in 1999.Cube star is the cube that the length of side is 10cm, and it is consumed
Scope of the power at several watts, weight is about 1 ~ 2kg.According to the demand of task, a cube star is extended to Unit 2（Unit 1 is one
The length of side is 10cm cube）, the even Unit 6 of Unit 3.Compared with traditional Large-scale satellite, cube star development cost is low, grinds
Cycle processed is short, is easy to extend and carries flexible with separate mode.At present, cube star number mesh that statistics obtains in international coverage is
More than 200.
Because the structure of cube star is relatively simple with respect to large satellite, therefore the house keeping computer of cube star（On-Board
Computer, abbreviation OBC）Module is generally with based on central processing unit（Central Processing Unit, abbreviation CPU）Core
The single-chip microcomputer of piece realizes data processing on real-time star with reference to certain peripheral circuit（On-Board Data Handling, referred to as
OBDH）With control.However, traditional instruction system formula CPU performs reading in process instruction, with the serial mode of reading-execution
Go out instruction, and using the form response external request interrupted；This processing mode control is strong with operational capability, but SECO
Weaker, the combinational logic ability for handling complexity is weaker；The instruction cycle is longer, more than concurrent event and when interrupting frequent, often
Single-chip microcomputer disposal ability is caused to decline because processing load is overweight.With stepping up and space mission for aerospace electron integrated level
Increasingly complicated, monolithic singlechip chip has been difficult the demand of competent space mission.
Field programmable gate array（Field-Programmable-Gate-Arrays, abbreviation FPGA）, its internal logic
Array is mainly by logic unit and d type flip flop（D-flip-flop）Form, be performed in parallel matching somebody with somebody by logic unit when working on power
Function is put, therefore need not be responded in a manner of interruption, therefore FPGA has stronger processing energy to the combinational logic of complexity
Power, when Process capabi l i ty 32 it is strong；In addition, FPGA I/O numbers are more more than cpu chip, while its parallel process instruction mode is to more
I/O control has original advantage, and when CPU is managed using interrupt mode to multiple I/O, its disposal ability suffers from
Particularly apparent influence.FPGA is applied to following occasion：The management of interface（The particularly management of high-speed interface）, difference transmission speed
Coupling and the data processing of bridge joint, hardware layer between rate, different agreement, such as：Even-odd check, CRC check, EDAC verifications
Deng.But generally FPGA control ability and operational capability are weaker.
The NanoMind A712 series house keeping computers of the GomSpace companies research and development of Denmark, are provided using Atmel companies
The singlechip chip based on ARM7 CPU as core processor, be aided with certain peripheral circuit, realize relatively simple
Cube star business function.The printed circuit board (PCB) of the serial house keeping computer（Printed Circuit board, abbreviation PCB）In,
In addition to the single-chip microcomputer based on ARM7, also it is integrated with and extends out SRAM（Static Random Access
Memory, abbreviation SRAM）, magnetometer, the asic chip such as Flash memory cell, pass through PC104 interfaces and some other periphery
Interface, communication and control between cube star other subsystems are realized, and cost is relatively low（About 4500 Euros）.But its work(
Can be relatively easy with structure, the data transfer of higher speed and complicated control function can not be realized, and usable interface is less, nothing
To satellite, remaining subsystem provides enough interface supports to method, it usually needs the NanoHub that external GomSpace companies provide connects
The shortcomings that mouth mold block is to make up its interface deficiency.In addition, it uses one-chip CPU chip to realize Star Service management, energy is calculated and handled
Power is weaker.
The high-performance cube star spaceborne computers of Andrews Model 160 of the ISIS corporate agents of Holland, use
The Virtex-4 FPGA that Xilinx companies provide are kernel processor chip, integrate dual processor, and protect provided with single particle effect
Measure and watchdog circuit, self-test mistake and it can be corrected.The compatible PC104 interfaces of Andrews Model 160, handle energy
Power and data storage capacities are all very strong, and integrated level is higher, are a high performance cube of star business Computer Designs.Its shortcoming
It is：Andrews Model 160 price is very expensive（77,500 dollars）, and its using the SRAM type FPGA of high power consumption as
Core carries out design, and power consumption is very big, while SRAM type FPGA dispensing unit is very sensitive to space single particle effect, is easier to
Generation single-particle inversion（Single-Event-Upset, abbreviation SEU）Event, even if taking the radiation hardening measure on software
Also it need to be reloaded from outside EEPROM, cause the temporary transient loss of systemic-function.In addition, this house keeping computer is to China
Embargo, therefore, the high performance house keeping computer of development that the country can not use design.
The content of the invention
It is an object of the present invention to provide a kind of embedded cube of star house keeping computer based on FPGA and its reconstruct side
Method, it can be with reference to FPGA parallel processing capability and CPU control operational capability, the advantages of making FPGA and CPU complementation, fully
CPU control ability is discharged, optimizes the performance of satellited system.
To achieve the above object, the invention provides a kind of embedded cube of star house keeping computer based on FPGA, including
Process chip, the process chip are integrated with FPGA stones, FPGA logic cell and CPU core；The FPGA stones are used for
Communicated with each subsystem of peripheral circuit and cube star；The FPGA logic cell is used to carry out the peripheral circuit
Control, while during to the Star Service local zone time school of cube star；The CPU core is used to carry out cube star whole star control algolithm reality
Existing, whole sing data management, attitude control algorithm are realized, control command is distributed and load data management.
To achieve the above object, opening present invention also offers a kind of embedded cube of star house keeping computer based on FPGA
Dynamic method, comprises the following steps：（1）When house keeping computer works on power, the power subsystem of the house keeping computer is judged
Battery dump energy whether be less than predetermined threshold value, if less than if perform step（2）, otherwise perform step（3）；（2）Into peace
Syntype, the part to be communicated with communications subsystem in the house keeping computer are started working；（3）Into power on mode, from
Operation code is read in the non-volatile memory cells of the house keeping computer, the operation program and ancillary equipment of itself are driven
Initialized, step is performed after the completion of initialization（4）；（4）Into mode of operation, the mode of operation includes pose adjustment mould
At least one of formula, load modes, communication pattern and mode bus, wherein, the pose adjustment pattern is used for real-time
The in-orbit posture of satellite is adjusted, the load modes are used to realize the control and data interaction to load subsystem, the communication
Pattern is used for the control with realizing star or between star to communicate, and the mode bus is used for the data interaction for realizing bus level.
To achieve the above object, present invention also offers a kind of embedded cube of star house keeping computer based on FPGA is in-orbit
Reconstructing method, comprise the following steps：（A）Ground surface end generation matching somebody with somebody comprising FPGA logic cell and CPU core software code simultaneously
Put file；（B）Configuration file is uploaded to the communication terminal of cube star；（C）Communication terminal is calculated using UART buses and Star Service
Machine carries out data interaction, and configuration file is sent to house keeping computer；（D）Control UART stones to receive configuration file, and pass through
SPI stones store configuration file to outside flash memory；（E）Configuration information in configuration file is read one by one, write
Non-volatile memory cells inside process chip；（F）The process chip is reloaded into configuration information and completes in-orbit reconstruct.
The advantage of the invention is that：
1）Using flexible：FPGA available I/O numbers are up to hundreds of used by process chip in the present invention, and not same district
Different supply voltages can be set in the I/O in domain, so as to adapt to the demand signals of varying level standard；And in existing cube of star task
Star Service module in, using special ASIC CPU chip microcontroller Star Service management functions, although it can be by writing single-chip microcomputer
Code realizes flexibility functionally, and control ability is stronger, but the I/O of singlechip chip is limited in practical application,
I/O number demands are often difficult to meet demand when larger；
2）Performance optimizes and integrated level is high：The present invention integrates the function of FPGA logic cell and CPU core, is applying
When can carry out embedded design according to the actual requirements, FPGA logical code and CPU software are write respectively, according to respective disposal ability
Advantage and disadvantage carry out the task division of labor so that the Performance optimization of system, and FPGA and CPU are integrated in chip piece, can be significantly
Improve the integrated level of circuit；And existing singlechip chip uses the processing mode of serial execute instruction, concurrent event when property is handled
Can be poor, when concurrent event occurs frequent, the disposal ability of singlechip chip and flexibility suffer from larger limitation；
3）Cost is low：Process chip of the present invention can use the Flash types that Microsemi companies provide
SmartFusion2 FPGA, the Smartfusion2 FPGA of monolithic technical grade price are about 1000 ~ 2000 yuan, with single-chip microcomputer
The price of chip is suitable, or even low, and its flexibility is big, can meet the needs of different task, can reduce secondary development into
This；
4）Reliability is high：By taking radiation hardening measure to FPGA logic cell and CPU core software, it is ensured that be
When in space environment by high-energy particle bombardment single event is occurred for system, the reliability of guarantee system is remained able to.
Brief description of the drawings
Fig. 1, the Organization Chart of the embedded cube of star house keeping computer of the present invention based on FPGA.
Fig. 2, it is of the present invention that schematic diagram is reinforced to FPGA logic cell；
Fig. 3, it is of the present invention that EDAC checking process figures are carried out to SRAM；
Fig. 4, the startup method flow diagram of the embedded cube of star house keeping computer of the present invention based on FPGA；
Fig. 5, the embedded cube of star house keeping computer in-orbit reconstructing method flow chart of the present invention based on FPGA.
Abbreviation and Key Term definition：
OBC：On-Board Computer house keeping computers
OBDH：Data processing on On-Board Data Handling stars
ADC：Amplitude-Digital-Convertor amplitude digitizers
FPGA：Field-Programmable-Gate-Arrays field programmable gate arrays
CPU：Central Processing Unit central processing units
SEU：Single-Event-Upset single-particle inversions
SRAM：Static Random Access Memory SRAMs
PCB：Printed Circuit board printed circuit board (PCB)s
SPI：Serial Peripheral Interface peripheries serial line interface
UART：Universal Asynchronous Receiver ＆ Transmitter UART Universal Asynchronous Receiver Transmitters
CAN：Control Area Network controller LAN serial communications
I2C bus：Inter Integrated Circuits bus bidirectional two-line serial communication bus
Flash Memory：Flash memory.
Embodiment
Below in conjunction with the accompanying drawings to the embedded cube of star house keeping computer provided by the invention based on FPGA and its reconstruct side
The embodiment of method elaborates.
Referring to Fig. 1, the Organization Chart of the embedded cube of star house keeping computer of the present invention based on FPGA, including processing
Chip 10, the process chip 10 are integrated with FPGA stones, FPGA logic cell and CPU core 11；Namely the Star Service meter
Calculation machine is using FPGA as kernel processor chip.The FPGA stones are used to be led to each subsystem of peripheral circuit and cube star
Letter；The FPGA logic cell is used to be controlled the peripheral circuit, while during to the Star Service local zone time school of cube star；
The CPU core 11 is used to carry out cube star whole star control algolithm realization, whole sing data management, the realization of attitude control algorithm, control
Order distribution and load data management.Wherein, stone (Hard IP Core) refers to layout in FPGA designs and technique is consolidated
Design that is fixed, being verified by front-end and back-end.In the present invention, FPGA logic cell and CPU core combine, and realize the whole of cube star
Star controls and data management, complementary the advantages of FPGA and CPU, fully release CPU control ability, optimizes the performance of system.
In the present invention, the CPU core can use ARM Cortex-M3 processor cores.The process chip can
With the Flash type SmartFusion2 FPGA provided using Microsemi companies, using more than its I/O number and integrated ARM
The advantages of Cortex-M3 processor cores, it can make with reference to FPGA parallel processing capability and CPU control operational capability
The advantages of FPGA and CPU, is complementary, fully discharges CPU control ability, optimizes the performance of satellited system.Meanwhile CPU and FPGA
It is integrated in on a ASIC device, improves satellited system integrated level and functional density.In addition, utilize Flash types FPGA's
Low-power consumption, repeatable programming, anti-space radiation ability more by force with safe advantage, it is possible to provide a kind of low-power consumption, low cost,
Design flexibility is compared with strong and high integrated level cube star house keeping computer.In Flash type FPGA Smartfusion2-M2S050T
In realize embedded cube of star business computer module；Using Smartfusion2 ARM Cortex-M3, I2C, SPI,
The kernels such as CAN, UART, counter, with reference to FPGA logic unit, it is subject to radioresistance while being aided with certain peripheral circuit and adds
Fixed meter, complete embedded cube of star business system for computer design.Realizing as described in the present invention based on FPGA's
During the function of embedded cube of star house keeping computer, other models are used to integrate the Flash types FPGA of ARM CPU cores（Such as
Fusion series and Smart Fusion series）, identical purpose can be reached.
In the present invention, the process chip and the peripheral circuit are integrated in a block size and are less than 10*10cm2Printing
In circuit board, the integrated level of circuit is greatly improved.
APB (Advanced Peripheral Bus, On-Chip peripheral bus) is mainly used in piece at a slow speed in APB@AHB in figure
The communication of upper peripheral hardware and ARM cores；AHB (Advanced High performance Bus, high performance bus) is mainly used in system
High-performance, high clock rate intermodule communication.
The FPGA stones of the process chip 10 include I2C stones 12, UART stones 13, SPI stones 14, CAN stones 15
With timer stone 16.The FPGA stones in process chip 10 and CPU core 11 is called to carry out embedded Star Service Design assistant
Function Extension, the FPGA for completing the C language housekeeping software Code Design of CPU core 11 and being carried out based on programmable logic cells
Hardware identification code designs, to reduce the demand to peripheral circuit.In the present invention, the peripheral circuit includes flash memory 21, width
Spend digital quantizer 22, SRAM 24, SD card 25 and CAN transceiver 26.
The I2C stones 12 are used to realize cube star satellited system I2C bus datas transmitting-receiving and communicated with each subsystem；
Each subsystem can receive instruction and the return information that satellited system is distributed by I2C buses and I2C stones 12.It is described
UART stones 13 are used to realize the Point-to-Point Data Transmission cube between star satellited system and each subsystem, with adapt to data volume compared with
Big transmission demand.The SPI stones 14 are used to be communicated with the flash memory 21 and the SD card 25；It is described
SPI stones 14 also provide Peripheral extension ability for satellited system.The function of the CAN stones 15 and the I2C stones
12 is similar, for realizing cube star business system CAN bus data transmitting-receiving and being communicated with each subsystem；But the CAN is hard
The CAN transmission data rate of core 15 is high more than I2C buses, and integrated CAN stones 15 can expand the total of cube star satellited system
Line ability.The timer stone 16 is used to provide regular time bat to cube star business software, makes housekeeping software according to solid
Fixed sequential performs Star Service function.
The flash memory 21 is used to store Star Service code, namely the software code of the storage CPU core 11 and
The configuration code of the FPGA logic cell.The amplitude digitizer 22 is used for the simulation to each system on cube star in real time
Amount is acquired, to feed back working condition of cube star at current time；Moulds of the 16 road ADC to feedback instantaneous operating conditions on star
Analog quantity is acquired, and the temperature sensor 23 of two coupled passages then provides the real-time monitoring simulation of temperature for satellited system
Amount.The SRAM 24 is used for the operation code and real time data for storing cube star attitude control subsystem, for described
CPU core 11 calls；The SRAM 24 use 4MBytes SRAM for attitude control subsystem provide software code and
The memory space of data.The SD card 25 be used for store cube spaceborne lotus subsystem real time data, with etc. be sent to ground
End；The CAN transceiver 26 is used to provide CAN driving and receive capabilities, ensures the data transmission and reception energy of CAN
Power.In addition, house keeping computer of the present invention and the communication of remaining subsystem are then realized by PC104 sockets 27.
In the present invention, in addition to using house dog design to system progress reinforcement measure.Therefore, the peripheral circuit enters one
Step includes hardware watchdog 28, and the hardware watchdog 28 is used to be monitored a cube star business system, in a cube star software
System exports reset signal in time when running winged makes software systems recover to original state.When satellited system is run, hardware watchdog
28 counters of itself are added up, and process chip 10 needs timing to send reset signal to hardware watchdog 28, if process chip
System, which is run, in 10 flies and fails to send watchdog zero clearing signal in time, then hardware watchdog 28 is forced to answer process chip 10
Position.House dog design in the present invention can also include the software watchdog inside process chip 10, such as FPGA logic cell
With CPU core 11 can each other as software watchdog, when a side is run winged by external interference, by the opposing party to progress
Operation is resetted, without being resetted to both sides via hardware watchdog 28 simultaneously, to improve the reliability of satellited system.With reference to
Hardware watchdog 28 then can further improve the reliability of whole star.
It is relatively low that the embedded cube of star house keeping computer of the invention based on FPGA is primarily adapted for use in the radiation such as LEO
Application scenario, because hardware is mostly based on technical grade even business level chip on star, it is anti-to be aided with redundancy, reconstruct, house dog etc.
Radiation hardened measure, single-particle radiation hardening is done to FPGA logic cell and CPU core, improved to the radiation of space single-particle
Immunity is to improve system reliability.Radiation hardening measure includes：Triplication redundancy is done to the key component of FPGA logic cell,
Input and output are done with single event transient pulse filtering, CRC check is done to interactive data；The software code of CPU core is stored
SRAM do EDAC verifications, software trap is set to software code to handle because of interruption caused by single particle effect, it is and foregoing
Setting software watchdog with system run fly when resetted in time.
It is of the present invention that schematic diagram is reinforced to FPGA logic cell referring to Fig. 2.House keeping computer of the present invention enters one
Step includes triplication redundancy module 201 and filter circuit 202, adds for carrying out single-particle radioresistance to the FPGA logic cell
Gu.The triplication redundancy module 201 is used for the redundancy that three times module is carried out to the FPGA logic cell, and selects two using three
Mechanism obtains output result；The redundancy of three times module can be carried out for the key position of logic.The filter circuit 202 is used for
Single event transient pulse filtering is done in input and output to the FPGA logic cell；I.e. by input signal one-to-two, to wherein one
Road is delayed, when detecting this two paths of signals while state changes than before, just upset output state, with filter out because
The radiation-induced FPGA logic cell glitch noise of space single-particle.In the present invention, the output I/O for all FPGA is carried out
Single event transient pulse filters out operation.When carrying out single-particle radiation hardening to the present invention, redundancy is carried out using multiple devices
Without being designed in FPGA logic cell, identical purpose can be achieved in the two for design.The anti-spoke of single-particle is being carried out to the present invention
When penetrating reinforcing, Redundancy Design is carried out without being designed in FPGA logic cell using multiple devices, identical can be achieved in the two
Purpose.
House keeping computer of the present invention further comprises CRC check module（Not shown in figure）, the CRC check mould
Block is used to carry out CRC check to the data of interaction on cube star；Such as to on UART, I2C, CAN and spi bus on cube star
Interactive data carry out CRC check.On the implementation, the CRC check module can be realized by software program, or to described
FPGA logic cell is programmed realization.Detected by CRC check algorithm for the data received on cube star, only passed through
The data of CRC check are only valid data；For the data sent on cube star, then CRC codings, coded data are carried out in advance
Position is sent jointly with check bit.
House keeping computer of the present invention further comprises EDAC correction verification modules（Not shown in figure）, the EDAC verifications
Module is used to before operation code and real time data are stored in the SRAM 24 carrying out EDAC codings, and from institute
State when SRAM 24 reads data and carry out EDAC inspections.On the implementation, the EDAC correction verification modules can be by soft
Part program is realized, or is programmed realization to the FPGA logic cell.In the present invention, house keeping computer after the power-up, is run
Code and real-time data memory are in SRAM, to ensure satellited system reliability of operation, add the EDAC verifications of SECDED
To be reinforced.
It is of the present invention that EDAC checking process figures are carried out to SRAM referring to Fig. 3.Before data are stored in SRAM, all to it
Carry out EDAC codings.When reading data from SRAM, EDAC check algorithms are carried out first, if finding no the data bit of mistake,
Then directly read data；If it was found that there is a bit-errors position, data are read after correcting the error bit, and the data after correction are write
Return to the original address for storing the data；If it was found that there is the error bit of more than two, single-particle inversion fault interrupt is produced, is made
CPU core re-starts loading.
In addition, heretofore described FPGA logic cell can be realized to extending out SRAM's by writing VHDL hardware identification codes
Control and the management of EDAC verifications, 16 road ADC control, hardware watchdog and SD card, while school is carried out to Star Service local zone time
When.The logic unit and I/O pins of the repeatable configurations of FPGA, can not only provide larger design flexibility, may also provide extension
UART buses, I2C buses, the ability of CAN and spi bus port number.
Present invention also offers a kind of method of work of house keeping computer, suitable for of the present invention based on the embedding of FPGA
Enter formula cube star house keeping computer.
With reference to figure 4, the startup method flow diagram of the embedded cube of star house keeping computer of the present invention based on FPGA.
It the described method comprises the following steps：When house keeping computer works on power（S40）, judging that the power supply of the house keeping computer divides is
Whether the battery dump energy of system is less than predetermined threshold value（S41）, if performing step S42 less than if, otherwise perform step S43.
S42：Into safe mode, the part to be communicated in the house keeping computer with communications subsystem is started working；Namely electricity
It is insufficient then enter safe mode, until switching to power on mode after battery capacity is enough.S43：Into power on mode, from the star
It is engaged in reading operation code in the memory cell of computer, operation program and the ancillary equipment driving to itself initialize, just
Beginningization is completed（S44）Step S45 is performed afterwards.S45：Into mode of operation, the mode of operation includes pose adjustment pattern, load
At least one of pattern, communication pattern and mode bus；Wherein, the pose adjustment pattern is used to adjust satellite in real time
In-orbit posture, the load modes are used to realize control and data interaction to load subsystem, and the communication pattern is used for
The control with realizing star or between star to communicate, the mode bus are used for the data interaction for realizing bus level；Above-mentioned pattern can lead to
Cross and write corresponding software code and fpga logic and be achieved.After cube star enters mode of operation, can also further it sentence
Whether the battery dump energy of the disconnected power subsystem is less than the predetermined threshold value（S46）, if the execution step S42 less than if；
If that is, into the not enough power supply of the battery of discovery power-supply system after mode of operation, into safe mode, wait electricity sufficient
Exit safe mode again afterwards.
The present invention utilizes Flash types FPGA reconfigurable characteristic, can carry out the in-orbit reconstruct of house keeping computer, with
Improve the in-orbit application flexibility and reliability of cube star.House keeping computer of the present invention for FPGA logic cell and
CPU core is set and reconfigures function, and reading configuration information in the flash memory when needing reconstruct from peripheral circuit is carried out
Reload.
With reference to figure 5, the embedded cube of star house keeping computer in-orbit reconstructing method flow of the present invention based on FPGA
Figure, the in-orbit reconstructing method of house keeping computer, it is engaged in calculating using the embedded cube of star of the present invention based on FPGA
Machine.The reconstructing method comprises the following steps：1）Ground surface end generation includes FPGA logic cell and CPU core software code simultaneously
Configuration file；2）Configuration file is uploaded to the communication terminal of cube star；3）Communication terminal utilizes UART buses and Star Service meter
Calculation machine carries out data interaction, and configuration file is sent to house keeping computer；4）Control UART stones to receive configuration file, and pass through
SPI stones store configuration file to outside flash memory；5）Configuration information in configuration file is read one by one, at write-in
Manage the non-volatile memory cells of chip internal；6）The process chip is reloaded into configuration information and completes in-orbit reconstruct.By
Memory cell more than one in FPGA, only non-volatile memory cells are for storage configuration information.
, can be certainly when the process chip of the embedded cube of star house keeping computer of the present invention based on FPGA works on power
It is dynamic to read configuration information from its internal non-volatile memory cells, FPGA logic cell and CPU core are initialized,
Flash memory outside piece is used for the configuration data for storing backup.
The Flash type SmartFusion2 FPGA provided using Microsemi companies need to update configuration information to Star Service
When module is reconfigured, it need to be carried out according to below scheme：
1）Integrated software Libero SOC 11.2 are compiled in ground surface end operation Smartfusion2, in the integrated software
The software code of FPGA logic cell and ARM CPU is redesigned respectively, generation afterwards comprising FPGA logic cell and
The configuration file of CPU core software programming code；
2）Communicated by earth station with a cube star, configuration file is uploaded to the communication terminal of cube star；
3）Communication terminal carries out data interaction using UART buses and house keeping computer of the present invention, by configuration file
Send to house keeping computer；
4）ARM Cortex-M3 CPU cores control UART stones in the fpga chip of house keeping computer receive configuration text
Part, and the flash memory to outside piece is stored configuration file by SPI stones and spi bus；
5）CPU core controls the flash memory after more new configuration file by spi bus, and configuration information is read one by one
Go out, write in the non-volatile memory cells inside fpga chip；
6）After CPU core is fully completed to non-volatile memory cells read-write operation in flash memory outside piece and piece,
Fpga chip is reloaded into configuration information, that is, the in-orbit of fpga chip for completing house keeping computer reconfigures.
Wherein, above-mentioned reconstruct flow is the control that the CPU core being internally integrated using fpga chip completes above-mentioned function,
Highly reliable peripheral control unit chip can also be used in other embodiment to realize.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (8)
- A kind of 1. embedded cube of star house keeping computer based on FPGA, it is characterised in that including process chip, the processing core Piece is integrated with FPGA stones, FPGA logic cell and CPU core；The FPGA stones are used to be communicated with each subsystem of peripheral circuit and cube star；The FPGA logic cell is used to be controlled the peripheral circuit, while to the Star Service local zone time school of cube star When；The CPU core is used to carry out cube star whole star control algolithm realization, whole sing data management, the realization of attitude control algorithm, control System order distribution and load data management；The FPGA stones include I2C stones, UART stones, SPI stones, CAN stones and timer stone, the periphery electricity Road includes flash memory, amplitude digitizer, SRAM, SD card and CAN transceiver；The I2C stones are used to realize cube star satellited system I2C bus datas transmitting-receiving and communicated with each subsystem；It is described UART stones are used for Point-to-Point Data Transmission of the realization cube between star satellited system and each subsystem；The SPI stones are used for Communicated with the flash memory and the SD card；The CAN stones are used to realize a cube star business system CAN bus Data transmit-receive and communicated with each subsystem；The timer stone is used to provide regular time to cube star business software Clap；The flash memory is used to store the software code of the CPU core and the configuration code of the FPGA logic cell； The amplitude digitizer is used in real time be acquired the analog quantity of each system on cube star, to feed back cube star current The working condition at moment；The SRAM is used for the operation code and number in real time for storing cube star attitude control subsystem According to so that the CPU core calls；The SD card be used for store cube spaceborne lotus subsystem real time data, with etc. it is to be sent To ground surface end；The CAN transceiver is used to provide CAN driving and receive capabilities；The house keeping computer further comprises triplication redundancy module and filter circuit；The triplication redundancy module, for pair The FPGA logic cell carries out the redundancy of three times module, and obtains output result using three mechanism for selecting two；The filtered electrical Road, single event transient pulse filtering is done for the input and output to the FPGA logic cell.
- 2. embedded cube of star house keeping computer according to claim 1, it is characterised in that the peripheral circuit is further Including hardware watchdog, the hardware watchdog is used to be monitored a cube star business system, is run in cube star software systems Exporting reset signal when winged in time makes software systems recover to original state.
- 3. embedded cube of star house keeping computer according to claim 1 or 2, it is characterised in that the fpga logic list First and described CPU core software watchdog each other.
- 4. embedded cube of star house keeping computer according to claim 1, it is characterised in that the house keeping computer enters one Step includes CRC check module, and the CRC check module is used to carry out CRC check to the data of interaction on cube star.
- 5. embedded cube of star house keeping computer according to claim 1, it is characterised in that the house keeping computer enters one Step includes EDAC correction verification modules, and the EDAC correction verification modules are used to deposit in operation code and the real time data deposit static random EDAC codings are carried out before reservoir, and EDAC inspections are carried out when reading data from the SRAM.
- A kind of 6. startup method of the embedded cube of star house keeping computer based on FPGA, applied to as claimed in claim 1 The embedded cube of star house keeping computer based on FPGA, it is characterised in that comprise the following steps：(1) when house keeping computer works on power, judging the battery dump energy of the power subsystem of the house keeping computer is It is no to be less than predetermined threshold value, if performing step (2) less than if, otherwise perform step (3)；(2) safe mode is entered, the part to be communicated in the house keeping computer with communications subsystem is started working；(3) enter power on mode, operation code read from the non-volatile memory cells of the house keeping computer, to itself Operation program and ancillary equipment driving are initialized, and step (4) is performed after the completion of initialization；(4) mode of operation is entered, the mode of operation includes pose adjustment pattern, load modes, communication pattern and bus mould At least one of formula, wherein, the pose adjustment pattern is used for the in-orbit posture for adjusting satellite in real time, the load modes For realizing control and data interaction to load subsystem, the communication pattern is used for the control with realizing star or between star to communicate System, the mode bus are used for the data interaction for realizing bus level.
- 7. the startup method of house keeping computer according to claim 6, it is characterised in that step (4) further comprises, sentences Whether the battery dump energy of the disconnected power subsystem is less than the predetermined threshold value, if the execution step (2) less than if.
- A kind of 8. embedded cube of in-orbit reconstructing method of star house keeping computer based on FPGA, applied to as claimed in claim 1 The embedded cube of star house keeping computer based on FPGA, it is characterised in that comprise the following steps：(A) ground surface end generation includes the configuration file of FPGA logic cell and CPU core software code simultaneously；(B) configuration file is uploaded to the communication terminal of cube star；(C) communication terminal carries out data interaction using UART buses and house keeping computer, and configuration file is sent to Star Service and calculated Machine；(D) control UART stones to receive configuration file, and stored configuration file to outside flash memory by SPI stones；(E) configuration information in configuration file is read one by one, the non-volatile memory cells write inside process chip；(F) process chip is reloaded into configuration information and completes in-orbit reconstruct.
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| CN111309477B (en) * | 2020-02-13 | 2023-04-21 | 中国科学院微小卫星创新研究院 | Satellite in-orbit data processing system and method |
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