CN108100308B - Reconfigurable veneer skin satellite system - Google Patents

Reconfigurable veneer skin satellite system Download PDF

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CN108100308B
CN108100308B CN201711280404.0A CN201711280404A CN108100308B CN 108100308 B CN108100308 B CN 108100308B CN 201711280404 A CN201711280404 A CN 201711280404A CN 108100308 B CN108100308 B CN 108100308B
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module
data
satellite
communication
processing unit
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CN108100308A (en
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高武
姜东蛟
葛兴
彭驰葳
费彬
赵晨
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Northwestern Polytechnical University
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B64AIRCRAFT; AVIATION; COSMONAUTICS
    • B64GCOSMONAUTICS; VEHICLES OR EQUIPMENT THEREFOR
    • B64G1/00Cosmonautic vehicles
    • B64G1/10Artificial satellites; Systems of such satellites; Interplanetary vehicles
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B64AIRCRAFT; AVIATION; COSMONAUTICS
    • B64GCOSMONAUTICS; VEHICLES OR EQUIPMENT THEREFOR
    • B64G1/00Cosmonautic vehicles
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Abstract

The invention provides a reconfigurable single-board satellite system, which relates to the field of design and development of spacecrafts, and is characterized in that a functional module required by a satellite space task is integrated on a single board based on a printed circuit satellite structure, all logic and control are realized by using an FPGA (field programmable gate array), and meanwhile, the fault-tolerant capability of a processor is improved by using the IP (Internet protocol) kernel development of the processor based on the single-board satellite of the FPGA, and a software secondary development mode; the invention realizes the control of the computer system to each subsystem by connecting the scheduling bus controller with each module, has the characteristics of simple structure, high integration, small volume, low power consumption and low cost, realizes the reconfiguration of the processor by using the FPGA to realize that different manufacturers provide processor IP cores with different architectures, and improves the fault-tolerant capability of the processor by adopting the anti-radiation technology to carry out secondary development on the processor IP cores; and according to the pico-satellite sensor and the measurement function, hardware realization of different types of algorithms is completed by adopting the FPGA.

Description

Reconfigurable veneer skin satellite system
Technical Field
The invention relates to the field of spacecraft design and development, in particular to a pico-satellite system.
Background
Pico-satellites generally refer to microsatellites with a mass of less than 1 kilogram and having a special functional task. Currently, the mainstream technology for pico-satellite design is the cubic satellite technology. The cube star technology is used for providing the most basic and necessary design outline and guidance for different developers, and the size of the pico-satellite is clearly defined. A single-board satellite is also one of pico-satellites, and in order to further improve the integration level and reduce the power consumption and the cost, Barnhart D J, Vladimirova T, Baker A M, et al.A low-cost femto satellite to enable distributed space satellites [ J ]. Acta Astronautica,2009,64 (11-12): 1123-1143. the design of a printed-board circuit satellite is described, and basic functional modules required by the satellite are integrated on a PCB board of 10cm multiplied by 10cm, so that the low cost and the mass production of the satellite are realized. The printed circuit board circuit is provided with a power supply system for charging regulation and peak power tracking, a communication system integrating a ZigBee module, an iTraX-03S single-mode GPS receiver, a Sarantel antenna and a posture control system of a single-axis magnet, adopts a Mega128L RISC microcontroller of Atmel company as a data processing center, and carries a CMOS image sensor payload.
However, the printed circuit satellite is an integrated electronic system based on the MCU, cannot be reconstructed, is not beneficial to the anti-radiation reinforcement design, and generally adopts a multi-mode redundant system structure, so that the original cost is increased, and the power consumption and the area of the system are also increased. In addition, the design is not well suited for the migration of other processors, such as if the processing module is replaced, the entire circuit needs to be redesigned, increasing the design cost.
Disclosure of Invention
In order to overcome the defects of the prior art and aim at the characteristics of the pico-satellite in terms of volume, quality, integration level and the like, the invention provides a reconfigurable single-slab pico-satellite system, which is based on a printed circuit satellite structure, uses the most basic independent function module required by a commercial off-the-shelf pico-satellite space task on a single slab, and realizes all logic and control by using an FPGA (field programmable gate array), so that the system has certain reliability, the integration level of the single slab satellite is improved, the rapid emission of the satellite is realized, meanwhile, the single slab satellite based on the FPGA is developed by using an IP (Internet protocol) core of a processor, the transplantation of different processors is easy to realize, and the fault-tolerant capability of the processor can also be improved by.
The technical scheme adopted by the invention for solving the technical problems is as follows:
the invention relates to a reconfigurable veneer skin satellite system which comprises a digital data processing module, a data storage module, a communication module, a voltage generation module, a GNC module and a camera module, wherein the digital data processing module comprises a power management controller, a calculation processing unit, a camera preprocessing unit and a bus controller; when the current electric quantity is detected to be higher than a set high threshold value, the satellite is fully charged by the solar battery on the current day, and the system power supply is controlled according to the current satellite electric quantity; the computing processing unit adopting the IP core is the core of the digital data processing module and is a task management and algorithm execution unit; the camera preprocessing unit is used for processing data from original photo data in the camera module to a decoding chip so that the data format of the photo meets the JPEG2000 standard, and the bus controller is used for providing interfaces between the digital data processing module and other modules;
all logics and controls in the digital data processing module are realized by using FPGA, the FPGA is used for dynamic management of a power supply, so that the power supply management controller is realized, a processor IP core is used as a CPU (Central processing Unit), namely a calculation processing unit, data is preprocessed, namely a camera preprocessing unit, and a bus controller is realized according to I2C, UART (Universal asynchronous receiver/transmitter) and SPI (Serial peripheral interface) bus time sequences, wherein when the processor IP core is used, in order to increase the fault-tolerant capability of the calculation processing unit, full redundancy processing is carried out on the IP core, namely, the processor core is copied into three parts, the three processor cores respectively execute the same program, share data and program storage, and triple modular redundancy is realized;
the data storage module comprises a FLASH chip and a peripheral circuit and is used for storing parameters during the initialization of the single-board satellite, data after picture compression coding and geomagnetic field data required by attitude orbit control;
the communication module comprises WIFI, UHF and S waveband modules and is used for ground test of the functions of the single-board satellite, receiving and sending of instructions and interaction of short-distance and main satellite data information, switching is controlled through a calculation processing unit in the digital data processing module, namely, an enabling switch of the connection module is connected, different enabling switches are enabled through different communication distances, namely, the communication is in WIFI communication, the calculation processing unit is informed through WIFI communication, when the communication is switched to an S waveband, the calculation processing unit enables the S waveband module to be opened, the connection between the S waveband module and the outside is reestablished, the WIFI communication is disconnected, and the working state of the single-board satellite is transmitted to a ground PC or a main satellite through the communication module by using three communication modules of WIFI, UHF and S;
the voltage generation module is used for providing voltage required by the integral power supply of the single-board satellite and independently supplying power for each module in the single-board pico-satellite system, and the digital circuit, the analog circuit and the high-frequency communication module are designed separately, wherein the analog voltage meeting the precision and noise requirements is obtained by boosting the analog power through the DC-DC converter and then reducing the voltage through the LDO for the system to use, the digital circuit is used for converting the DC-DC converter into the LDO for the system to use, and the high-frequency communication directly uses the voltage required by the high-frequency communication output by the DC-DC converter;
the GNC module acquires magnetic field information, rotation quantity and acceleration of a current single-plate satellite, namely acquires the motion state and position information of the current satellite;
the camera module is used for acquiring a single-board satellite image, completing image acquisition and image data compression, transmitting the photographed image data to a camera preprocessing unit of the digital data processing module after the camera photographs, preprocessing the data, namely extracting image gray data, so that the data format of the image data meets the JPEG2000 standard, and transmitting the preprocessed data to the camera module for compression coding;
after the system is powered on, the voltage generation module generates voltages required by the operation of each module, all the systems are powered on to operate, when a measurement and control system on the ground or a main satellite sends an instruction, the instruction is received by the communication module and transmitted to the digital data processing module, the instruction is analyzed and recognized by the calculation processing unit in the digital data processing module, if the instruction is a camera instruction, the camera module is controlled to take a picture to obtain picture data, if the instruction is a GNC instruction, data reading and data storage are carried out through the GNC module, data needing to be accessed are stored in the data storage module through the calculation processing unit, and the read data and the picture data are both sent through the communication module.
The invention uses ADC to collect solar energy patch voltage V1, the reference voltage of ADC is analog voltage V2 obtained by LDO,the noise of LDO is Root Mean Square (RMS), and the conversion formula of ADC is
Figure BDA0001497393130000031
Where M is a digital code, K is a performance parameter of the ADC, and using an n-bit ADC, the value of K is 2nDividing (V2-RMS) into 2nAnd obtaining the digital code through a conversion formula.
The invention has the advantages that the bus controller is connected with each module through the dispatching bus, thereby realizing the control of the computer system on each subsystem, having the characteristics of simple structure, high integration, small volume, low power consumption and low cost, being suitable for the space networking pico-satellite, compared with the printed board circuit satellite, all logic and control operation circuits are realized in the FPGA according to the specific task requirements, the FPGA can realize that different manufacturers provide processor IP cores with different architectures, the reconfiguration of the processor is realized, and simultaneously, the radiation-resistant technology can be adopted to carry out secondary development on the processor IP cores so as to improve the fault-tolerant capability of the processor; according to the pico-satellite sensor and the measurement function, the FPGA is adopted to complete hardware realization of different types of algorithms.
Drawings
Fig. 1 is a block diagram of a single-board satellite system.
Fig. 2 is a schematic diagram of an implementation of the digital data processing module.
FIG. 3 is a block diagram of a DATA storage connection, where WP is a write protect signal, WE is write enable, ALE is address issue enable, CLE is command issue enable, RE is read enable, R/B is busy ready, CE is chip select, and DATA is DATA.
Fig. 4 is a block diagram of a communication module, wherein the UART is a communication asynchronous transceiver and the SPI is a serial asynchronous interface.
Fig. 5 is a block diagram of a voltage generation module, where DC-DC is a DC-DC conversion chip, and LDO is a low dropout linear regulator.
FIG. 6 is a connection diagram of the GNC module and the bus controller, and I2C is an Inter Integrated Circuit, which represents a synchronous serial bus; GPIO is General Purpose Input Output, which represents a General Purpose Input/Output interface; GNC stands for attitude trajectory control.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
The invention provides a reconfigurable veneer pico-satellite system aiming at the characteristics of pico-satellite volume, quality, integration level and the like, wherein a high-reliability veneer satellite system module comprises a digital data processing module, a data storage module, a communication module, a voltage generation module, a GNC module and a camera module, wherein the digital data processing module comprises a power management controller, a calculation processing unit, a camera preprocessing unit and a bus controller; when the current electric quantity is detected to be higher than a set high threshold value, the satellite is fully charged by the solar battery on the current day, and the system power supply is controlled according to the current satellite electric quantity; the computing processing unit adopting the IP core is the core of the digital data processing module and is a task management and algorithm execution unit; the camera preprocessing unit is used for processing data from original photo data in the camera module to a decoding chip so that the data format of the photo meets the JPEG2000 standard, and the bus controller is used for providing interfaces between the digital data processing module and other modules;
all logics and controls in the digital data processing module are realized by using FPGA, the FPGA is used for dynamic management of a power supply, so that the power supply management controller is realized, a processor IP core is used as a CPU (Central processing Unit), namely a calculation processing unit, data is preprocessed, namely a camera preprocessing unit, and a bus controller is realized according to I2C, UART (Universal asynchronous receiver/transmitter) and SPI (Serial peripheral interface) bus time sequences, wherein when the processor IP core is used, in order to increase the fault-tolerant capability of the calculation processing unit, full redundancy processing is carried out on the IP core, namely, the processor core is copied into three parts, the three processor cores respectively execute the same program, share data and program storage, and triple modular redundancy is realized;
the digital data processing module realizes the reconfigurable design and the complex data and control algorithm of the single-board satellite in the FPGA. In the principle prototype stage, in order to reduce the cost, an Altera Cyclone IV series FPGA based on SRAM is adopted, and then an anti-fuse type FPGA with radiation resistance is used. And the power management controller, the camera preprocessing unit, the calculation processing unit based on the IP core and the bus controller in the digital data processing module are integrated to realize the whole data processing in the FPGA. The digital data processing module in the structure of fig. 1 describes the connections between the internal sub-modules, and fig. 2 shows the specific implementation of the internal sub-modules of the digital data processing module.
The power supply management controller controls the power supply condition of the satellite, and the maximum reduction of power supply of the satellite is ensured on the premise of normal work. The computer processing unit monitors the current satellite electric quantity state information, when the current electric quantity is detected to be lower than a set low threshold value, the current satellite electric quantity is insufficient, the power management controller conducts power-off processing on a current non-working module through the control voltage generation module, and the solar battery is waited for charging; when the current power is detected to be higher than the design high threshold, it indicates that the satellite is fully charged by the current solar cell.
For the use and verification of the MSP430 in the cube star, the invention adopts an MSP430IP core as a computing processing unit, wherein, for different space tasks, an IP core of the computing processing unit can be replaced by an IP core with different architectures. The computing processing unit is mainly responsible for coordination of various system modules, execution of GNC algorithm and operation of management software. Further, when the processor IP core is used, in order to increase the fault-tolerant capability of the computing processing unit, the IP core is subjected to full redundancy processing.
The bus controller is mainly used for providing an interface for data exchange between the digital data processing module taking the computing processing unit as a core and other systems, and controlling the I2C, the UART, the SPI and the GPIO interface.
The camera preprocessing unit completes initialization of an image compression chip, camera photographing control, data caching and forwarding according to an image processing algorithm, uses a hardware circuit to quickly process picture information, and sends the picture information to the calculation processing unit;
firstly, writing the required data into FLASH by using a FLASH writing program, then downloading a software program, and covering the program; reading a flag bit in the FLASH every time the software program is operated, wherein the flag bit is not identified when the software program is operated for the first time, writing intermediate data to FLASH operation is carried out in the software program operation, the FLASH data is replaced, and the flag bit is identified; when the power is off and then the power is on, the software program is still operated, when the operation is started, the flag bit is read from the FLASH, the flag bit in the FLASH at the moment can be identified through the last operation, whether the flag bit read from the FLASH is identified or not is judged, and then the subsequent operation is executed. In this embodiment, the flag information is exemplified in addition to the constant information. If repeated, the number of the current signals can be increased or decreased according to actual conditions.
The data storage module comprises a FLASH chip and a peripheral circuit and is used for storing parameters during the initialization of the single-board satellite, data after picture compression coding and geomagnetic field data required by attitude orbit control;
the data storage module is used for increasing the storage capacity of nonvolatile data, and consists of a Flash memory chip and a peripheral circuit thereof, and as shown in fig. 3, the data storage module is connected with the calculation processing unit. The computing processor unit is connected with a data storage module Flash memory chip through a 15-bit parallel data/control bus. Including a 1-bit chip select signal, a 6-bit control signal, and an 8-bit data signal. For storing initial operating parameter values, images and earth magnetic field data. Flash adopts a three-star K9F4G08U0M chip, the Flash is divided into three blocks according to the address space according to the storage size space, three data backups are stored in three different address spaces of the Flash when data are stored each time, data are respectively obtained from three areas in the Flash when a computing processing unit reads the data from the Flash at any moment, three-out-of-two processing is carried out on three groups of data, two groups of same data are used for subsequent processing, the correctness of data reading is improved, and the reliability of data storage is increased.
The communication module comprises WIFI, UHF and S waveband modules and is used for ground test of the functions of the single-board satellite, receiving and sending of instructions and interaction of short-distance and main satellite data information, switching is controlled through a calculation processing unit in the digital data processing module, namely, an enabling switch of the connection module is connected, different enabling switches are enabled through different communication distances, namely, the communication is in WIFI communication, the calculation processing unit is informed through WIFI communication, when the communication is switched to an S waveband, the calculation processing unit enables the S waveband module to be opened, the connection between the S waveband module and the outside is reestablished, the WIFI communication is disconnected, and the working state of the single-board satellite is transmitted to a ground PC or a main satellite through the communication module by using three communication modules of WIFI, UHF and S;
the communication module is mainly used for single-board satellite ground function test, and interaction with the control and data of the main satellite. Three communication modes of WIFI, UHF and S bands are provided, as shown in FIG. 4. The three communication modes have different effective transmission distances, wherein USR-WIFI232-X series are used for WIFI, SM55D type wireless communication modules are used for UHF, and SO75CC2500PA wireless transmission modules are used for S bands. WIFI and UHF link to each other with the bus controller in the digital data processing module through serial bus interface, and the S wave band passes through 4 line SPI buses and links to each other with the bus controller. The single-board satellite has one and only one communication mode at any moment, and the selection of the communication mode is controlled by the digital data processing module.
The voltage generation module is used for providing voltage required by the integral power supply of the single-board satellite and independently supplying power for each module in the single-board pico-satellite system, and the digital circuit, the analog circuit and the high-frequency communication module are designed separately, wherein the analog voltage meeting the precision and noise requirements is obtained by boosting the analog power through the DC-DC converter and then reducing the voltage through the LDO for the system to use, the digital circuit is used for converting the DC-DC converter into the LDO for the system to use, and the high-frequency communication directly uses the voltage required by the high-frequency communication output by the DC-DC converter;
the voltage generation module is used for providing voltage required by all modules on the single-board satellite to work, external power supply is converted into stable voltage through the DC-DC chip and the LDO chip, digital and analog are separated, each module in the system supplies power independently, as shown in fig. 5, the voltage generation module is used for separating and controlling power supply of each module, and the computer processing unit can realize power-off processing on the modules which do not need to work at present through the power management controller, so that power consumption of the system is reduced.
The whole system is provided with power supply modules of digital, analog and high-frequency communication, the system design follows the design standard of a digital-analog mixed signal circuit, the system is divided into three types of ground, namely a digital ground, an analog ground and a high-frequency communication ground, and three ground signals are connected through a 0-ohm resistor or a magnetic bead to play an isolation role and reduce the influence of each part of circuit.
The invention uses ADC to collect solar energy patch voltage V1, the voltage precision of V1 is 0.5mv, the reference voltage of ADC is analog voltage V2 obtained by LDO, the noise of LDO is Root Mean Square (RMS), the conversion formula of ADC is
Figure BDA0001497393130000061
Where M is a digital code, K is a performance parameter of the ADC, and using an n-bit ADC, the value of K is 2nDividing (V2-RMS) into 2nAnd obtaining the digital code through a conversion formula. V1 corresponds to several shares therein, i.e., 1000_0000_ 0000; only such 0, 1 numbers can be recognized in the processor, when 1000_0000_0000 is recognized, the value of V1 is 1.
The ADC converts the analog signal to a digital signal, the conversion of the ADC being responsive to the voltage accuracy.
The GNC module acquires magnetic field information, rotation quantity and acceleration of a current single-plate satellite, namely acquires the motion state and position information of the current satellite;
the attitude and orbit control module of the GNC module comprises a gyroscope, a magnetometer and a magnetic rod and is used for acquiring the acceleration, magnetic field position information and the like of the current single-plate satellite, and the GNC module is connected with the processor module as shown in fig. 6. The magnetometer data acquisition chip uses a Feichal magnetometer chip MAG3110, the gyroscope uses an MPU6050 chip, and the magnetic rod is realized by a double-channel H-bridge motor driving chip DRV 8833. The magnetometer and the gyroscope are connected with a bus controller in the FPGA processing module through an I2C interface, and the magnetic bar drive is connected with the bus controller through a GPIO interface. And the calculation processing unit acquires and controls the GNC module information through the bus controller. Meanwhile, the operation of the GNC algorithm is executed in the computing processing unit, the acquired data are used as the parameter input of the GNC algorithm, the corresponding despinning capture algorithm is executed, and the algorithm execution result acts on the current single-board satellite in return. For example, the solar patch generates current after being irradiated, the current is influenced by the irradiation area, the current is collected by a computer processing unit after being amplified and used as the input of the GNC algorithm control part, and the light receiving surface condition is changed through the execution result of the algorithm.
The camera module is used for acquiring a single-board satellite image, completing image acquisition and image data compression, transmitting the photographed image data to a camera preprocessing unit of the digital data processing module after the camera photographs, preprocessing the data, namely extracting image gray data, so that the data format of the image data meets the JPEG2000 standard, and transmitting the preprocessed data to the camera module for compression coding;
the camera module realizes image acquisition and image compression and is used for system photographing of the single-board satellite, wherein the image acquisition sub-module adopts an OV7725 camera, and the image compression sub-module adopts ADV212 compression. The image acquisition sub-modules are arranged on the front side and the back side of the single-plate satellite and used for shooting image information at different angles. In order to meet the strict requirement of a single-board satellite on power consumption and ensure that a system runs under low power consumption, 2 cameras adopt a polling photographing mode, one camera is in a dormant state when the other camera works, after a picture is taken, the whole camera module enters the dormant state, and the camera module is started again when a photographing instruction is received next time.
And after receiving the photographing instruction information of the processor, the camera executes corresponding action, the picture acquired by the camera is transmitted to a camera preprocessing unit in the FPGA through a data bus, the image gray data is extracted, the data is transmitted to a compression chip, the input gray picture is compressed by adopting a JPEG2000 standard, a compressed code stream is transmitted to an internal cache of the FPGA in parallel through a 16-bit data bus, and if the data volume is large, the picture data is stored in a Flash chip for transmitting the inter-satellite or inter-satellite data. In the whole process, the camera preprocessing module in the FPGA completes control over the camera and the compression chip, and comprises camera selection, initialization of all devices, configuration, reading and writing, working mode selection and the like.
After the system is powered on, the voltage generation module generates voltages required by the operation of each module, all the systems are powered on to operate, when a measurement and control system on the ground or a main satellite sends an instruction, the instruction is received by the communication module and transmitted to the digital data processing module, the instruction is analyzed and recognized by the calculation processing unit in the digital data processing module, if the instruction is a camera instruction, the camera module is controlled to take a picture to obtain picture data, if the instruction is a GNC instruction, data reading and data storage are carried out through the GNC module, data needing to be accessed are stored in the data storage module through the calculation processing unit, and the read data and the picture data are both sent through the communication module.
The software design of the invention adopts a radiation-resistant triple-modular redundancy design method, carries out two-out-of-three voting on important parameters, and simultaneously uses a watchdog timer control technology to prevent a program from running away. When the running program needs to respond and wait, if the running program does not respond for a preset time, the frame information is discarded and is sent and received again, and the dead cycle is prevented. Further, when the calculation processing unit reads the same value through the bus controller for multiple times, the communication between the calculation processing unit and the bus controller is considered to be in fault, and at the moment, the module is powered off and restarted through control.
The single board satellite data link is as follows: after the instruction for acquiring the state information of the whole satellite is sent to the single-board satellite through different communication modules, the instruction information is transmitted to the calculation processing unit through the bus controller, the calculation processing unit analyzes the instruction to finish photographing, acquiring the attitude information of the satellite and the like, and the data is transmitted out from the communication modules through the bus controller.
In order to improve the reliability of the pico-satellite system, when selecting the chip of the satellite-borne computer system, whether the operating temperature, the performance and the power consumption of the chip meet the requirements of the pico-satellite working environment is considered firstly. When selecting the capacitor, the resistor and other devices, derating factors such as voltage and power consumption derating of the capacitor, power derating and voltage derating of the resistor are considered.
In order to further improve the reliability of the single-board satellite system, a shielding case is additionally arranged on the processor module after the system is manufactured. In addition, the outer skin of the single-plate satellite can also play a certain shielding role on space radiation.
The veneer skin satellite system fully considers the reliability of the system in the stages of device model selection, system design and manufacture, has the characteristics of simple structure, high integration level, small volume and low power consumption, and has higher reliability by carrying out redundancy and check processing on data through software and hardware layers.

Claims (2)

1. A reconfigurable veneer pico satellite system comprises a digital data processing module, a data storage module, a communication module, a voltage generation module, a GNC module and a camera module, and is characterized in that:
the digital data processing module comprises a power management controller, a calculation processing unit, a camera preprocessing unit and a bus controller, wherein the calculation processing unit monitors the current satellite electric quantity state information, when the current electric quantity is detected to be lower than a set low threshold value, the current satellite electric quantity is insufficient, and the power management controller controls a voltage generation module to perform power-off processing on a current non-working module to wait for charging of a solar battery; when the current electric quantity is detected to be higher than a set high threshold value, the current solar battery is full of the satellite, and the system power supply is controlled according to the current satellite electric quantity; the computing processing unit adopting the IP core is the core of the digital data processing module and is a task management and algorithm execution unit; the camera preprocessing unit is used for processing data from original photo data in the camera module to the decoding chip so that the data format of the photo meets the JPEG2000 standard, and the bus controller is used for providing interfaces between the digital data processing module and other modules;
all logics and controls in the digital data processing module are realized by using FPGA, the FPGA is used for dynamic management of a power supply, so that the power supply management controller is realized, a processor IP core is used as a CPU (Central processing Unit), namely a calculation processing unit, data is preprocessed, namely a camera preprocessing unit, and a bus controller is realized according to I2C, UART (Universal asynchronous receiver/transmitter) and SPI (Serial peripheral interface) bus time sequences, wherein when the processor IP core is used, in order to increase the fault-tolerant capability of the calculation processing unit, full redundancy processing is carried out on the IP core, namely, the processor core is copied into three parts, the three processor cores respectively execute the same program, share data and program storage, and triple modular redundancy is realized;
the data storage module comprises a FLASH chip and a peripheral circuit and is used for storing parameters during initialization of the single slab skin satellite, data after picture compression coding and geomagnetic field data required by attitude orbit control;
the communication module comprises WIFI, UHF and S waveband modules and is used for testing the functions of the veneer dermatosatellite on the ground, receiving and sending instructions and interacting data information of a main satellite in a short distance, switching is controlled by a calculation processing unit in the digital data processing module, namely, an enabling switch of the connection module is connected, different enabling switches are enabled in different communication distances, namely, the communication is in WIFI communication, the calculation processing unit is informed of the WIFI communication, when the communication is switched to an S waveband, the calculation processing unit enables the S waveband module to be opened, the connection between the S waveband module and the outside is reestablished, the WIFI communication is disconnected, and the working state of the veneer dermatosatellite is transmitted to a measurement and control system or the main satellite on the ground through the communication module by using the three communication modules of WIFI, UHF and S;
the voltage generation module is used for providing voltage required by the integral power supply of the veneer pico-satellite and independently supplying power for each module in the veneer pico-satellite system, and the digital circuit, the analog circuit and the high-frequency communication module are designed separately, wherein the analog voltage meeting the precision and noise requirements is obtained by the step-up of the analog power through the DC-DC converter and the step-down of the analog power through the LDO for the system to use, the digital circuit is used for converting the DC-DC converter into the LDO for the system to use, and the high-frequency communication directly uses the voltage required by the high-frequency communication output by the DC-DC converter;
the GNC module acquires the magnetic field information, the rotation quantity and the acceleration of the current veneer skin satellite, namely the motion state and the position information of the current satellite;
the camera module is used for acquiring a single slab satellite image to complete image acquisition and image data compression, after the camera takes a picture, the taken image data is transmitted to a camera preprocessing unit of the digital data processing module to preprocess the data, namely, image gray data is extracted, so that the data format of the image data meets the JPEG2000 standard, and the preprocessed data is transmitted to the camera module to be compressed and encoded;
after the system is powered on, the voltage generation module generates voltages required by the work of each module, all the systems are powered on to work, when a measurement and control system on the ground or a main satellite sends an instruction, the instruction is received by the communication module and transmitted to the digital data processing module, after the instruction is analyzed and recognized by the calculation processing unit in the digital data processing module, if the instruction is a camera instruction, the camera module is controlled to take a picture to obtain picture data, if the instruction is a GNC instruction, data reading and data storage are carried out through the GNC module, data needing to be accessed are stored in the data storage module through the calculation processing unit, and the read data and the picture data are both sent through the communication module.
2. The reconfigurable veneer skin satellite system according to claim 1, wherein:
the voltage of the solar patch collected by the ADC is V1, the reference voltage of the ADC is an analog voltage V2 obtained by the LDO, the noise of the LDO is root-mean-square, and the conversion formula of the ADC is
Figure FDA0002691061680000021
Where M is a digital code, K is a performance parameter of the ADC, and using an n-bit ADC, the value of K is 2nDividing (V2-RMS) into 2nAnd obtaining the digital code through a conversion formula.
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