CN102156626A - Sine-cosine function IP core capable of reconfiguring spaceborne computer and control method thereof - Google Patents
Sine-cosine function IP core capable of reconfiguring spaceborne computer and control method thereof Download PDFInfo
- Publication number
- CN102156626A CN102156626A CN 201110107337 CN201110107337A CN102156626A CN 102156626 A CN102156626 A CN 102156626A CN 201110107337 CN201110107337 CN 201110107337 CN 201110107337 A CN201110107337 A CN 201110107337A CN 102156626 A CN102156626 A CN 102156626A
- Authority
- CN
- China
- Prior art keywords
- cosine
- value
- sine
- module
- multiplier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Control Of Position, Course, Altitude, Or Attitude Of Moving Bodies (AREA)
- Position Fixing By Use Of Radio Waves (AREA)
Abstract
The invention relates to a sine-cosine function IP core capable of reconfiguring a spaceborne computer and a control method thereof, relating to the technical field of aerospace electronics, and solving the problems that the result of initial value assignment is largely influenced due to rounding errors, and the larger the angle is, the more the iteration times is needed. An initializing module is connected with a right-shift N-bit module and a module 1, the module 1 is connected with a cosine value storing device, the right-shift N-bit module is connected with a sine value storing device, the cosine value storing device and the sine value storing device are connected with a subtracter-adder and a first multiplier, the subtracter-adder is connected with a second multiplier and then is connected with the cosine value storing device, the first multiplier is connected with a left-shift 1-bit module and then is connected with the sine value storing device, and the a controller is connected with the sine value storing device and the cosine value storing device. The control method comprises the following steps of: mapping eta into [0, pi/2] to generate theta; judging whether theta is less than and equal to beta; if theta is less than and equal to beta, directly assigning the value and carrying out the last step; otherwise, carrying out the iteration operation, and obtaining an assigned initial value according to an approximate rule; calculating by utilizing a double-angle formula, judging whether n is less than N; if n is less than N, calculating again; otherwise, finishing the operation; finally assigning a sine/cosine function value according to the positive/negative result obtained by the sign bit judgment. The invention is applied to attitude control.
Description
Technical field
The present invention relates to the electronic technology field of space flight and aviation.
Background technology
Along with the restructural technology is constantly opened up in the application of space industry, become satellite electron systematic research focus based on the spaceborne computer of FPGA (Field Programmable GateArray, field programmable gate array).Use with FPGA and can reduce volume, weight, power consumption and the cost of microsatellite, improve the functional density of system as the satellite electron system of core.
Attitude is determined and the attitude control and treatment is one of critical function of spaceborne computer, in traditional spaceborne computer, the standard sincos functions that call in the C language mathematical function library that rely on carry out the calculating of attitude control algolithm more, its time of calculating sin cos functions, as seen the computed in software sin cos functions was consuming time very long up to 2.5 μ s/ time (be accurate to radix point after 7).The general algorithm that adopts IP kernel to calculate sin cos functions has look-up table, polynomial expansion method, cordic algorithm and process of iteration.Though wherein look-up table also can be realized fast, be subject to the size and the speed of memory device; The polynomial expansion method is not subjected to the restriction of storage space, but needs could guarantee convergence after the normalization, and precision is not high; Cordic algorithm can reach precision arbitrarily, but its computing velocity is relevant with computational accuracy, and computational accuracy requires high more, and convergent speed is just slow more as a result; Process of iteration is the fastest, but iterations is relevant with the calculating angle, and it is big more to calculate angle, and required iterations is just many more.The principle of iterative algorithm is: for arbitrary input angle θ, with it divided by 2
N, when N is enough big, all can obtain very little angle [alpha] ≈ θ/2
NAccording to approximate criterion, can be similar to and obtain sin α ≈ α, cos α ≈ 1.Utilize double angle formula
sin2α＝2×sinα×cosα
cos2α＝(cosα+sinα)×(cosα-sinα)
Iteration can obtain importing the sine and cosine value of angle for N time.
From principle as can be known: when angle was little, less N just can satisfy the approximate valuation requirement, and number of iterations is less, and the speed of calculating is very fast.In the process of iteration, can use two register-stored result of calculations, as the input of next iteration, and do not need extra storage space, and can calculate the sin cos functions value simultaneously.But there is round-off error in the initial assignment of iterative algorithm, and it is very big to result's influence; Keep limited bits in the iterative process, have truncation error, along with increasing of iterations, the error of accumulation increases; For different angles, the iterations difference that needs, angle is big more, and the iterations that needs is many more, therefore needs to be optimized.
Summary of the invention
There is round-off error in the initial assignment that the present invention solves for existing iterative algorithm, and it is to the far-reaching problem of result; And for different angles, the iterations difference that needs, angle is big more, the many more defectives of iterations that need, and a kind of sin cos functions IP kernel and control method thereof of reconfigurable satellite-borne computer are proposed.
The sin cos functions IP kernel of reconfigurable satellite-borne computer comprises initialization module 1, the N position module that moves to right 2,1 module 3, subtracter 4, totalizer 5, first multiplier 6, second multiplier 7,1 module 8, sine value storer 9, cosine value storer 10 and controller 11 move to left; The input end of initialization module 1 is the angle η input end of the sin cos functions IP kernel of reconfigurable satellite-borne computer, two output terminals of initialization module 1 connect the move to right input end of N position module 2 and the input end of 1 module 3 respectively, the output terminal of 1 module 3 connects the first input end of cosine value storer 10, the output terminal of the N position module 2 that moves to right connects the first input end of sine value storer 9, the output terminal of cosine value storer 10 connects the first input end of subtracter 4 respectively, the first input end of the first input end of totalizer 5 and first multiplier 6, the output terminal of sine value storer 9 connects second input end of subtracter 4 respectively, second input end of second input end of totalizer 5 and first multiplier 6, the output terminal of subtracter 4 connects the first input end of second multiplier 7, the output terminal of totalizer 5 connects second input end of second multiplier 7, the output terminal of second multiplier 7 connects second input end of cosine value storer 10, the output terminal of first multiplier 6 connects the input end of 1 module 8 that moves to left, the output terminal of 1 module 8 that moves to left connects second input end of sine value storer 9, the 4th output terminal of sine value storer 9 is the sinusoidal output terminal of the sin cos functions IP kernel of reconfigurable satellite-borne computer, the four-input terminal of cosine value storer 10 is the cosine output terminal of the sin cos functions IP kernel of reconfigurable satellite-borne computer, and two signal controlling ends of controller 11 connect the control signal receiving end of sine value storer 9 and the control signal receiving end of cosine value storer 10 respectively.
The step of the control method of the sin cos functions IP kernel of reconfigurable satellite-borne computer is as follows:
Step 1: according to the periodicity of trigonometric function angle η being mapped to becomes input angle θ in [0, pi/2], and sign bit is set;
Step 2: judge that in advance whether the input angle θ that judges input is smaller or equal to given critical angle β, promptly when β 〉=θ, then directly utilize sin θ=θ, cos θ=1 to carry out assignment and enter step 4, not, promptly when β＜θ≤pi/2, then enter step 3;
Step 3: interative computation:
Step 1: the input angle θ to input carries out interative computation, will import angle θ divided by 2
N, obtain initial assignment according to approximate criterion:
sinα＝θ/2
N
cosα＝1
n＝0
Wherein, N represents total iterations, and n represents iteration the n time;
Step 2: utilize double angle formula to calculate:
cos2
n+1α＝(cos2
nα+sin2
nα)×(cos2
nα-sin2
nα)
sin2
n+1α＝2×sin2
nα×cos2
nα
n＝n+1
Step 3: judge n＜N, be, then return step 2 and calculate once more, not, then enter step 4;
Step 4: finish sine and cosine value sin θ=sin2 that interative computation obtains importing angle θ
Nα, cos θ=cos2
Nα;
Step 4: judge the positive and negative of resulting result according to sign bit, give the sin cos functions value, obtain final sine and cosine value.
The objective of the invention is to design the IP kernel that a kind of FPGA of utilization hardware calculates the sincos function,, carry out attitude control, improve the performance of reconfigurable satellite-borne computer as the coprocessor of reconfigurable satellite-borne computer.Require very high to the real-time of calculating in the attitude of satellite control, the computing velocity of process of iteration is the fastest and to take resource also less, so the present invention is optimized process of iteration according to actual needs, round-off error in the iterative algorithm and truncation error are inevitably, but can error be reduced by the method that increases the register figure place.For being accurate to behind the radix point 7, will keep 15 position effective digitals among the present invention and carry out interative computation, and computing machine is preserved the error of double-precision floating points 10
-15～10
-16Between, carry out interative computation so keep 15 position effective digitals among the present invention.When the calculating angle was big, iterations is very big could to satisfy accuracy requirement, suitably dwindled the scope of calculating angle and can improve the efficient of calculating.In addition, just can satisfy accuracy requirement for the low-angle indirect assignment, carry out interative computation and can increase unnecessary calculated amount on the contrary, and precision is reduced, iterative algorithm is optimized in design according to analyzing: the field of definition of calculating angle η sin cos functions is (∞, + ∞), according to the periodicity of trigonometric function, will import angle θ and be mapped in [0, pi/2], and sign bit is set, import the calculating of angle θ sin cos functions again.Calculate the scope of angle and dwindle, make iterations reduce, accumulated error is little, has improved speed and the precision calculated.As input angle θ during smaller or equal to given critical angle β, indirect assignment does not need to carry out the requirement that iteration also can reach precision, improves the speed of calculating.
Description of drawings
Fig. 1 is the process flow diagram of control method of the sin cos functions IP kernel of reconfigurable satellite-borne computer; Fig. 2 is the structural representation of the sin cos functions IP kernel of reconfigurable satellite-borne computer.
Embodiment
Embodiment one: in conjunction with Fig. 1 present embodiment is described, the present embodiment step is as follows:
Step 1: according to the periodicity of trigonometric function angle η being mapped to becomes input angle θ in [0, pi/2], and sign bit is set;
Step 2: judge that in advance whether the input angle θ that judges input is smaller or equal to given critical angle β, promptly when θ≤β, then directly utilize sin θ=θ, cos θ=1 to carry out assignment and enter step 4, not, promptly when β＜θ≤pi/2, then enter step 3;
Step 3: interative computation:
Step 1: the input angle θ to input carries out interative computation, will import angle θ divided by 2
N, obtain initial assignment according to approximate criterion:
sinα＝θ/2
N
cosα＝1
n＝0
Wherein, N represents total iterations, and n represents iteration the n time;
Step 2: utilize double angle formula to calculate:
cos2
n+1α＝(cos2
nα+sin2
nα)×(cos2
nα-sin2
nα)
sin2
n+1α＝2×sin2
nα×cos2
nα
n＝n+1
Step 3: judge n＜N, be, then return step 2 and calculate once more, not, then enter step 4;
Step 4: finish sine and cosine value sin θ=sin2 that interative computation obtains importing angle θ
Nα, cos θ=cos2
Nα;
Step 4: judge the positive and negative of resulting result according to sign bit, give the sin cos functions value, obtain final sine and cosine value.
Embodiment two: present embodiment and embodiment one difference are the asking for of critical angle β in the step 2:
The design accuracy that expection reaches is 10
-m, according to the principle of initial assignment, critical angle β should satisfy:
For example, expect that the design accuracy that reaches is 10
-7, critical angle β should satisfy:
The β that asks=0.0014.Other composition is identical with embodiment one with connected mode.
Embodiment three: present embodiment and embodiment one or 2 are that the total iterations N in the step 3 is 21 times; Adopt iterative algorithm to realize that the main error of sin cos functions has: round-off error and truncation error.When iterative process keeps significant figure more for a long time, truncation error is very little to the result of calculation influence, can ignore, so only consider the round-off error that produces in initial assignment.
Sinx, cosx are carried out Taylor launch, have:
sinx＝x-x
3/3！+x
5/5！-…
cosx＝1-x
2/2！+x
4/4！-…
When the value of x much smaller than 1 the time, only need to keep first requirement that can satisfy computational accuracy of expansion.
Make α ≈ θ/2
N, the error of establishing n step iterative computation sine, cosine is respectively ε
n, Δ
n, the error expression of employing recurrence method derivation sin cos functions.At first carry out initial assignment, sin α ≈ α, cos α ≈ 1 ignore high order power error, then have
ε
0＝|-α
3/3！+α
5/5！-…|≈α
3/3！
Δ
0＝|-α
2/2！+α
4/4！-…|≈α
2/2！
By that analogy, the size of finding iteration error and α, number of iterations are relevant, and the derivation iteration error is as shown in table 1:
Table 1 iteration error
| Iterations | The sinusoidal calculations error | The cosine error of calculation |
| 0 | α 3/3 | α 2/2 |
| 1 | 4α 3/3 | α 2 |
| 2 | 20α 3/3 | 2α 2 |
| 3 | 88α 3/3 | 4α 2 |
| n | 2 n-1(2 n-2/3)α 3 | 2 n-1α 2 |
When θ＞1, can get
2
n-1(2
n-2/3)α
3≈2
2n-1α
3
＝(2
n-1α
2)·(2
nα)
＝2
n-1α
2·θ＞2
n-1α
2
Derive as can be known according to following formula: when angle is big, the error that the error of sinusoidal calculations is calculated greater than cosine, the precision that only needs to consider sinusoidal calculations gets final product.Angle is big more in iterative algorithm, and iterations is many more.When θ=pi/2, according to the sinusoidal calculations error formula as can be known, reach 10
-7Precision need iteration 21 times, so can reach the requirement of design accuracy for 21 times for [0, pi/2] interior unspecified angle iteration.Other composition is identical with embodiment one or two with connected mode.
Embodiment four: in conjunction with the bright present embodiment of Fig. 2, present embodiment comprises initialization module 1, the N position module that moves to right 2,1 module 3, subtracter 4, totalizer 5, first multiplier 6, second multiplier 7,1 module 8, sine value storer 9, cosine value storer 10 and controller 11 move to left; The input end of initialization module 1 is the angle η input end of the sin cos functions IP kernel of reconfigurable satellite-borne computer, two output terminals of initialization module 1 connect the move to right input end of N position module 2 and the input end of 1 module 3 respectively, the output terminal of 1 module 3 connects the first input end of cosine value storer 10, the output terminal of the N position module 2 that moves to right connects the first input end of sine value storer 9, the output terminal of cosine value storer 10 connects the first input end of subtracter 4 respectively, the first input end of the first input end of totalizer 5 and first multiplier 6, the output terminal of sine value storer 9 connects second input end of subtracter 4 respectively, second input end of second input end of totalizer 5 and first multiplier 6, the output terminal of subtracter 4 connects the first input end of second multiplier 7, the output terminal of totalizer 5 connects second input end of second multiplier 7, the output terminal of second multiplier 7 connects second input end of cosine value storer 10, the output terminal of first multiplier 6 connects the input end of 1 module 8 that moves to left, the output terminal of 1 module 8 that moves to left connects second input end of sine value storer 9, the 4th output terminal of sine value storer 9 is the sinusoidal output terminal of the sin cos functions IP kernel of reconfigurable satellite-borne computer, the four-input terminal of cosine value storer 10 is the cosine output terminal of the sin cos functions IP kernel of reconfigurable satellite-borne computer, and two signal controlling ends of controller 11 connect the control signal receiving end of sine value storer 9 and the control signal receiving end of cosine value storer 10 respectively.
Initialization module 1, be used for the angle η of input is mapped to [0, pi/2] in become input angle θ, also be used to judge in advance, judge that input angle θ whether smaller or equal to given critical angle β, is, then indirect assignment, not, then will import angle θ is converted to equivalent integer and sends to move to right N position module 2 and 1 module 3 simultaneously; Described input angle θ is standardizing number or the arithmetic number zero in the double-precision floating points, numerical range is [0,2), because the multiplier that FPGA provides only supports multiplication to calculate, in order to guarantee to call first multiplier 6 and second multiplier 7, therefore just double-precision floating points is converted to equivalent integer, thereby accelerates arithmetic speed.
Its transfer process: at first, read symbol, exponent and tail sign indicating number and the preservation of double-precision floating points, next, each the respective weights addition of tail sign indicating number is obtained weight and P, afterwards, calculate carry digit N and direction of displacement according to exponent, final, the integer of equivalence is P/2
NKeep behind the radix point 15, be about to floating number and take advantage of 1e+15, the every weight table of binary load is as shown in table 2:
Table 2 binary load tail sign indicating number weight table
| The tail sign indicating number | 52 | 51 | 50 | 49 | 0 | |
| Weight | 1e+15 | 5e+14 | 2.5e+14 | 1.25e+14 | 0 |
Wherein, IEEE 754 standard codes the coding of binary storage of double-precision floating points, sign bit is that 1, exponent are that 11, tail sign indicating number are 52 in the double-precision floating points, totally 64, accounts for 2 continuous 32 words;
The N position module that moves to right 2,1 module 3, subtracter 4, totalizer 5, first multiplier 6, second multiplier 7 and 1 module 8 that moves to left are used for equivalent integer is carried out interative computation N time;
The N position module 2 that moves to right is used for initial value sin=θ/2 of exporting the sine function iteration according to the equivalent integer that receives
N, and the initial value of sine function iteration sent to sine value storer 9;
1 module 3 is used for exporting according to the equivalent integer that receives the initial value cos=1 of cosine function iteration, and the initial value of cosine function iteration is sent to cosine value storer 10;
Sine value storer 9, be used to store the sine value that receives, and with this sine value as the sinusoidal input value of next iteration or final sinusoidal output valve, when receiving the control input signals of controller 11, then the sine value that will store sends subtracter 4, totalizer 5 and first multiplier 6 respectively as the sinusoidal input value of next iteration, when receiving the control output signal of controller 11, then the sine value that will store is converted to double-precision floating points as final sinusoidal output valve and outwards exports;
Cosine value storer 10, be used to store the cosine value that receives, and with this cosine value as the cosine input value of next iteration or final cosine output valve, when receiving the control input signals of controller 11, then the cosine value that will store sends subtracter 4, totalizer 5 and first multiplier 6 respectively as the cosine input value of next iteration, when receiving the control output signal of controller 11, then the cosine value that will store is converted to double-precision floating points as final cosine output valve and outwards exports;
The whole-number result of sine value storer 9 and 10 pairs of outputs of cosine value storer is carried out following operation and is converted into double-precision floating points output: at first, output result one is decided to be positive integer, sign bit S=0; Secondly, the N bit manipulation that moves to right (is for decimal number and takes advantage of 2 to the output result
NOperation), the result is satisfied between 1e+15 to 2e+15, and storage move to right figure place N and R as a result; Finally, can get the exponent value according to the figure place N that moves to right; Can corresponding everybody value of tail sign indicating number of judged result R according to tail sign indicating number weight table 2.Calculate sin cos functions, its result keeps behind the radix point 15 between 0-1, utilize the multiplier IP kernel to realize that the output result (decimal representation) of iterative algorithm is between 0-1e+15 as can be known.
Subtracter 4 be used for the sine function and the cosine function value of input are poor cos-sin, and the difference that will obtain sends to second multiplier 7,
Totalizer 5 is used for sine function and the cosine function value of input are done and cos+sin, and will obtain with send to second multiplier 7,
First multiplier 6, sine function that is used to import and the cosine function value cos * sin that multiplies each other, and the product that obtains sent to 1 module 8 that moves to left,
Second multiplier 7 is used for the output valve of totalizer and the output valve of subtracter are multiplied each other (cos+sin) * (cos-sin), and the product that obtains sent to is cosine value storer 10;
1 module 8 that moves to left moves to left 1 with the output valve of first multiplier 6, finishes and takes advantage of operation 2 * cos * sin of 2, and its output valve sent to be sine value storer 9;
Table 3 is the corresponding relation of double-precision floating points, equivalent integer and corresponding binary format product thereof.Therefrom as can be seen, when calling multiplier and carrying out multiplying, the output figure place can double.During binary representation, the input of multiplier IP kernel mostly is 128 most, is output as 256.When binary representation, n figure place and n figure place multiply each other, and will import the 2n figure place.Iteration can be found several times: the scope that the output number of bits will can calculate above multiplier, iteration can not continue.Need after each multiplying, block the operation of figure place, just can guarantee the continuation of iteration.As can be seen from Table 3, for keep N position behind the radix point carry out iteration the time, block the figure place operation and be equivalent to the result of multiplier is removed 10
NOperation, and round.Describe to keep 2 significant digits below, maximum available 7 bits of integer double figures are represented, so select multiplier to be input as 27 bits, are output as 14 bits.Table 4 is depicted as everybody weight of output binary number, decimal number 4300 (binary form is shown 01000011001100), every weight addition of binary representation is got 43, and block coming to the same thing of figure place in the table 3, so solved the problem that the multiplying figure place doubles.
The corresponding relation of table 3 different data format product
| Product | The result | Block figure place | |
| Floating number | 0.50×0.86 | 0.4300 | 0.43 |
| The equivalence integer | 50×86 | 4300 | 43 |
| Scale-of-two | 0110010×1010110 | 01000011001100 | 0101011 |
The every weight table of table 4 output binary number
| The output scale-of-two is every | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5…0 |
| Weight | 82 | 41 | 20 | 10 | 5 | 3 | 1 | 1 | 0 |
Controller 11, be used for transmitting control signal to sine value storer 9 and cosine value storer 10, when control module 4 count down to N, then stop interative computation and send the control output signal to sine value storer 9 and cosine value storer 10 respectively, when control module 4 countings do not arrive N, then continue interative computation and send control input signals to sine value storer 9 and cosine value storer 10 respectively.
Content of the present invention is not limited only to the content of the respective embodiments described above, and the combination of one of them or several embodiments equally also can realize the purpose of inventing.
Claims (5)
1. the sin cos functions IP kernel of reconfigurable satellite-borne computer is characterized in that it comprises initialization module (1), the N position module (2) that moves to right, 1 module (3), subtracter (4), totalizer (5), first multiplier (6), second multiplier (7), 1 module (8) that moves to left, sine value storer (9), cosine value storer (10) and controller (11); The input end of initialization module (1) is the angle η input end of the sin cos functions IP kernel of reconfigurable satellite-borne computer, two output terminals of initialization module (1) connect the input end of the N position module (2) that moves to right and the input end of 1 module (3) respectively, the output terminal of 1 module (3) connects the first input end of cosine value storer (10), the output terminal of the N position module (2) that moves to right connects the first input end of sine value storer (9), the output terminal of cosine value storer (10) connects the first input end of subtracter (4) respectively, the first input end of the first input end of totalizer (5) and first multiplier (6), the output terminal of sine value storer (9) connects second input end of subtracter (4) respectively, second input end of second input end of totalizer (5) and first multiplier (6), the output terminal of subtracter (4) connects the first input end of second multiplier (7), the output terminal of totalizer (5) connects second input end of second multiplier (7), the output terminal of second multiplier (7) connects second input end of cosine value storer (10), the output terminal of first multiplier (6) connects the input end of 1 module (8) that moves to left, the output terminal of 1 module (8) that moves to left connects second input end of sine value storer (9), the 4th output terminal of sine value storer (9) is the sinusoidal output terminal of the sin cos functions IP kernel of reconfigurable satellite-borne computer, the four-input terminal of cosine value storer (10) is the cosine output terminal of the sin cos functions IP kernel of reconfigurable satellite-borne computer, and two signal controlling ends of controller (11) connect the control signal receiving end of sine value storer (9) and the control signal receiving end of cosine value storer (10) respectively.
2. the sin cos functions IP kernel of reconfigurable satellite-borne computer according to claim 1 is characterized in that it
Initialization module (1), be used for the angle η of input is mapped to [0, pi/2] in become input angle θ, also be used to judge in advance, judge that input angle θ whether smaller or equal to given critical angle β, is, then indirect assignment, not, then will import angle θ is converted to equivalent integer and sends to move to right N position module (2) and 1 module (3) simultaneously;
The N position module (2) that moves to right is used for initial value sin=θ/2 of exporting the sine function iteration according to the equivalent integer that receives
N, and the initial value of sine function iteration sent to sine value storer (9);
1 module (3) is used for exporting according to the equivalent integer that receives the initial value cos=1 of cosine function iteration, and the initial value of cosine function iteration is sent to cosine value storer (10);
Sine value storer (9), be used to store the sine value that receives, and with this sine value as the sinusoidal input value of next iteration or final sinusoidal output valve, when receiving the control input signals of controller (11), then the sine value that will store sends subtracter (4), totalizer (5) and first multiplier (6) respectively as the sinusoidal input value of next iteration, when receiving the control output signal of controller (11), then the sine value that will store is converted to double-precision floating points as final sinusoidal output valve and outwards exports;
Cosine value storer (10), be used to store the cosine value that receives, and with this cosine value as the cosine input value of next iteration or final cosine output valve, when receiving the control input signals of controller (11), then the cosine value that will store sends subtracter (4), totalizer (5) and first multiplier (6) respectively as the cosine input value of next iteration, when receiving the control output signal of controller (11), then the cosine value that will store is converted to double-precision floating points as final cosine output valve and outwards exports;
Subtracter (4) be used for the sine function and the cosine function value of input are poor cos-sin, and the difference that will obtain sends to second multiplier (7),
Totalizer (5) is used for sine function and the cosine function value of input are done and cos+sin, and will obtain with send to second multiplier (7),
First multiplier (6), sine function that is used to import and the cosine function value cos * sin that multiplies each other, and the product that obtains sent to 1 module (8) that moves to left,
Second multiplier (7) is used for the output valve of totalizer and the output valve of subtracter are multiplied each other (cos+sin) * (cos-sin), and the product that obtains sent to is cosine value storer (10);
1 module (8) that moves to left moves to left 1 with the output valve of first multiplier (6), finishes and takes advantage of operation 2 * cos * sin of 2, and its output valve sent to be sine value storer (9);
Controller (11), be used for transmitting control signal to sine value storer (9) and cosine value storer (10), when control module 4 count down to N, then stop interative computation and send the control output signal to sine value storer (9) and cosine value storer (10) respectively, when control module 4 countings do not arrive N, then continue interative computation and send control input signals to sine value storer (9) and cosine value storer (10) respectively.
3. the control method of the sin cos functions IP kernel of reconfigurable satellite-borne computer is characterized in that its step is as follows:
Step 1: according to the periodicity of trigonometric function angle η being mapped to becomes input angle θ in [0, pi/2], and sign bit is set;
Step 2: judge that in advance whether the input angle θ that judges input is smaller or equal to given critical angle β, promptly when β 〉=θ, then directly utilize sin θ=θ, cos θ=1 to carry out assignment and enter step 4, not, promptly when β＜θ≤pi/2, then enter step 3;
Step 3: interative computation:
Step 1: the input angle θ to input carries out interative computation, will import angle θ divided by 2
N, obtain initial assignment according to approximate criterion:
sinα＝θ/2
N
cosα＝1
n＝0
Wherein, N represents total iterations, and n represents iteration the n time;
Step 2: utilize double angle formula to calculate:
cos2
n+1α＝(cos2
nα+sin2
nα)×(cos2
nα-sin2
nα)
sin2
n+1α＝2×sin2
nα×cos2
nα
n＝n+1
Step 3: judge n＜N, be, then return step 2 and calculate once more, not, then enter step 4;
Step 4: finish sine and cosine value sin θ=sin2 that interative computation obtains importing angle θ
Nα, cos θ=cos2
Nα;
Step 4: judge the positive and negative of resulting result according to sign bit, give the sin cos functions value, obtain final sine and cosine value.
4. the sin cos functions IP kernel and the control method thereof of reconfigurable satellite-borne computer according to claim 3 is characterized in that asking for of critical angle β:
The design accuracy that expection reaches is 10
-m, according to the principle of initial assignment, critical angle β should satisfy:
5. according to the sin cos functions IP kernel and the control method thereof of claim 3 or 4 described reconfigurable satellite-borne computers, it is characterized in that the total iterations N in the step 3 is 21 times.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110107337A CN102156626B (en) | 2011-04-27 | 2011-04-27 | Sine-cosine function IP core capable of reconfiguring spaceborne computer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110107337A CN102156626B (en) | 2011-04-27 | 2011-04-27 | Sine-cosine function IP core capable of reconfiguring spaceborne computer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102156626A true CN102156626A (en) | 2011-08-17 |
| CN102156626B CN102156626B (en) | 2012-10-10 |
Family
ID=44438136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110107337A Expired - Fee Related CN102156626B (en) | 2011-04-27 | 2011-04-27 | Sine-cosine function IP core capable of reconfiguring spaceborne computer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102156626B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107402743A (en) * | 2017-07-24 | 2017-11-28 | 珠海泰芯半导体有限公司 | A kind of phase demodulation apparatus and method based on cordic algorithm |
| CN108100308A (en) * | 2017-12-07 | 2018-06-01 | 西北工业大学 | A kind of restructural veneer skin satellite system |
| CN109190084A (en) * | 2018-07-25 | 2019-01-11 | 中国航空工业集团公司西安飞行自动控制研究所 | A kind of hardware implementation method that sine and cosine calculates |
| CN112650973A (en) * | 2019-10-11 | 2021-04-13 | 珠海格力电器股份有限公司 | Trigonometric function calculation device and electronic equipment |
| CN117573069A (en) * | 2023-11-23 | 2024-02-20 | 北京国科天迅科技股份有限公司 | CORDIC algorithm chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1983103A (en) * | 2006-06-15 | 2007-06-20 | 华为技术有限公司 | Trigonometric value determiner, determining method and telecommunicating apparatus therewith |
| CN101493809A (en) * | 2009-03-03 | 2009-07-29 | 哈尔滨工业大学 | Multi-core onboard spacecraft computer based on FPGA |
| WO2009146284A1 (en) * | 2008-05-29 | 2009-12-03 | Harris Corporation | Sine/cosine generator |
-
2011
- 2011-04-27 CN CN201110107337A patent/CN102156626B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1983103A (en) * | 2006-06-15 | 2007-06-20 | 华为技术有限公司 | Trigonometric value determiner, determining method and telecommunicating apparatus therewith |
| WO2009146284A1 (en) * | 2008-05-29 | 2009-12-03 | Harris Corporation | Sine/cosine generator |
| CN101493809A (en) * | 2009-03-03 | 2009-07-29 | 哈尔滨工业大学 | Multi-core onboard spacecraft computer based on FPGA |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107402743A (en) * | 2017-07-24 | 2017-11-28 | 珠海泰芯半导体有限公司 | A kind of phase demodulation apparatus and method based on cordic algorithm |
| CN107402743B (en) * | 2017-07-24 | 2023-06-02 | 珠海泰为电子有限公司 | Phase demodulation device and method based on CORDIC algorithm |
| CN108100308A (en) * | 2017-12-07 | 2018-06-01 | 西北工业大学 | A kind of restructural veneer skin satellite system |
| CN108100308B (en) * | 2017-12-07 | 2021-01-05 | 西北工业大学 | Reconfigurable veneer skin satellite system |
| CN109190084A (en) * | 2018-07-25 | 2019-01-11 | 中国航空工业集团公司西安飞行自动控制研究所 | A kind of hardware implementation method that sine and cosine calculates |
| CN112650973A (en) * | 2019-10-11 | 2021-04-13 | 珠海格力电器股份有限公司 | Trigonometric function calculation device and electronic equipment |
| CN117573069A (en) * | 2023-11-23 | 2024-02-20 | 北京国科天迅科技股份有限公司 | CORDIC algorithm chip |
| CN117573069B (en) * | 2023-11-23 | 2024-04-19 | 北京国科天迅科技股份有限公司 | CORDIC algorithm chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102156626B (en) | 2012-10-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Park et al. | Weighted-entropy-based quantization for deep neural networks | |
| CN108780492B (en) | Analog coprocessor | |
| CN102156626B (en) | Sine-cosine function IP core capable of reconfiguring spaceborne computer | |
| CN109062540A (en) | A kind of restructural floating-point operation device based on cordic algorithm | |
| CN106155627B (en) | Low overhead iteration trigonometric device based on T_CORDIC algorithm | |
| Langroudi et al. | Positnn framework: Tapered precision deep learning inference for the edge | |
| CN101874237A (en) | Apparatus and method for performing magnitude detection for arithmetic operations | |
| Murillo et al. | Energy-efficient MAC units for fused posit arithmetic | |
| CN102073472A (en) | Trigonometric function CORDIC iteration operation coprocessor and operation processing method thereof | |
| CN103677737A (en) | Method and device for achieving low delay CORDIC trigonometric function based on carry-save summator | |
| CN102323878B (en) | Circuit device and method for norm correction of CORDIC (Coordinated Rotation Digital Computer) algorithm | |
| CN107423026B (en) | Method and device for realizing sine and cosine function calculation | |
| CN104536720A (en) | Method and system for measuring and calculating trigonometric function value of to-be-measured angle based on FPGA | |
| CN110222305A (en) | A kind of logarithmic function computing system and method based on hyperbolic CORDIC | |
| CN110187866A (en) | A kind of logarithmic multiplication computing system and method based on hyperbolic CORDIC | |
| CN103049716B (en) | First moment-based convolver | |
| Amaricai | Design trade-offs in configurable FPGA architectures for k-means clustering | |
| CN103809931A (en) | Design of dedicated high-speed floating point index arithmetic unit | |
| CN107657078B (en) | Ultrasonic phased array floating point focusing transmission implementation method based on FPGA | |
| CN116384455A (en) | Non-uniform piecewise linearization activation function hardware implementation method | |
| Zhang et al. | Efficient FPGA implementation of softmax layer in deep neural network | |
| CN113778379A (en) | CORDIC-based low-complexity hardware system and application method | |
| CN102073471B (en) | Method and circuit for Cordic (Coordinate Rotation Digital Computer) iterative operation of processor | |
| CN102253924B (en) | Method for realizing root extraction arithmetic on hardware and root extraction arithmetic device | |
| US8924447B2 (en) | Double precision approximation of a single precision operation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121010 Termination date: 20130427 |