CN107402743A - A kind of phase demodulation apparatus and method based on cordic algorithm - Google Patents
A kind of phase demodulation apparatus and method based on cordic algorithm Download PDFInfo
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Abstract
The invention discloses a kind of phase demodulation apparatus and method based on cordic algorithm, described device includes data preprocessing module, CORDIC interative computations module, the phase correction module being sequentially connected；The CORDIC interative computations module includes amplitude computing module, phase operation module, phase error computing module；Two output ports of the amplitude computing module are connected with phase operation module, phase error computing module respectively；The phase operation mould is connected with the output end of phase error computing module and the input of phase correction module soon；The phase interative computation result that phase operation module exports is added by the phase correction module with the accumulated phase cut-off error that phase error computing module exports, the phase after being corrected.The present invention calculates the Phase Truncation Error of accumulation using phase error computing module, the Phase Truncation Error of accumulation is added in the identified result of classical cordic algorithm with reference to phase correction module, effectively reduces influence of the accumulation to precision of phase discrimination of Phase Truncation Error.
Description
Technical field
The invention belongs to digital processing field, more particularly to a kind of digital phase detection device based on cordic algorithm and
Method.
Background technology
Phase demodulation refers to differentiate the phase difference of two-way circuit by circuit or algorithm.Phase detecting method includes analogue phase detection
Method and digital phase detecting method.With widely using for digital sampling techniques and Digital processing device, digital phase detecting method and
Digital phase detection circuit is widely applied, especially in digital received system and three-phase electrical power system.
Traditional digital phase detecting method is by carrying out quadrature demodulation to digital quadrature signal, obtaining the amplitude and phase of signal
Position.Principle is as follows：
If signal S (n)=A (n) × eT×φ(n), then S (n) can with two mutually orthogonal signal I (n), TQ (n) come
Represent, wherein I (n)=A (n) × cos φ (n), Q (n)=A (n) × sin φ (n).Now, signal S (n) amplitude A (n)=
(I(n)2+Q(n)2)1/2, phase (n)=arctan (I (n)/Q (n)) (I (n) >=0) or φ (n)=π+arctan (I (n)/Q
(n)) (I (n) ＜ 0).But traditional phase detecting method is employed square, evolution, arc tangent etc. are realized in digital circuit and compared
Troublesome computing.
Nineteen fifty-nine, t.D.Volder is proposed a kind of obtains vector phase by basic addition, subtraction and shift operation
Computational algorithm, this algorithm is exactly cordic algorithm.The algorithmic formula of cordic algorithm is： Ii+1=Ii-δi×round(Qi
×2-i), Qi+1=Qi+δi×round(Ii×2-i), θi+1=θi-δi×εi, δi=sgn (Qi), wherein I0=I (n), Q0=Q
(n), θ0=0, εi=arctan (2-i), i=0,1,2,3 ... N-1, N are accumulation iterationses.After n times iteration, QiConvergence
In 0, θNAs arctan (I (n)/Q (n)).
But in digital phase detection circuit, the digit that amplitude and phase represent is limited, therefore is calculated according to CORDIC
Phase Truncation Error be present in the phase obtained by method.The Phase Truncation Error can constantly accumulate during interative computation, drop
Low precision of phase discrimination.
The content of the invention
First purpose of the present invention aims to provide a kind of phase demodulation apparatus based on cordic algorithm, effectively reduces phase and cuts
Influence of the accumulation of disconnected error to precision of phase discrimination.
In order to realize first purpose of the present invention, this invention takes following technical scheme：
A kind of phase demodulation apparatus based on cordic algorithm, includes amplitude computing module and the CORDIC of phase operation module
Interative computation module；First output port of amplitude computing module is connected with phase operation module；It is characterized in that：It is described
CORDIC interative computations module also includes phase error computing module；The phase demodulation apparatus also includes phase correction module；It is described
Second output port of amplitude computing module is connected with phase error computing module；The phase operation module is transported with phase error
The output end for calculating module is connected as two output ports of CORDIC interative computations module with phase correction module, phase operation mould
The phase result of CORDIC interative computations is output to phase correction module by block.
Further, the phase error computing module accumulation N accumulates the Phase Truncation Error in iterative process and is output to
Phase correction module, N are the iterations of cordic algorithm；The phase correction module exports phase error computing module
Accumulated phase truncated error is added to the phase result of phase operation module output, and phase is corrected.
Further, the phase operation module includes phased memory, the first multiplier, the first subtracter and phase
Accumulator register；The phased memory, the first multiplier, the first subtracter and phase accumulator register are sequentially connected；Institute
Amplitude computing module is stated to the first multiplier output data.
Further, the phased memory is stored with to data arctan (2-t) divided by π and move to left L-1 positions amplification after four
The result that house five enters, i.e. phase(t)=round ((arctan (2-t)/π)×2L-1) (as follows), as phase interative computation
The anglec of rotation is output to the first multiplier, wherein t=0, and 1,2,3 ... T-1, T value are identical with accumulative iterations N, and L is phase
The bit wide of bit memory, round (x) are represented to x round numbers；The amplitude computing module exports to the first multiplier
δi, wherein δiIt is the direction of rotation of ith iteration, i=0,1,2,3 ... N-1；First multiplier stores phased memory
N number of data be multiplied by δiAfterwards the first subtracter is output to as subtrahend；First subtracter stores phase accumulator register
The data that are exported with the first multiplier of phase subtract each other, phase accumulator register, i.e. θ are arrived in as a result storagei+1=θi-δi×
phase(t), as a result it is stored in phase accumulator register, wherein θiIt is the phase of ith iteration, i and t value is identical；It is described
The initial value of phase accumulator register is 0, i.e. θ0=0；The phase accumulator register is by phase operation module n times interative computation
Phase result θNIt is output to phase correction module.
Further, the bit wide L values of the phased memory are identical with accumulative iterations N.
Further, the phase error computing module includes phase error memory, the second multiplier, the second subtracter
And phase error accumulative register；The phase error memory, the second multiplier, the second subtracter and phase error are tired out
Memory is added to be sequentially connected；The amplitude computing module is to the second multiplier output data.
Further, it is stored with and data phase in phased memory in the phase error memory(t)Corresponding number
According to phase error(t), phase error(t)=round (((arctan (2-t)/π)×2L-1-phase(t)) ×2K-1) (with
Similarly hereinafter), the anglec of rotation as Phase Truncation Error interative computation is output to the second multiplier, and wherein K stores for phase error
The bit wide of device；The data of phase error memory storage are multiplied by δ by second multiplieriAfterwards second is input to as minuend
Subtracter；The data phase that second subtracter exports the phase that phase error accumulator register stores with the second multiplier
Subtract, phase error accumulator register, i.e. E are arrived in as a result storagei+1=Ei-δi×phase error(t), as a result it is stored in phase error
Accumulator register, wherein EiIt is the accumulated phase truncated error of ith iteration, i is identical with t value；The phase error is tired out
The initial value for adding register is 0, i.e. E0=0；The phase error accumulator register accumulates Phase Truncation Error n times iteration
As a result ENIt is output to phase correction module.
Further, the bit wide K of the phase error memory is ceil (log2Q)+2, wherein q value changes with accumulative
Identical for times N, ceil (x) represents to round x to positive infinity.
Further, the phase correction module includes phase error computation module and first adder；The phase is missed
Poor computing module is connected with first adder；The Phase Truncation Error that the phase error accumulator register accumulates n times iteration
ENIt is output to phase error computation module；The phase error computation module is accumulated to phase error accumulator register n times iteration
Phase Truncation Error ENExecution moves to right K-1 positions and the operation to round up, is output to first adder as phase error, i.e.,
Phase error=round (EN/2K-1) (as follows), wherein phase error are phase errors；The first adder will
Phase error phase error and the n times phase interative computation of phase operation module output result θNIt is added, acquired results
Phase after as correcting.
Further, the phase demodulation apparatus also includes input data pretreatment module；The input data pretreatment module
It is connected with CORDIC interative computation modules, processing is amplified to pending arbitrary signal I and Q, and result is output to width
Spend computing module.
Further, the input data pretreatment module multiplies including multiplication factor computing module, the 5th multiplier, the 6th
Musical instruments used in a Buddhist or Taoist mass；Two output ports of the multiplication factor computing module are connected with the 5th multiplier, the 6th multiplier respectively；It is described to put
Big multiple computing module comparator input signal I and Q order of magnitude, and using larger absolute value M as divisor, with 2m+1Do
Division arithmetic, m value is identical with accumulation iterations N, and the result of gained is input to the 5th multiplier and the 6th after rounding and multiplied
Musical instruments used in a Buddhist or Taoist mass；5th multiplier and the 6th multiplier will input I and Q signal is multiplied by after multiplication factor as amplitude computing module
Primary data is output to amplitude computing module, i.e. I0=I × floor (2N+1/ M), Q0=Q × floor (2N+1/ M), wherein I0With
Q0It is the primary data (as follows) of amplitude interative computation, floor (x) represents to perform floor operation to x.
Further, the amplitude computing module includes circulating the first register of connection, the first shift unit, first successively
Round up circuit, the 3rd multiplier, second adder, the 3rd subtracter, the second register, the second shift unit, the two or four house
Five enter circuit, the 4th multiplier, symbol decision module；First output port of the input data pretreatment module is posted with first
Storage connects；Second output port of the input data pretreatment module is connected with the second register；First register
Circulate and connect with the 3rd subtracter；Second register connects with second adder circulation；The symbol decision module and the
Two registers connect, and judge the symbol of data storage in the second register, and to phase operation module and phase error computing mould
Block output symbol judged result.
Further, first shift unit and the second shift unit export to the first register and the second register respectively
Data perform and move to right i bit manipulations；Described first round up circuit and second round up circuit respectively to the first shift unit and
The data of second shift unit output perform the operation that rounds up；3rd multiplier and the 4th multiplier are given up to the one or four respectively
Five enter circuit and second round up circuit output data perform multiply δiOperation after be input to second adder and the 3rd and subtract
Musical instruments used in a Buddhist or Taoist mass；Storage is to the after the data that 3rd multiplier exports are added by the second adder with the data that the second register stores
Two registers；3rd subtracter enters the data that the 4th multiplier exports as the data that subtrahend stores with the first register
Stored after row subtraction to the first register；That is Ii+1=Ii-δi×round(Qi×2-i), the first register is as a result stored in,
Qi+1=Qi+ δi×round(Ii×2-i), as a result it is stored in the second register, wherein i=0,1,2,3 ... N-1, IiAnd QiRespectively
For the amplitude of ith iteration；The symbol decision module is by the symbol decision result sgn (Q of the second register data storagei),
That is δiIt is output to phase operation module and phase error computing module, wherein sgn (Qi) it is sign function, QiDuring ＜ 0, sgn
(Qi)=- 1；QiWhen=0, sgn (Qi)=0, QiDuring ＞ 0, sgn (Qi)=1.
Second object of the present invention aims to provide a kind of phase detecting method of the phase demodulation apparatus based on foregoing cordic algorithm,
Effectively reduce influence of the accumulation of Phase Truncation Error to precision of phase discrimination.
Second object of the present invention is realized by the following technical solutions.A kind of mirror based on above-mentioned phase demodulation apparatus
Phase method, comprise the steps of：
Amplitude interative computation：Amplitude computing module performs amplitude interative computation to pending two arbitrary signals I and Q,
The formula of amplitude interative computation is Ii+1=Ii-δi×round(Qi×2-i), Qi+1=Qi+δi× round(Ii×2-i), I0=I,
Q0=Q, symbol decision module is by the direction of rotation δ of n times interative computationiIt is output to phase operation module and phase error computing mould
Block, wherein δi=sgn (Qi), sgn (Qi) it is sign function, QiDuring ＜ 0, sgn (Qi)=- 1；QiWhen=0, sgn (Qi)=0, Qi
During ＞ 0, sgn (Qi)=1；
Phase interative computation：Phase operation module carries out phase interative computation, and the formula of phase interative computation is θi+1=
θi-δi×phase(t), θ0=0；The result θ of phase interative computationNIt is output to the first adder of phase correction module；
Phase Truncation Error iteration adds up：Phase error computing module carries out Phase Truncation Error accumulation, and phase truncation misses
Difference accumulation calculation formula be：Ei+1=Ei-δi×phase error(t), E0=0；The accumulation results EN of Phase Truncation Error is defeated
Go out the phase error computation module to phase correction module；
Phase error computation；Phase error computation module carries out phase error computation, and calculation formula is Phase error=
round(EN/2K-1)；
Phasing：First adder carries out phasing, and the calculation formula of phasing is Phase=θN+Phase
Error=θN+round(EN/2K-1)；
Further, the phase detecting method also includes the pre-treatment step of input data：Comparator input signal I's and Q is exhausted
To being worth size, take absolute value big numerical value, is set to M；With 2m+1Divided by M, to after result round numbers respectively with input signal I and Q phase
Multiply, and amplitude computing module is output to using result as primary data, m value is identical with accumulation iterations N, i.e. I0=I
×floor(2N+1/ M), Q0=Q × floor (2N+1/ M), wherein floor (x) represents to perform floor operation, I to x0And Q0It is width
Spend the primary data of interative computation.
Beneficial effect of the present invention：
From above technical scheme, the present invention calculates the Phase Truncation Error of accumulation by phase error computing module,
The Phase Truncation Error of accumulation is added in reference to phase correction module in the identified result of the cordic algorithm of classics, effectively reduced
Influence of the accumulation of Phase Truncation Error to precision of phase discrimination.At the same time, the present invention to input data by be multiplied by putting
Big multiple enhanced processing, reduces influence of the input data amplitude to phase.
Brief description of the drawings
In order to illustrate the embodiments of the present invention more clearly, simple Jie is done to the required accompanying drawing used in embodiment below
Continue.Drawings in the following description are only the embodiment in the present invention, for one of ordinary skill in the art, are not being paid
On the premise of going out creative work, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the device overall structure diagram of the present invention.
Fig. 2 is phase operation modular structure schematic diagram.
Fig. 3 is phase error computing module structural representation.
Fig. 4 is phase correction module structural representation.
Fig. 5 is amplitude computing module structural representation.
Fig. 6 is input data pretreatment module structural representation.
Fig. 7 is flow chart of the method for the present invention.
When Fig. 8 is no input data pretreatment module and Phase Truncation Error accumulation, output phase error simulation result
Figure.
Fig. 9 is output phase error emulation when having input data pretreatment module but being accumulated without Phase Truncation Error
Result figure.
When Figure 10 is while input data pretreatment module and Phase Truncation Error are accumulated, output phase error simulation result
Figure.
Embodiment
Below in conjunction with the accompanying drawings, the present invention will be described in detail.
In order that the purpose of the present invention, technical scheme, advantage are more clearly understood, below in conjunction with drawings and Examples to this
Invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, not
For limiting the present invention.
As shown in figure 1, a kind of phase demodulation apparatus based on cordic algorithm, including the input data pretreatment mould being sequentially connected
Block, CORDIC interative computations module and phase correction module.CORDIC interative computations module includes amplitude operation blocks, phase is transported
Calculate module and phase error computing module.Two output ports of amplitude computing module are connected with phase operation module respectively,
Phase error computing module connects.Phase operation module and the output end of phase error computing module are as CORDIC interative computations
Two output ports of module are connected with phase correction module.
The principle of the phase demodulation apparatus phase demodulation based on cordic algorithm is as follows：Two pending arbitrary signals are inputted
I and Q (as follows) are designated as to data prediction computing module, and by the two signals.Amplitude computing module is to pretreatment module
I, Q of output pre-process laggard line amplitude interative computation, and by N number of phase-rotation direction δ corresponding to n times interative computationiOutput
To phase operation module and phase error computing module, N is the accumulation iterations of cordic algorithm, i=0,1,2,3 ... N-
1, δi=sgn (Qi), sgn (Qi) it is sign function, QiDuring ＜ 0, sgn (Qi)=- 1；QiWhen=0, sgn (Qi)=0, QiDuring ＞ 0,
sgn(Qi)=1.Phase operation module carries out n times phase interative computation, the result θ of gainedNIt is output to phase correction module；Phase
Error op module carries out n times Phase Truncation Error iteration, and result (Phase Truncation Error accumulated) EN of gained is output to
Phase correction module.The accumulated phase truncated error that phase error computing module exports is added to phase by the phase correction module
The phase result of bit arithmetic module output, is corrected to phase.
As shown in fig. 6, input data pretreatment module includes multiplication factor computing module, the 5th multiplier, the 6th multiplication
Device.Two output ports of multiplication factor computing module are connected with the 5th multiplier, the 6th multiplier respectively.Multiplication factor calculates
Module compares two input signals I and Q order of magnitude, and using larger absolute value M as divisor, with 2m+1Do division fortune
Calculate, after the result of gained rounds, i.e. floor (2m+1/ M) the 5th multiplier and the 6th multiplier are input to, m values change with accumulation
It is identical for times N.5th multiplier and the 6th multiplier are multiplied by multiplication factor floor (2 to input signal I and QN+1/ M) make afterwards
Amplitude computing module is output to for the primary data of amplitude computing module.The primary data of amplitude computing module is designated as I0、Q0, then
I0=I × floor (2N+1/ M), Q0=I × floor (2N+1/ M), floor (x) represents to perform floor operation (as follows) to x.
As shown in figure 5, amplitude computing module includes circulating the first register of connection, the first shift unit, the one or four successively
House five enters circuit, the 3rd multiplier, second adder, the 3rd subtracter, the second register, the second shift unit, the two or four house five
Enter circuit, the 4th multiplier, symbol decision module.First register and the circulation of the 3rd subtracter connect.Second register and
The circulation connection of two adders.Symbol decision module is connected with the second register.First output end of input data pretreatment module
Mouth is connected with the first register.Second output port of input data pretreatment module is connected with the second register.
Amplitude computing module perform amplitude interative computation principle be：
Input signal I amplitude interative computation：The data that first shift unit exports to the first register, which perform, moves to right i positions behaviour
Make；First rounds up, and data that circuit exports to the first shift unit perform the operation that rounds up；3rd multiplier is to the one or four
The data execution that house five enters circuit output multiplies δiOperation after be input to second adder；Second adder is defeated by the 3rd multiplier
The data gone out are stored to the second register after being added with the data that the second register stores；That is Qi+1=Qi+δi×round(Ii×
2-i), as a result it is stored in the second register.Symbol decision module carries out symbol decision to the second register data storage, as a result sgn
(Qi), i.e. δiIt is output to phase operation module and phase error computing module；
Input signal Q amplitude interative computation：Second shift unit moves to right i to the data execution of the second register output respectively
Bit manipulation；Second rounds up, and data that circuit exports to the second shift unit perform the operation that rounds up；4th multiplier is to
Two data for rounding up circuit output, which perform, multiplies δiOperation after be input to the 3rd subtracter；3rd subtracter is by the 4th multiplication
The data of device output are stored to the first register after carrying out subtraction as the data that subtrahend and the first register store；I.e.
Ii+1=Ii-δi×round(Qi×2-i), as a result it is stored in the first register；
During the above is various, IiAnd QiIt is the amplitude of ith iteration；Round (x) is represented to x round numbers.
As shown in Fig. 2 phase operation module includes phased memory, the first multiplier, the first subtracter being sequentially connected
And phase accumulator register.Phased memory is stored with to data arctan (2-t) divided by π and move to left L-1 positions amplification after four house
The five result phase entered(t), i.e. phase(t)=round ((arctan (2-t)/π) ×2L-1), the anglec of rotation as phase iteration
Degree is output to the first multiplier, wherein t=0, and 1,2,3 ... T-1, T value are identical with accumulative iterations N, and L deposits for phase
The bit wide of reservoir, round (x) are represented to x round numbers.In the present embodiment, L is identical with accumulation iterations N.Width
Spend computing module and export δ to the first multiplieri.N number of data that first multiplier stores phased memory are multiplied by δiIt is used as and subtracts afterwards
Number is output to the first subtracter.The phase that first subtracter stores phase accumulator register and the data of the first multiplier output
Subtract each other, phase accumulator register, i.e. θ are arrived in as a result storagei+1=θi-δi×phase(t), phase accumulation register is as a result stored in,
Wherein i is identical with t value, and the initial value of phase accumulator register is 0, i.e. θ0=0.Phase accumulator register is by phase operation
The phase result θ of module n times interative computationNIt is output to phase correction module.
As shown in figure 3, phase error computing module include being sequentially connected phase error memory, the second multiplier, the
Two subtracters and phase error accumulative register.It is stored with phase error memory and data in phased memory
phase(t)Corresponding data phase error(t), phase error(t)=round (((arctan (2-t)/π)×2L-1-
phase(t))×2K-1)。phase error(t)The anglec of rotation as Phase Truncation Error interative computation is output to second and multiplied
Musical instruments used in a Buddhist or Taoist mass, wherein K are the bit wide of phase error memory, and K value is ceil (log2Q)+2, ceil (x) is represented to x to positive nothing
Round greatly thoroughly.In the present embodiment, q value is identical with accumulative iterations N.Second multiplier deposits phase error memory
The data of storage are multiplied by δiAfterwards the second subtracter is input to as minuend.Second subtracter stores phase error accumulator register
The data that are exported with the second multiplier of phase subtract each other, phase error accumulator register, i.e. E are arrived in as a result storagei+1=Ei-δi×
phase error(t), as a result it is stored in phase error accumulator register, wherein EiIt is the ith after moving to left the amplification of K-1 positions
The accumulated phase truncated error of iteration, i is identical with t value, and the initial value of phase error accumulator register is 0, i.e. E0=0.
The result E that the phase error accumulator register accumulates Phase Truncation Error n times iterationNIt is output to phase correction module.
As shown in figure 4, phase correction module includes phase error computation module and the first adder being sequentially connected.Phase
The phase truncation mistake after moving to left the amplification of K-1 positions for the n times iteration accumulation that error calculating module exports to phase error accumulator register
Poor ENExecution moves to right K-1 positions and the operation to round up, is as a result output to first adder, i.e. phase as phase error
Error=round (EN/2K-1), wherein phase error are phase error.First adder is by phase error phase
Error and the n times phase interative computation of phase operation module output result θNIt is added, acquired results are the phase after correcting
Position.
As shown in fig. 7, a kind of phase detecting method of the phase demodulation apparatus based on foregoing cordic algorithm, comprises the following steps：
The initialization step of phase accumulator register and phase error accumulator register：θ0=0, E0=0；
The pretreatment of input data：Comparator input signal I and Q order of magnitude, take absolute value big numerical value, is set to M；
With 2m+1Divided by M, to being multiplied respectively with input signal I and Q after result round numbers, the result of gained is output to as primary data
Amplitude computing module, m value is identical with accumulation iterations N, i.e. I0=I × floor (2N+1/ M), Q0=Q × floor (2N +1/ M), floor (x) represents to perform floor operation, I to x0And Q0It is the primary data of amplitude interative computation；
Amplitude interative computation：Amplitude computing module performs amplitude interative computation, amplitude iteration fortune to the signal I and Q of input
The formula of calculation is Ii+1=Ii-δi×round(Qi×2-i), Qi+1=Qi+δi×round(Ii×2-i)；Symbol decision module is by N
The direction of rotation δ of secondary interative computationiIt is output to phase operation module and phase error computing module, wherein δi=sgn (Qi), sgn
(Qi) it is sign function, QiDuring ＜ 0, sgn (Qi)=- 1；QiWhen=0, sgn (Qi)=0, QiDuring ＞ 0, sgn (Qi)=1；
Phase interative computation：Phase operation module carries out phase interative computation, and the formula of phase interative computation is θi+1=
θi-δi×phase(t), θ0=0；The result θ of phase interative computationNIt is output to phase correction module；
Phase Truncation Error iteration adds up：Phase error computing module carries out Phase Truncation Error accumulation, and phase truncation misses
Difference accumulation calculation formula be：Ei+1=Ei-δi×phase error(t), E0=0；The accumulation results EN of Phase Truncation Error is defeated
Go out the phase error computation module to phase correction module；
Calculate phase error：Phase error computation module carries out phase error computation, and calculation formula is Phase error=
round(EN/2K-1)；
Phasing：First adder carries out phasing, and the calculation formula of phasing is Phase=θN+Phase
Error=θN+round(EN/2K-1)。
When Fig. 8 is using traditional cordic algorithm (both pre-processed without input data or accumulated without Phase Truncation Error)
Phase error simulation result.Fig. 9 employ input data pretreatment but without using Phase Truncation Error accumulation when
Phase error simulation result.Figure 10 is to be imitated simultaneously using phase error when input data pretreatment and Phase Truncation Error accumulation
True result.Simulated conditions are：I=1 × 2n, Q=2 × 2n, n=0,1,2,3 ... 14,15 points altogether.
As shown in Figure 8,9, compared to traditional cordic algorithm, the cordic algorithm pre-processed using input data causes phase
Error keeps stable when input data amplitude is smaller, avoid signal amplitude it is smaller when, phase demodulation error becomes the problem of big.
As shown in Fig. 9,10, pre-processed still without using Phase Truncation Error accumulation compared to only with input data
Cordic algorithm, while phase error is caused using the CORDIC algorithms of input data pretreatment and Phase Truncation Error accumulation
Entirety diminishes.
Described above is only the preferred embodiments of the present invention, and protection scope of the present invention is not limited merely to above-mentioned implementation
Example, all technical schemes belonged under thinking of the present invention belong to protection scope of the present invention.It should be pointed out that for the art
Those of ordinary skill for, some improvements and modifications without departing from the principles of the present invention, these improvements and modifications
It should be regarded as protection scope of the present invention.
Claims (16)
1. a kind of phase demodulation apparatus based on cordic algorithm, the CORDIC for including amplitude computing module and phase operation module changes
For computing module；First output port of amplitude computing module is connected with phase operation module；It is characterized in that：The CORDIC
Interative computation module also includes phase error computing module；The phase demodulation apparatus also includes phase correction module；The amplitude fortune
The second output port for calculating module is connected with phase error computing module；The phase operation module and phase error computing module
Output end be connected as two output ports of CORDIC interative computations module with phase correction module, phase operation module will
The phase result of CORDIC interative computations is output to phase correction module.
A kind of 2. phase demodulation apparatus based on cordic algorithm according to claim 1, it is characterised in that：The phase error
Phase Truncation Error in computing module accumulation n times iterative process is simultaneously output to phase correction module, and N is the tired of cordic algorithm
Count iterations；The accumulated phase truncated error that phase error computing module exports is added to phase by the phase correction module
The phase result of computing module output, is corrected to phase.
A kind of 3. phase demodulation apparatus based on cordic algorithm according to claim 1, it is characterised in that：The phase operation
Module includes phased memory, the first multiplier, the first subtracter and phase accumulator register；The phased memory,
One multiplier, the first subtracter and phase accumulator register are sequentially connected；The amplitude computing module is defeated to the first multiplier
Go out data.
A kind of 4. phase demodulation apparatus based on cordic algorithm according to claim 3, it is characterised in that：The phase storage
Device is stored with to data arctan (2-t) divided by π and move to left the result that rounds up after the amplification of L-1 positions, i.e. phase(t)=round
((arctan(2-t)/π)×2L-1) (as follows), the anglec of rotation as phase interative computation is output to the first multiplier, wherein
T=0,1,2,3 ... T-1, T value are identical with accumulative iterations N, L be phased memory bit wide, round (x) represent pair
X rounds number (as follows)；The amplitude computing module exports δ to the first multiplieri, wherein δiIt is ith iteration
Direction of rotation, i=0,1,2,3 ... N-1 (as follows)；N number of data that first multiplier stores phased memory are multiplied by
δiAfterwards the first subtracter is output to as subtrahend；First subtracter multiplies the phase that phase accumulator register stores and first
The data of musical instruments used in a Buddhist or Taoist mass output are subtracted each other, and phase accumulator register, i.e. θ are arrived in as a result storagei+1=θi-δi×phase(t), as a result it is stored in phase
Position accumulator register, wherein θiIt is the phase of ith iteration, i and t value is identical；The phase accumulator register it is initial
It is worth for 0, i.e. θ0=0；The phase accumulator register is by the phase result θ of phase operation module n times interative computationNIt is output to phase
Bit correction module.
A kind of 5. phase demodulation apparatus based on cordic algorithm according to claim 4, it is characterised in that：The phase storage
The bit wide L values of device are identical with accumulative iterations N.
A kind of 6. phase demodulation apparatus based on cordic algorithm according to claim 1 or 2 or 3 or 4 or 5, it is characterised in that：
The phase error computing module adds up including phase error memory, the second multiplier, the second subtracter and phase error
Memory；The phase error memory, the second multiplier, the second subtracter and phase error accumulative register connect successively
Connect；The amplitude computing module is to the second multiplier output data.
A kind of 7. phase demodulation apparatus based on cordic algorithm according to claim 6, it is characterised in that：The phase error
It is stored with memory and data phase in phased memory(t)Corresponding data phase error(t), phase error(t)
=round (((arctan (2-t)/π)×2L-1-phase(t))×2K-1) (as follows), as Phase Truncation Error interative computation
The anglec of rotation be output to the second multiplier, wherein K is the bit wide of phase error memory；Second multiplier misses phase
The data of poor memory storage are multiplied by δiAfterwards the second subtracter is input to as minuend；Second subtracter is by phase error
The data that the phase of accumulator register storage exports with the second multiplier are subtracted each other, and phase error accumulator register is arrived in as a result storage,
That is Ei+1=Ei-δi×phase error(t), as a result it is stored in phase error accumulator register, wherein EiIt is the tired of ith iteration
Product Phase Truncation Error, i are identical with t value；The initial value of the phase error accumulator register is 0, i.e. E0=0；It is described
The result E that phase error accumulator register accumulates Phase Truncation Error n times iterationNIt is output to phase correction module.
A kind of 8. phase demodulation apparatus based on cordic algorithm according to claim 7, it is characterised in that：The phase error
The bit wide K of memory is ceil (log2Q)+2, wherein q value is identical with accumulative iterations N, ceil (x) represent to x to
Positive infinity rounds.
A kind of 9. phase demodulation apparatus based on cordic algorithm according to claim 7, it is characterised in that：The phasing
Module includes phase error computation module and first adder；The phase error computation module is connected with first adder；Institute
State the result E that phase error accumulator register accumulates Phase Truncation Error n times iterationNIt is output to phase error computation module；
The Phase Truncation Error E that the phase error computation module is accumulated to phase error accumulator register n times iterationNExecution moves to right K-
1 and the operation that rounds up, first adder, i.e. phase error=round (E are output to as phase errorN/2K -1), wherein phase error represent phase error (as follows)；The first adder by phase error phase error with
The result θ of the n times phase interative computation of phase operation module outputNIt is added, acquired results are the phase after correcting.
10. a kind of phase demodulation apparatus based on cordic algorithm according to claim 1 or 2 or 3 or 4 or 5, its feature exist
In：The phase correction module includes phase error computation module and first adder；The phase error computation module and the
One adder connects.
11. a kind of phase demodulation apparatus based on cordic algorithm according to claim 1 or 2 or 3 or 4 or 5, its feature exist
In：The phase demodulation apparatus also includes input data pretreatment module；The input data pretreatment module is transported with CORDIC iteration
Module connection is calculated, processing is amplified to pending two arbitrary signals I and Q, and result is output to amplitude computing module.
A kind of 12. phase demodulation apparatus based on cordic algorithm according to claim 11, it is characterised in that：The input number
Data preprocess module includes multiplication factor computing module, the 5th multiplier, the 6th multiplier；The multiplication factor computing module
Two output ports are connected with the 5th multiplier, the 6th multiplier respectively；The multiplication factor computing module comparator input signal I
With Q order of magnitude, and using larger absolute value M as divisor, with 2m+lDo division arithmetic, m value and accumulation iteration time
Number N are identical, and the result of gained is input to the 5th multiplier and the 6th multiplier after rounding；5th multiplier and the 6th multiplication
Device will input I and Q signal is multiplied by after multiplication factor and is output to amplitude computing module as the primary data of amplitude computing module, i.e.,
I0=I × floor (2N+1/ M), Q0=Q × floor (2N+1/ M), wherein I0And Q0It is the primary data of amplitude interative computation,
Floor (x) represents to perform floor operation, I to x0And Q0It is the primary data of amplitude interative computation.
13. a kind of phase demodulation apparatus based on cordic algorithm according to claim 1 or 2 or 3 or 4 or 5, its feature exist
In：The amplitude computing module include circulating successively the first register of connection, the first shift unit, first round up circuit,
3rd multiplier, second adder, the 3rd subtracter, the second register, the second shift unit, second round up circuit, the 4th
Multiplier, symbol decision module；First output port of the input data pretreatment module is connected with the first register；It is described
Second output port of input data pretreatment module is connected with the second register；First register follows with the 3rd subtracter
Ring connects；Second register connects with second adder circulation；The symbol decision module is connected with the second register, is sentenced
The symbol of data storage and it will determine that result is output to phase operation module and phase error computing mould in disconnected second register
Block.
A kind of 14. phase demodulation apparatus based on cordic algorithm according to claim 13, it is characterised in that：Described first moves
The data that position device and the second shift unit export to the first register and the second register respectively, which perform, moves to right i bit manipulations；Described
One rounds up circuit and second circuit that rounds up performs four to the data that the first shift unit and the second shift unit export respectively
House five enters operation；3rd multiplier and the 4th the multiplier circuit and second that rounded up respectively to first round up circuit
The data of output, which perform, multiplies δiOperation after be input to second adder and the 3rd subtracter；The second adder multiplies the 3rd
The data of musical instruments used in a Buddhist or Taoist mass output are stored to the second register after being added with the data that the second register stores；3rd subtracter is by
Storage is deposited to first after the data of four multipliers output carry out subtraction as the data that subtrahend and the first register store
Device；That is Ii+1=Ii-δi×round(Qi×2-i), operation result is stored in the first register, Qi+1=Qi+δi×round(Ii×
2-i), operation result is stored in the second register, wherein i=0,1,2,3 ... N-1, IiAnd QiThe respectively amplitude of ith iteration；
The symbol decision module is by the symbol decision result sgn (Q of the second register data storagei), i.e. δiIt is output to phase operation mould
Block and phase error computing module, wherein sgn (Qi) it is sign function, QiDuring ＜ 0, sgn (Qi)=- 1；QiWhen=0, sgn (Qi)
=0, QiDuring ＞ 0, sgn (Qi)=1.
15. a kind of phase detecting method of phase demodulation apparatus based on cordic algorithm according to claim 1-14 any one,
It is characterized in that：Comprise the steps of：
Amplitude interative computation：Amplitude computing module performs amplitude interative computation, the public affairs of amplitude interative computation to input signal I and Q
Formula is Ii+1=Ii-δi×round(Qi×2-i), Qi+1=Qi+δi×round(Ii×2-i), wherein I0=I, Q0=Q, symbol are sentenced
Disconnected module is by the direction of rotation δ of n times interative computationiIt is output to phase operation module and phase error computing module, wherein δi=
sgn(Qi), sgn (Qi) it is sign function, QiDuring ＜ 0, sgn (Qi)=- 1；QiWhen=0, sgn (Qi)=0, QiDuring ＞ 0, sgn (Qi)
=1；
Phase interative computation：Phase operation module carries out phase interative computation, and the formula of phase interative computation is θi+1=θi-δi×
phase(t), θ0=0；The result θ of phase interative computationNIt is output to the first adder of phase correction module；
Phase Truncation Error iteration adds up：Phase error computing module carries out Phase Truncation Error accumulation, and Phase Truncation Error is tired out
Long-pending calculation formula is：Ei+1=Ei-δi×phase error(t), E0=0；Phase Truncation Error accumulation results ENIt is output to phase
The phase error error calculating module of bit correction module；
Phase error computation；Phase error computation module carries out phase error computation, and calculation formula is Phase error=
round(EN/2K-1), Phase error represent phase error；
Phasing：First adder carries out phasing, and the calculation formula of phasing is Phase=θN+phase error
=θN+round(EN/2K-1)。
A kind of 16. phase detecting method of phase demodulation apparatus based on cordic algorithm according to claim 15, it is characterised in that：
Also include the pre-treatment step of input data：Comparator input signal I and Q order of magnitude, take absolute value big numerical value, is set to
M；With 2m+1Divided by M, to being multiplied respectively with input signal I and Q after result round numbers, and it is output to result as primary data
Amplitude computing module, m value is identical with accumulation iterations N, i.e. I0=I × floor (2N+1/ M), Q0=Q × floor (2N +1/ M), wherein floor (x) represents to perform floor operation, I to x0And Q0It is the primary data of amplitude interative computation.
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