CN104036709B - Display apparatus - Google Patents
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- CN104036709B CN104036709B CN201310072509.2A CN201310072509A CN104036709B CN 104036709 B CN104036709 B CN 104036709B CN 201310072509 A CN201310072509 A CN 201310072509A CN 104036709 B CN104036709 B CN 104036709B
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Abstract
A data driving circuit of a display apparatus is electrically connected with a display panel through a plurality of data lines. A scanning driving circuit is electrically connected with the display panel through a plurality of scanning lines, and is provided with multiple stages of driving units. Each stage of driving unit is provided with a shift control element and a driving element, the shift control element outputs a control signal according to a starting signal, the driving element outputs an output signal to the corresponding scanning line according to the control signal, a first trigger signal and a second trigger signal, and the output signal is used as the starting signal of the next stage of driving unit. At a first second trigger signal and in a blanking time after start of a data output time of the display panel, the time for upward transition of the second trigger signal and the time for downward transition of the first trigger signal at least partially overlap.
Description
Technical field
The present invention is on a kind of display device, especially in regard to a kind of flat display apparatus with scan drive circuit.
Background technology
Flat display apparatus（flat display apparatus）With its power consumption it is low, caloric value is few, it is lightweight and
The advantages of non-radiation type, it has been used in electronic product miscellaneous, and has little by little replaced traditional cathode-ray
Pipe（cathode ray tube,CRT）Display device.In the manufacturing technology of flat display apparatus, such as liquid crystal display device,
The element of scan drive circuit is made on glass substrate with thin film transistor (TFT) technique, to save the cost of turntable driving IC
Technology is referred to as GOP（Gate driver on panel）Technology.Manufactured by existing GOP technologies is mostly bilateral driving
Display device, that is to say, that in the viewing area of display device arranged on left and right sides respectively have one group of GOP circuit（Turntable driving
Circuit）, to avoid during unilateral driving large scale display device, scan drive circuit can because circuit it is distant, resistance value compared with
Phenomenon that is high and causing drive signal decrease.
Refer to shown in Fig. 1, it is a kind of function block schematic diagram of the scan drive circuit 1 of existing display device.Sweep
Retouch drive circuit 1 and include a clock pulse generator CK, first order driver element 11, second level driver element 12 ... and m grades of driving
Unit 1m.Wherein, clock pulse generator CK alternately produces two clock signal CK1 and CK2.Wherein, clock signal CK1 is in advance
The signal of the phases of clock signal CK2 mono-, and clock signal CK1 and CK2 are input into the driving of the first order driver element 11, second level respectively
Unit 12 ... and m grades of driver element 1m.In addition, first order driver element 11 receives an initial signal IN（It is for example, vertical same
Step signal STV）, and export an output signal OUT1, output signal OUT1A row pixel cell except being used to drive display device
Outward, and can be used as the initial signal of second level driver element 12.In other words, it is same per the output signal of one-level driver element output
The drive signal of the row pixel cells of Shi Zuowei mono- and its initial signal of next stage driver element.Thereby so that turntable driving electricity
Road 1 can sequentially export an output signal OUT from first order driver element 11 to m grades of driver element 1mk（1≦k≦m）, to make
It is the scanning signal of display device.Scanning signal is input into the driving transistor of pixel（Such as thin film transistor (TFT) TFT）Grid
(Gate) driving of, the conducting and cut-off of controllable driving transistor, then data-signal of arranging in pairs or groups, can make display device show image
Picture.
Refer to shown in Fig. 2A and Fig. 2 B, its clock signal CK1, CK2 for being respectively Fig. 1 and kth level driver element 1k（1
≦k≦m）Output signal waveform diagram.Wherein, driver element is in order to can reach enough driving forces, last driving
Element（Such as thin film transistor (TFT)）Size it is generally quite big, relatively its parasitic capacitance（Such as Cgd）Also can be quite very big.Therefore,
As shown in Figure 2 A, when clock signal CK2 transitions（High levle is become by low level, or low level is become by high levle）When, can be because
Signal is coupled（coupling）Effect and in thin film transistor (TFT) grid produce a ripple up or down（ripple）（Visually
It is noise）.In addition, during clock signal CK1 transitions also can because of coupling in the grid of thin film transistor (TFT) produce it is one downward
Or upward ripple.And when clock signal CK2 becomes high levle by low level, last driving element can be made（As film is brilliant
Body pipe）A leakage path is produced, therefore a larger ripple is had when clock signal CK2 becomes high levle by low level
（ripple）Produce.Therefore, prior art be in data entry time by the downward ripple produced by clock signal CK1
Coupling counters（decoupling）Produced upward ripple during clock signal CK2 transitions, and then offset output signal OUTk
In the produced noise of time t1, t2, t3 ... of Fig. 2A.
However, as shown in Figure 2 B, existing display device is empty at the beginning of a data entry time Td of each picture or in one
The shelves time（blanking time）During Tb, the clock signal CK2 of driver element 11 does not have the clock signal of previous phase
CK1 can offset the ripple produced by it.Therefore, time Tp1, the Tp2 ... such as Fig. 2 B are shown, in the picture frame time T of each picture
After beginning, output signal OUTkCan make because of couplings of the clock signal CK2 as produced by low level transition to high levle and electric leakage
With and produce one compared with high levle ripple voltage VP（Can betide each picture data entry time Td start after first
In clock signal CK2 and time dead Tb）.And, all driver element 1k electrically connected with clock signal CK2（1≦k≦m）
This kind of situation will occur.
Output signal OUT described abovekThe current potential that has ripple higher and when being input into the grid of this driving transistor, meeting
Cause the grid of driving transistor fairly close with the current potential of source electrode so that its pressure difference（That is Vgs）Diminish.If grid and source electrode
Critical voltage of the pressure difference more than driving transistor（Threshold voltage,Vth）, i.e. during Vgs ＞ Vth, driving crystal will be made
Pipe is turned on, and causes pixel voltage to produce electric leakage, causes the exception of display picture（Such as bright concealed wire）Phenomenon.
Therefore, how a kind of display device is provided, the pixel voltage leakage that signal is coupled and electric leakage effect is caused can be avoided
Electricity, in turn results in the abnormal phenomenon of display picture, it has also become one of important topic.
The content of the invention
In view of above-mentioned problem, the purpose of the present invention is that offer is a kind of avoids signal coupling and electric leakage effect caused
Pixel voltage leaks electricity, and in turn results in the display device of the abnormal phenomenon of display picture.
Be up to above-mentioned purpose, include according to a kind of display device of the invention, a display panel, a data drive circuit with
And scan driving circuit.Data drive circuit passes through multiple data wires and is electrically connected with display panel.Scan drive circuit passes through
Multiple scan lines are electrically connected with display panel, and with multiple drive power unit, driver elements at different levels and each scan line corresponding matching,
There is a shift control element and a driving element per one-level driver element.Shift control element is according to enabling signal output one
Control signal.Driving element is electrically connected with shift control element, and driving element is according to control signal, one first trigger signal and
Second trigger signal output one outputs signal to corresponding scan line, and output signal is believed as the startup of the driver element of next stage
Number, wherein, a sky of first the second trigger signal and display panel after starting in the data output time of display panel
In the shelves time, the second trigger signal upward transition time is least partially overlapped with the first trigger signal downward transition time.
Be up to above-mentioned purpose, according to a kind of display device of the invention include a display panel, a data drive circuit with
And scan driving circuit.Data drive circuit passes through multiple data wires and is electrically connected with display panel.Scan drive circuit passes through
Multiple scan lines are electrically connected with display panel, and with multiple drive power unit, driver elements at different levels and each scan line corresponding matching,
There is a shift control element, a driving element and a releasing member per one-level driver element.Shift control element is opened according to one
The dynamic control signal of signal output one.Driving element is electrically connected with shift control element, and driving element is according to control signal, one first
Trigger signal and one second trigger signal output one output signal to corresponding scan line, and output signal as the drive of next stage
The enabling signal of moving cell.Releasing member is electrically connected with driving element, and receives the control of a release signal, is believed with release control
Number or the electricity that has of output signal.
From the above, because according to display device of the invention, being by the data output time in display panel
In rear first the second trigger signal and a time dead of display panel, the second trigger signal upward transition time and first
The trigger signal downward transition time is least partially overlapped, or receives the control of a release signal by releasing member, to discharge control
The electricity that signal processed or output signal have.Thereby, can be when the picture frame time of each picture starts, using first second
In trigger signal appearance and time dead, the second trigger signal upward transition time is with the first trigger signal downward transition time extremely
Small part is overlapped, and can eliminate the second trigger signal because of the noise higher of the current potential produced by coupling and electric leakage effect；Or pass through
Release signal turns on releasing member, will be input into the noise of the ripple high that the control signal or output signal of driving element have
Discharge.Therefore, the present invention can make the grid of driving transistor in display panel pixel be not more than drive with the pressure difference of source electrode
The critical voltage of dynamic transistor, therefore display device will not produce the problem that pixel voltage leaks electricity, and also not result in display picture
It is abnormal（Bright concealed wire）Phenomenon.
Brief description of the drawings
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, not
Constitute limitation of the invention.In the accompanying drawings：
Fig. 1 is a kind of function block schematic diagram of the scan drive circuit of existing display device.
Fig. 2A and Fig. 2 B are respectively the waveform diagram of the output signal of clock signal and kth the level driver element of Fig. 1.
Fig. 3 is a kind of schematic diagram of display device of first embodiment of the invention.
Fig. 4 A illustrate for the function block of the wherein one-level driver element of the scan drive circuit of first embodiment of the invention
Figure.
Fig. 4 B are the circuit diagram of the driver element of Fig. 4 A.
Fig. 4 C are the waveform diagram of first trigger signal, the second trigger signal and output signal of Fig. 4 A.
Fig. 4 D are Chong Die with the downward transition time portion of the first trigger signal to show the second trigger signal upward transition time
It is intended to.
Fig. 4 E are the circuit diagram of the driver element of another implementation aspect of first embodiment of the invention.
Fig. 4 F are the partial schematic diagram of a clock pulse generator and scan drive circuit.
Fig. 5 is a kind of schematic diagram of display device of second embodiment of the invention.
Fig. 6 A are the function block schematic diagram of the wherein one-level driver element of the scan drive circuit of Fig. 5.
Fig. 6 B are the circuit diagram of the driver element of Fig. 6 A.
Fig. 7 A are the waveform diagram of the output signal of the driver element of scan drive circuit in the prior art.
Fig. 7 B are the waveform diagram of the output signal of the driver element of first embodiment of the invention.
Fig. 7 C are the waveform diagram of the output signal of the driver element of second embodiment of the invention.
Drawing reference numeral explanation：
1、23、33：Scan drive circuit
11st, 12,1k, 1m, 24,24a, 251~255,34：Driver element
2、3：Display device
21、31：Display panel
22、32：Data drive circuit
241、341：Shift control element
242、342：Driving element
243、343：Drop down element
244、344：Releasing member
A、B、C：Region
C：Electric capacity
CK：Clock pulse generator
CK1~CK4：Clock signal
CS：Control signal
D21~D2n：Data wire
IN：Initial signal
OUT、OUT1~OUT5、OUTk、OUTm：Output signal
RS：Release signal
STV：Vertical synchronizing signal
S21~S2m：Scan line
SS：Enabling signal
T：Picture frame time
T1~t3, Tp1~Tp5：Time
T1：The first transistor
T2：Transistor seconds
T3：Third transistor
Tb：Time dead
Td：The data output time
Tf、Tr：The transition time
To：Overlapping time
TS1、TS3：First trigger signal
TS2、TS4：Second trigger signal
VGL：Reference voltage
VP：Ripple voltage
Specific embodiment
Hereinafter with reference to correlative type, illustrate that wherein identical element will according to the display device of present pre-ferred embodiments
It is illustrated with identical reference marks.
Refer to shown in Fig. 3, it is a kind of schematic diagram of display device 2 of first embodiment of the invention.
Display device 2 includes a display panel 21, a data drive circuit 22 and scan driving circuit 23.Display surface
Plate 21 may be, for example, that liquid crystal display panel, organic electric-excitation luminescent displaying panel, LED display panel or other planes show
Show panel, be not limited in this.In addition, data drive circuit 22 is by multiple data wire D21~D2nWith display panel
21 electrical connections, and scan drive circuit 23 is by multiple scan line S21~S2mElectrically connected with display panel 21.Wherein, scan
Drive circuit 23 has multiple drive power unit（It is total m grades in this）, driver elements at different levels respectively with each scan line corresponding matching.Change
Yan Zhi, the driver element scan line fit applications corresponding with respectively per one-level, drives this to sweep with output drive signal
Retouch line.In addition, display device 2 more may include a sequential control circuit（Figure does not show）, when sequential control circuit can transmit vertical
The vision signal received from external interface is converted into data by arteries and veins signal and vertical synchronizing signal to scan drive circuit 23
Data-signal used by drive circuit 22, and transmit data-signal, horizontal clock signal and horizontal-drive signal to data-driven
Circuit 22.Additionally, scan drive circuit 23 according to vertical synchronizing signal turn in order this etc. scan line S21~S2m.When this etc. is swept
Retouch line S21~S2mWhen being respectively turned on, data drive circuit 22 will correspond to the data-signal of each row pixel cell, by the grade number
Pixel voltage signal is sent to the pixel electrode of each pixel cell according to line, display device 2 can be made to show an image.
In addition, refer to shown in Fig. 4 A, it is the wherein one-level drive of the scan drive circuit 23 of first embodiment of the invention
The function block schematic diagram of moving cell 24.
Every one-level driver element 24 of scan drive circuit 23 has a shift control element 241 and a driving element respectively
242.Shift control element 241 receives an enabling signal SS, and exports a control signal CS according to enabling signal SS.Wherein, move
Position control element 241 can be comprising pull-up（pull-up）Control circuit and or drop-down（pull-down）Control circuit etc.（Figure does not show
Show）.In this, pull-up control circuit is used to receive the enabling signal SS of previous stage, to trigger the output signal of this one-level, and it is drop-down
Control circuit is used to maintain the stabilization of the output signal of driver element 24.
Driving element 242 is electrically connected with shift control element 241.Driving element 242 receives shift control element 241 and exports
Control signal CS, one first trigger signal TS1 and one second trigger signal TS2, and according to control signal CS, one first triggering
Signal TS2 and the second trigger signal TS2 exports an output signal OUT to corresponding scan line.In this, this output signal OUT is
It is the scanning signal with the corresponding scan line of driver element 24.In addition, driver elements 24 of the output signal OUT as next stage
Enabling signal SS.In other words, the driver element 24 of next stage need to treat this one-level the output signal output OUT of driver element 24 it
Afterwards, can just be exported by driving.Thereby, can make the grade driver element 24 sequentially output signal output OUT and turn in order this etc.
Scan line S21~S2m.Wherein, when first order driver element of the driver element 24 for scan drive circuit 23, enabling signal SS
The vertical synchronizing signal that for example, sequential control circuit is sent（STV）.
In addition, please also refer to shown in Fig. 4 C, it is the first trigger signal TS1, the second trigger signal TS2 and the output of Fig. 4 A
Signal OUTkWaveform diagram.
As shown in Figure 4 C, picture frame time T includes the data output time（data output time）When Td and a neutral gear
Between（blanking time）Tb.Wherein, display panel 21 is in exporting a picture frame picture data in data output time Td, and empty
Shelves time Tb is for display panel 21 exports the time interval between two adjacent frames picture datas.In other words, in time dead
During Tb, display panel 21 does not export picture frame picture data, that is, all scan line S21~S2mSequentially output signal output OUT
（Scanning signal）Afterwards, the time interval as time dead Tb continued before the scanning of picture frame picture data next time.In this, first
Trigger signal TS1 and the second trigger signal TS2 can be respectively a pulse signal（Such as clock signal）.
First the second trigger signal TS2 and display panel 21 after the data output time Td of display panel 21 starts
Time dead Tb in, the second trigger signal TS2 upward transition times with the first trigger signal TS1 downward transition times at least portion
Divide and overlap.In this, as shown in Figure 4 D, so-called " partly overlapping " represents, the second trigger signal TS2 has upward transition time Tr
（Second trigger signal TS2 also has the downward transition time certainly）, and the first trigger signal TS1 has downward transition time Tf
（Certainly, the first trigger signal TS1 also has the upward transition time）, and upward transition time Tr of the second trigger signal TS2 with
Downward transition time Tf of the first trigger signal TS1 has the part for overlapping, as shown in the overlapping time To of Fig. 4 D.Preferably,
Second trigger signal TS2 upward transition times Tr are completely overlapped with the first trigger signal TS1 downward transition times Tf.But, it is
Simplification figure 4C, Fig. 4 C do not show upward transition time Tr and downwards of the first trigger signal TS1 and the second trigger signal TS2
Transition time Tf.
In addition, refer to shown in Fig. 4 B, it is the circuit diagram of the driver element 24 of Fig. 4 A.
In the present embodiment, driving element 242 has a first transistor T1, control end and the displacement of the first transistor T1
Control element 241 is electrically connected, and its first end is used to receive the second trigger signal TS2, its second end output signal output OUT.In
This, the control end of the first transistor T1 is the grid of the first transistor T1, and grid can receive the output of shift control element 241
Control signal CS, and second end of the first transistor T1 is alternatively referred to as the output end of driver element 24, and output signal output
OUT.When the control signal CS of the output of shift control element 241 turns on the first transistor T1, the second trigger signal TS2 can transmit
To second end of the first transistor T1（Output end）And output signal output OUT.Additionally, the first trigger signal TS1 is by one
Electric capacity C1 is electrically connected with the control end of the first transistor T1.
In addition, driver element 24 have more a drop down element 243, drop down element 243 respectively with shift control element 241 and
Driving element 242 is electrically connected.In this, drop down element 243 has a transistor seconds T2, the control end of transistor seconds T2（Grid
Pole）Electrically connected with shift control element 241, its first end is electrically connected with second end of the first transistor T1, its second end is electrically connected
Connect a reference voltage（It is the V of low level in thisGL）.The control of the acceptable shift control element 241 of the control end of transistor seconds T2
Make and turn on.Wherein, transistor seconds T2 is a pull-down transistor, its acceptable next stage output signal（Figure does not show）Control
System, will export the output signal OUT forcible abortings to this one-level, maintain the stabilization of output signal OUT.In other words, next stage
When output signal OUT is exported, the voltage of the output signal OUT of upper level is pulled down to reference voltage by pressure, so that upper level is defeated
The current potential for going out signal OUT is equal to reference voltage, to tie up the stabilization of upper level output signal OUT.Additionally, driver element 24 can more have
The first end for having an electric capacity C, electric capacity C is electrically connected with the control end of the first transistor T1, its second end respectively with the first transistor
The first end electrical connection at second end and transistor seconds T2 of T1.
Referring again to shown in Fig. 4 C, first the second trigger signal TS2 and sky after starting due to data output time Td
In shelves time Tb, the second trigger signal TS2 is by low voltage transition to high-tension time and the first trigger signal TS1 by high voltage
Conversion to low-voltage time portion is overlapped（In the prior art, first the second trigger signal after data output time Td starts
（Such as the clock signal CK2 of Fig. 2 B）And in time dead Tb, the second trigger signal（Such as the clock signal CK2 of Fig. 2 B）By low-voltage
Change paramount voltage time not necessarily with the first trigger signal（Such as the clock signal CK1 of Fig. 2 B）Changed to low electricity by high voltage
Pressure time-interleaving）So that display device 2 is when second trigger signal that the time dead Tb of each picture starts（Such as
Two trigger signal TS2）, using successional trigger signal（Such as the first trigger signal TS1）To offset the ripple produced by it.
Therefore, time Tp1, Tp2, the Tp3 ... such as Fig. 4 C are shown, when the picture frame time T of each picture starts, using differing a phase
The first trigger signal TS1 can eliminate current potential produced by the second trigger signal TS2 couplings noise higher（Such as dotted line
VPIt is shown）.Thereby, the grid of driving transistor in the pixel of display panel 21 can be made to be not more than driving with the pressure difference of source electrode brilliant
The critical voltage of body pipe, therefore display device 2 will not produce the problem that pixel voltage leaks electricity, and also not result in the exception of display picture
Phenomenon.
In addition, refer to shown in Fig. 4 E, it is the driver element 24a of another implementation aspect of first embodiment of the invention
Circuit diagram.
With the driver element 24 of Fig. 4 B primary difference is that, driver element 24a has more a releasing member 244, release
Element 244 is electrically connected with driving element 242, and receives the control of a release signal RS, with release control signal CS or output letter
The electricity of number OUT.In this implementation aspect, releasing member 244 respectively with the control of shift control element 241 and driving element 242
End electrical connection processed, and receive the control of release signal RS, with the electricity that release control signal CS has.Wherein, releasing member
244 have a third transistor T3, the control end of third transistor T3（Grid）Receive release signal RS, its first end and first
The control end electrical connection of transistor T1, its second end is electrically connected to reference voltage（The V of low levelGL）.Wherein, as shown in Figure 4 C,
If the noise of the ripple high that control signal CS has is when first trigger signal TS1 of each picture frame time T occurs, can profit
With the vertical synchronizing signal STV of sequential control circuit output as release signal RS, control is believed with turning on releasing member 244
The noise of the ripple high of number CS is discharged.If in addition, in the time dead Tb of picture frame time T, control signal CS has ripples high
The noise of ripple, then can make releasing member 244 receive the release signal RS of a high levle in time dead Tb and turn on release unit
Part 244, the noise of the ripple high of control signal CS is discharged（When control signal CS does not have ripple noise high, output signal
OUT there will not be）.Thereby, the grid of driving transistor in the pixel of display panel 21 can be made to be not more than with the pressure difference of source electrode
The critical voltage of driving transistor, therefore display device 2 will not produce the problem that pixel voltage leaks electricity, and also not result in display picture
Anomaly.
Additionally, in other implementation aspects（Figure does not show）, the first end of third transistor T3 can be also electrically connected to
Second end of the first transistor T1（That is output end）, and second end of third transistor T3 is electrically connected to reference voltage.Therefore, when
Third transistor T3 receives release signal RS and turns on third transistor T3, and output signal OUT is when having the noise of ripple high,
Can directly be discharged by third transistor T3, can equally be avoided the anomaly of display picture.
In addition, refer to shown in Fig. 4 F, it is the partial schematic diagram of a clock pulse generator and scan drive circuit.Wherein,
Display device 2 more may include a clock pulse generator CK, clock pulse generator CK respectively with driver element 1k at different levels（1≦k≦m）It is electrically connected
Connect, clock pulse generator CK produces multiple clock signals（The grade clock signal is respectively periodic continuous signal）.It is aobvious in this
Show 5 grades of driver element, and those skilled in the art can understand scan drive circuit 23 and clock pulse generator by the framework of Fig. 4 F
The integrated connection relation of CK.
In the present embodiment, clock pulse generator CK produces 4 groups of clock signal CK1~CK4, and is input into drivings at different levels respectively
Unit.Wherein, grade clock signal CK1~CK4 is included as the first trigger signal TS1, and can at least trigger as second
The clock signal of signal TS2.Specifically, in the grade driver element of Fig. 4 F, from top to bottom it is referred to as the first driver element
251st, the second driver element 252 ... and the 5th driver element 255.Wherein, clock signal CK1 is first order driver element 251
Second trigger signal TS2, and clock signal CK4 is the first trigger signal TS1 of first order driver element 251；Clock signal CK2
It is the second trigger signal TS2 of second level driver element 252, and clock signal CK1 is touched for the first of second level driver element 252
Signalling TS1；Clock signal CK3 is the second trigger signal TS2 of third level driver element 253, and clock signal CK2 is the 3rd
First trigger signal TS1 of level driver element 253；Clock signal CK4 is the second trigger signal of fourth stage driver element 254
TS2, and clock signal CK3 is the first trigger signal TS1 of fourth stage driver element 254；Additionally, clock signal CK1 is the 5th
Second trigger signal TS2 of level driver element 255, and clock signal CK4 is the first trigger signal of level V driver element 255
TS1, by that analogy.
Because clock signal CK1 is first clock signal of clock pulse generator CK, and it is first order driver element 251
Second trigger signal TS2, though and clock signal CK4 is the 4th clock signal of clock pulse generator CK, and be the first order drive
First trigger signal TS2 of unit 251, but because the first trigger signal TS1 and the second trigger signal TS2 are respectively periodically
Continuous signal, and a phase is differed, therefore clock signal CK1 and CK4 is also respectively periodic continuous signal, and one phase of difference
Position.Thereby, can as shown in Figure 4 C, by clock signal CK4（First trigger signal TS1）Produced coupling comes during transition
Offset clock signal CK1（Second trigger signal TS2）Transition（After especially clock signal CK1 starts in the data output time
Switched to switch to high levle by low level in high levle and time dead by low level for the first time）When produced upward ripple, enter
And offset output signal OUT1Produced ripple.
Illustrate again, the present invention is not intended to limit clock pulse generator CK and can produce how many clock signals to turntable driving electricity
The grade driver element 1k on road 23（1≦k≦m）As long as the transition of last clock signal can be eliminated（Or suppress）First
Ripple produced by clock signal transition, and can be eliminated in time dead（Or suppress）Produced by first clock signal transition
Ripple.In addition, the present invention does not also limit the first trigger signal TS1 and the source one of the second trigger signal TS2 is set to clock pulse
The clock signal that generator CK is produced, the first trigger signal TS1 and the second trigger signal TS2 is alternatively other control circuit institutes
The control signal of generation, as long as the control signal for producing is pulse signal, and opens in the data output time Td of display panel 21
First the second trigger signal TS2 after beginning and in the time dead Tb of display panel 21, the second upward transitions of trigger signal TS2
Time is least partially overlapped with the first trigger signal TS1 downward transition times.
In addition, please respectively refer to shown in Fig. 5, Fig. 6 A and Fig. 6 B, wherein, Fig. 5 shows for one kind of second embodiment of the invention
The schematic diagram of showing device 3, Fig. 6 A illustrate for the function block of the wherein one-level driver element 34 of the scan drive circuit 33 of Fig. 5
Figure, and Fig. 6 B are the circuit diagram of the driver element 34 of Fig. 6 A.
As shown in figure 5, display device 3 includes that a display panel 31, a data drive circuit 32 and one scan drive electricity
Road 33.Data drive circuit 32 is by multiple data wire D31~D3nElectrically connected with display panel 31, and scan drive circuit 33
It is by multiple scan line S31~S3mElectrically connected with display panel 31.Wherein, scan drive circuit 33 has multiple drive power unit
34, driver elements at different levels 34 respectively with each scan line corresponding matching.It is respectively turned on this etc. and sweeps when scan drive circuit 33 is exported
Retouch line S31~S3mWhen, data drive circuit 32 will each row pixel cell of correspondence data-signal, by the grade data wire by picture
Plain voltage signal is sent to the pixel electrode of each pixel cell, so that the display image of display device 3.
As shown in Figure 6A, have respectively per one-level driver element 34 a shift control element 341, a driving element 342 and
One releasing member 344.Shift control element 341 exports a control signal CS according to an enabling signal SS.Driving element 342 and shifting
Position control element 341 is electrically connected.Driving element 342 is according to control signal CS, one second trigger signal TS3 and one second triggering letter
Number TS4 exports an output signal OUT to corresponding scan line.In this, the first trigger signal TS3 and the second trigger signal TS4 points
Wei not clock pulse generator（Figure does not show）Produced clock signal, and output signal OUT to be the driver element 34 corresponding
The scanning signal of scan line.In addition, output signal OUT also as next stage driver element 34 enabling signal SS.Thereby, may be used
Make the grade driver element 34 of scan drive circuit 33 sequentially output signal output OUT and turn in order this etc. scan line S31~
S3m.Wherein, when first order driver element of the driver element 34 for scan drive circuit 33, enabling signal SS can be SECO
The vertical synchronizing signal that circuit is sent.In addition, releasing member 344 is electrically connected with driving element 342, and receive a release signal
The control of RS, with release control signal CS or the electricity of output signal OUT.Wherein, the triggerings of the first trigger signal TS3 and second letter
Number TS4 is when the time dead Tb of display panel 31 and does not have a pulse signal（The respectively signal of discontinuity）.
In the present embodiment, as shown in Figure 6B, driving element 342 has a first transistor T1, the first transistor T1's
Control end is electrically connected with shift control element 341, and its first end is used to receive the second trigger signal TS4, and the output of its second end is defeated
Go out signal OUT.In addition, releasing member 344 has a third transistor T3, the control end of third transistor T3（Grid）Reception is released
Discharge signal RS, its first end is electrically connected with the control end of the first transistor T1, and its second end is electrically connected to reference voltage（Low level
VGL）.
Additionally, the driver element 34 of the present embodiment has more a drop down element 343, drop down element 343 is controlled with displacement respectively
Element processed 341 and driving element 342 are electrically connected.In this, drop down element 343 has a transistor seconds T2, transistor seconds T2
Control end（Grid）Electrically connected with shift control element 341, its first end is electrically connected with second end of the first transistor T1, its
Second end electrically connects a reference voltage（The V of low levelGL）.Additionally, driver element 34 can more have an electric capacity C, the first of electric capacity C
End electrically connected with the control end of the first transistor T1, its second end respectively with second end of the first transistor T1 and transistor seconds
The first end electrical connection of T2.Wherein, other technical characteristics of driver element 34 can refer to the driver element 24a of first embodiment,
Repeated no more in this.
In addition, refer to shown in Fig. 7 A to Fig. 7 C, wherein, Fig. 7 A are the driving list of scan drive circuit in the prior art
The output signal of unit（Scanning signal）Waveform diagram, Fig. 7 B for first embodiment of the invention driver element output signal
Waveform diagram, and Fig. 7 C for second embodiment of the invention driver element output signal waveform diagram.
As shown in Figure 7 A, in the prior art, output signal OUT has in the region A when data output time, Td started
Have one compared with high levle ripple, and the actual magnitude of voltage for measuring is about 4.7V.But in Fig. 7 B first embodiment and Fig. 7 C
In the output signal OUT of two embodiments, the interior ripple without this high levle of region B, C.Therefore, the present invention can be avoided really
Display device is because of the display picture exception caused by the pixel voltage electric leakage produced by ripple（Bright concealed wire）Phenomenon.
In sum, because according to display device of the invention, by after the data output time of display panel starts
First the second trigger signal and display panel a time dead in, the second trigger signal upward transition time with first touch
Downward transition time of signaling is least partially overlapped, or receives the control of a release signal by releasing member, with release control
The electricity that signal or output signal have.Thereby, can be touched using first second when the picture frame time of each picture starts
Signal in appearance and time dead, the second trigger signal is by low voltage transition to voltage time high and the first trigger signal by height
Voltage conversion is least partially overlapped to the low-voltage time, eliminates the second trigger signal because of the current potential produced by coupling and electric leakage effect
Noise higher；Or releasing member is turned on by release signal, the control signal or output signal of driving element will be input into
The noise of the ripple high being had is discharged.Therefore, the present invention can make the grid of driving transistor in display panel pixel with
The pressure difference of source electrode is not more than the critical voltage of driving transistor, therefore display device will not produce the problem that pixel voltage leaks electricity,
The exception of display picture is not resulted in yet（Bright concealed wire）Phenomenon.
The foregoing is only illustrative, rather than for restricted.It is any without departing from spirit and scope of the invention, and to it
The equivalent modifications for carrying out or change, are intended to be limited solely by claims.
Claims (9)
1. a kind of display device, it is characterised in that including：
One display panel；
One data drive circuit, is electrically connected by multiple data wires with the display panel；And
Scan driving circuit, is electrically connected by multiple scan lines with the display panel, and with multiple drive power unit, it is at different levels
Driver element and each scan line corresponding matching, have per one-level driver element：
One shift control element, a control signal is exported according to an enabling signal；
One driving element, is electrically connected with the shift control element, and the driving element is touched according to the control signal, one first
Signal and one second trigger signal output one outputs signal to corresponding scan line, and the output signal as next stage
The enabling signal of driver element；And
One releasing member, electrically connects with the driving element, and receives the control of a release signal, to discharge the control signal
Or the electricity that the output signal has；
Wherein, the driving element has a first transistor, and the first end of the first transistor is used to receive described second
Trigger signal, the second end of the first transistor exports the output signal；
Wherein, first trigger signal is all coupled to described the second of the first transistor with second trigger signal
End.
2. display device according to claim 1, it is characterised in that
The control end of the first transistor is electrically connected with the shift control element.
3. display device according to claim 2, it is characterised in that driver elements at different levels have more a drop down element, institute
Drop down element is stated to be electrically connected with the shift control element and the driving element respectively.
4. display device according to claim 3, it is characterised in that the drop down element has a transistor seconds, institute
The control end for stating transistor seconds is electrically connected with the shift control element, the second end of its first end and the first transistor
Electrical connection, its second end electrically connects a reference voltage.
5. display device according to claim 4, it is characterised in that the releasing member has a third transistor, institute
The control end for stating third transistor receives the release signal, and its first end is electrically connected with the control end of the first transistor,
Its second end is electrically connected to the reference voltage.
6. display device according to claim 4, it is characterised in that the releasing member has a third transistor, institute
The control end for stating third transistor receives the release signal, and its first end is electrically connected with the second end of the first transistor,
Its second end is electrically connected to the reference voltage.
7. display device according to claim 1, it is characterised in that opened in the data output time of the display panel
First the second trigger signal after beginning and in a time dead of the display panel, the upward transition of the second trigger signal
Time is least partially overlapped with the first trigger signal downward transition time.
8. display device according to claim 7 a, it is characterised in that picture frame time of the display panel is comprising described
Data output time and the time dead, the display panel export a picture frame picture data in the data output time,
And the time dead is the time interval between the display panel exports two adjacent frames picture datas.
9. display device according to claim 1, it is characterised in that further include：
One clock pulse generator, electrically connects with driver elements at different levels respectively, and the clock pulse generator produces multiple clock signals, described
Clock signal is included at least as one first clock signal of first trigger signal and as second trigger signal
One second clock signal.
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| CN201310072509.2A CN104036709B (en) | 2013-03-07 | 2013-03-07 | Display apparatus |
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| CN201310072509.2A CN104036709B (en) | 2013-03-07 | 2013-03-07 | Display apparatus |
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| CN104036709B true CN104036709B (en) | 2017-05-24 |
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| CN106782421B (en) * | 2017-03-10 | 2019-08-13 | 深圳市华星光电技术有限公司 | Image element driving method and device |
| TWI616860B (en) * | 2017-06-27 | 2018-03-01 | 友達光電股份有限公司 | Gate driving circuit and operating method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110210955A1 (en) * | 2010-03-01 | 2011-09-01 | Chih-Yuan Chang | Gate driver and related driving method for liquid crystal display |
| TW201214372A (en) * | 2010-09-21 | 2012-04-01 | Chunghwa Picture Tubes Ltd | Display device |
| CN102945656A (en) * | 2012-06-07 | 2013-02-27 | 友达光电股份有限公司 | Gate driver of display device and operation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110210955A1 (en) * | 2010-03-01 | 2011-09-01 | Chih-Yuan Chang | Gate driver and related driving method for liquid crystal display |
| TW201214372A (en) * | 2010-09-21 | 2012-04-01 | Chunghwa Picture Tubes Ltd | Display device |
| CN102945656A (en) * | 2012-06-07 | 2013-02-27 | 友达光电股份有限公司 | Gate driver of display device and operation method thereof |
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