CN104022025A - 一种耐高压脉宽调制控制器终端制造方法 - Google Patents

一种耐高压脉宽调制控制器终端制造方法 Download PDF

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CN104022025A
CN104022025A CN201410249560.0A CN201410249560A CN104022025A CN 104022025 A CN104022025 A CN 104022025A CN 201410249560 A CN201410249560 A CN 201410249560A CN 104022025 A CN104022025 A CN 104022025A
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徐谦刚
杜林德
李�昊
李文军
杨虹
薛建国
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TIANSHUI TIANGUANG SEMICONDUCTOR CO Ltd
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    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction

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Abstract

一种耐高压脉宽调制控制器终端制造方法,制造步骤:采用离子注入工艺,在预留的浓硼终止高压环区域进行硼离子注入,能量E=(50.0~80.0)keV,剂量D=(2.00~8.00)E+15cm-2;采用常规氧化扩散工艺10′(O2)+(30~100)′(O2+H2)+10′(O2)进行硼再扩散工艺,将设计好的浓硼终止高压环区域扩散出预订电阻值(1.0~5.0Ω)的硼掺杂区域。本发明从芯片设计入手,改变常规脉宽调制控制器终端晶体管设计,为常规终端晶体管设计浓硼终止高压环区域,通过离子注入工艺技术为脉宽调制控制器输出晶体管制作一电压缓冲环,以提高击穿电压、场开启电压,可有效防止电过应力引起的器件失效,保证器件工作在高压时的可靠性。

Description

一种耐高压脉宽调制控制器终端制造方法
技术领域
本发明涉及脉宽调制控制器终端耐高压技术领域,特别涉及使用离子注入工艺技术实现脉宽调制控制器输出晶体管表面终止高压环结构,实现脉宽调制控制器输出晶体管耐高压的技术,具体说是一种耐高压脉宽调制控制器终端制造方法。
背景技术
随着科学技术的飞速发展、微电子技术的广泛应用,脉宽调制控制器在耐高压能力、抗电磁干扰等方面要求越来越高。
随着现代化的进展,电子装备和武器系统的精度、威力和机动性日益提高,装备的使用环境日趋复杂、严酷,对于高可靠双极型集成电路的质量、性能和可靠性各方面都提出了较高要求,因此电子元器件的可靠性对系统的可靠性有举足轻重的作用,而电子元器件耐高压能力是影响元器件可靠性的一个主要因素,近年来,因元器件耐高压能力失效所造成的经济损失非常大,解决耐高压能力失效问题显得至关重要;当前,在元器件的生产、封装、测试及适用过程中,大家都采用了相应的耐高压防护措施,如果在元器件设计时就考虑到耐高压能力,才是解决耐高压能力失效的最根本、最有效途径。
发明内容
本发明的目的是针对现有技术中存在的问题提供一种耐高压脉宽调制控制器终端制造方法。
一种耐高压脉宽调制控制器终端制造方法,包括以下步骤:
a )重新设计脉宽调制控制器终端晶体管的结构:在常规脉宽调制控制器终端晶体管的周边设计浓硼终止高压环区域,为浓硼终止高压环工艺技术预留空间;
b )采用离子注入工艺:通过离子注入机对预留的浓硼终止高压环区域进行硼离子注入,离子注入机注入离子能量E=(50.0~80.0)keV,注入离子剂量D=(2.00~8.00)E+15cm-2
c )采用常规氧化扩散工艺10′(O2)+(30~100)′(O2+ H2)+ 10′(O2)进行硼再扩散工艺,将设计好的浓硼终止高压环区域扩散出预订电阻值(1.0~5.0Ω)的硼掺杂区域。
本发明具有以下有益效果:
本发明从芯片设计入手,改变常规脉宽调制控制器终端晶体管设计,为常规终端晶体管设计浓硼终止高压环区域,通过离子注入工艺技术为脉宽调制控制器输出晶体管制作一电压缓冲环,以提高击穿电压、场开启电压,可有效防止电过应力引起的器件失效,保证器件工作在高压时的可靠性;通过常规氧化扩散工艺在终端晶体管周围形成限场环,改变晶体管周围电场分布,达到提高终端晶体管耐压能力的目的,进而提高整体脉宽调制控制器耐压能力的目的。
附图说明
图1为常规脉宽调制控制器终端正视图;
图2为常规脉宽调制控制器终端截面图;
图3为本发明脉宽调制控制器终端正视图;
图4为本发明脉宽调制控制器终端截面图。
图中1为脉宽调制控制器终端晶体管,2为浓硼终止高压环区域,3为脉宽调制控制器终端晶体管集电极。
具体实施方式
下面结合附图和实施例对本发明做进一步说明:
在常规脉宽调制控制器终端晶体管周围制作高浓度P型区域(如图3所示),使输出晶体管周围被P型高浓度参杂区包围,改变了常规脉宽调制控制器终端晶体管的结构设计,该区域与终端晶体管形成一个突变PN结,在工作状态终端晶体管集电极的电场分布会因此发生改变,提高集电极的击穿电压,达到提高终端晶体管击穿电压的目的,进而提高脉冲调制控制的终端耐高压能力。
在常规脉宽调制控制器终端晶体管周围制作高浓度P型区域(如图4所示),提高集电极的击穿电压,达到提高终端晶体管击穿电压的目的,进而提高脉冲调制控制的终端耐高压能力。
由图3和图4可以看出,在工作状态终端晶体管集电极的电场分布会因此发生改变,提高集电极的击穿电压,达到提高终端晶体管击穿电压的目的,进而提高脉冲调制控制的终端耐高压能力。
通过晶体管图示仪进行测试所得数据显示,常规脉冲调制控制的终端耐压能力在30~40V之间,采用本发明的脉冲调制控制的终端耐压能力可以提升到60V以上,选取不同的工艺条件能够达到不同的耐压能力,依据产品要求和实际使用领域而定,采用本发明的脉冲调制控制的终端耐压能力最大可以达到120V。
实施例1
 1、重新设计脉宽调制控制器终端晶体管的结构:在常规脉宽调制控制器终端晶体管的周边设计浓硼终止高压环区域,为浓硼终止高压环工艺技术预留空间;
2、采用离子注入工艺:使用型号为NV-10-160的离子注入机对预留的浓硼终止高压环区域进行硼离子注入,离子注入机注入离子能量E=50.0keV,注入离子剂量D=2.00E+15cm-2
3、采用常规氧化扩散工艺:将离子注入工艺完成的晶片装入专用氧化炉管,工艺温度1050℃,10′(O2)+ 30′(O2+ H2)+ 10′(O2)进行硼再扩散工艺,将设计好的浓硼终止高压环区域扩散出预订电阻值(4.0~5.0Ω)的硼掺杂区域。
通过晶体管图示仪进行测试,脉冲调制控制的终端耐压能力为60V~70V。
实施例2
 1、重新设计脉宽调制控制器终端晶体管的结构:在常规脉宽调制控制器终端晶体管的周边设计浓硼终止高压环区域,为浓硼终止高压环工艺技术预留空间;
2、采用离子注入工艺:使用型号为NV-10-160的离子注入机对预留的浓硼终止高压环区域进行硼离子注入,离子注入机注入离子能量E=50.0keV,注入离子剂量D=5.00E+15cm-2
3、采用常规氧化扩散工艺:将离子注入工艺完成的晶片装入专用氧化炉管,工艺温度1050℃,10′(O2)+ 50′(O2+ H2)+ 10′(O2)进行硼再扩散工艺,将设计好的浓硼终止高压环区域扩散出预订电阻值(2.0~3.0Ω)的硼掺杂区域。
通过晶体管图示仪进行测试,脉冲调制控制的终端耐压能力为80V~90V。
实施例3
 1、重新设计脉宽调制控制器终端晶体管的结构:在常规脉宽调制控制器终端晶体管的周边设计浓硼终止高压环区域,为浓硼终止高压环工艺技术预留空间;
2、采用离子注入工艺:使用型号为NV-10-160的离子注入机对预留的浓硼终止高压环区域进行硼离子注入,离子注入机注入离子能量E=50.0keV,注入离子剂量D=8.00E+15cm-2
3、采用常规氧化扩散工艺:将离子注入工艺完成的晶片装入专用氧化炉管,工艺温度1050℃,10′(O2)+ 100′(O2+ H2)+ 10′(O2)进行硼再扩散工艺,将设计好的浓硼终止高压环区域扩散出预订电阻值(1.0~2.0Ω)的硼掺杂区域。
通过晶体管图示仪进行测试,脉冲调制控制的终端耐压能力为90V~100V。
实施例4
1、重新设计脉宽调制控制器终端晶体管的结构:在常规脉宽调制控制器终端晶体管的周边设计浓硼终止高压环区域,为浓硼终止高压环工艺技术预留空间;
2、采用离子注入工艺:使用型号为NV-10-160的离子注入机对预留的浓硼终止高压环区域进行硼离子注入,离子注入机注入离子能量E=80.0keV,注入离子剂量D=2.00E+15cm-2
3、采用常规氧化扩散工艺:将离子注入工艺完成的晶片装入专用氧化炉管,工艺温度1050℃,10′(O2)+ 50′(O2+ H2)+ 10′(O2)进行硼再扩散工艺,将设计好的浓硼终止高压环区域扩散出预订电阻值(4.0~5.0Ω)的硼掺杂区域。
通过晶体管图示仪进行测试,脉冲调制控制的终端耐压能力为70V~80V。
实施例5
1、重新设计脉宽调制控制器终端晶体管的结构:在常规脉宽调制控制器终端晶体管的周边设计浓硼终止高压环区域,为浓硼终止高压环工艺技术预留空间;
2、采用离子注入工艺:使用型号为NV-10-160的离子注入机对预留的浓硼终止高压环区域进行硼离子注入,离子注入机注入离子能量E=80.0keV,注入离子剂量D=8.00E+15cm-2
3、采用常规氧化扩散工艺:将离子注入工艺完成的晶片装入专用氧化炉管,工艺温度1050℃,10′(O2)+ 100′(O2+ H2)+ 10′(O2)进行硼再扩散工艺,将设计好的浓硼终止高压环区域扩散出预订电阻值(1.0~2.0Ω)的硼掺杂区域。
通过晶体管图示仪进行测试,脉冲调制控制的终端耐压能力为100~120V。

Claims (1)

1.一种耐高压脉宽调制控制器终端制造方法,其特征在于包括以下步骤:
a )重新设计脉宽调制控制器终端晶体管的结构:在常规脉宽调制控制器终端晶体管的周边设计浓硼终止高压环区域,为浓硼终止高压环工艺技术预留空间;
b )采用离子注入工艺:通过离子注入机对预留的浓硼终止高压环区域进行硼离子注入,离子注入机注入离子能量E=(50.0~80.0)keV,注入离子剂量D=(2.00~8.00)E+15cm-2
c )采用常规氧化扩散工艺10′(O2)+(30~100)′(O2+ H2)+ 10′(O2)进行硼再扩散工艺,将设计好的浓硼终止高压环区域扩散出预订电阻值(1.0~5.0Ω)的硼掺杂区域。
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US6150225A (en) * 1996-12-20 2000-11-21 Nec Corporation Method for fabricating a semiconductor device having vertical and lateral type bipolar transistors
CN103165443A (zh) * 2011-12-16 2013-06-19 上海华虹Nec电子有限公司 一种绝缘栅晶体管器件及其制造工艺方法
CN103346085A (zh) * 2013-07-02 2013-10-09 江苏博普电子科技有限责任公司 一种提高双极型晶体管BVcbo的生产工艺

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6150225A (en) * 1996-12-20 2000-11-21 Nec Corporation Method for fabricating a semiconductor device having vertical and lateral type bipolar transistors
CN103165443A (zh) * 2011-12-16 2013-06-19 上海华虹Nec电子有限公司 一种绝缘栅晶体管器件及其制造工艺方法
CN103346085A (zh) * 2013-07-02 2013-10-09 江苏博普电子科技有限责任公司 一种提高双极型晶体管BVcbo的生产工艺

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