CN104021061B - USB/PCI/LAN OC instruction satellite ground detection module - Google Patents
USB/PCI/LAN OC instruction satellite ground detection module Download PDFInfo
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Abstract
Do you the present invention relates to a kind of USB/PCI/LAN? OC instruction satellite ground detection module.Develop corresponding integrated ground surface checkout equipment according to the concrete function of each satellite, there is the defects such as interface is various, the construction cycle is long.Module of the present invention is formed by USB/PCI/LAN multibus core board and OC instruction general detection interface floor combination; The former comprises FPGA device, DDRSDRAM device, FLASH device, PCI device, LAN device, USB device, core board power-supplying circuit and core board I/O; The latter comprises 5V and turns 28V circuit, OC instruction issue circuitry and OC command reception circuit; The OC command logic of interface base plate, by core board I/O, the PLB bus being articulated in FPGA Embedded Soft Core Microblaze completes control and data communication.USB, PCI, LAN tri-kinds of standard industry Interface design on one piece of core board, can be met the satellite prosecutor equipment fast integration based on these three kinds of standard industry interfaces by the present invention.
Description
Technical field
The invention belongs to satellite ground detection technique field, be specifically related to a kind of USB/PCI/LANOC instruction satellite ground detection module.
Background technology
Along with the increasing that country drops into satellite industry, satellite model task significantly increases, and the task amount of satellite ground checkout equipment also significantly increases thereupon.Before, the mode of corresponding integrated ground surface checkout equipment is developed according to the concrete function of each satellite, there is the defects such as interface is various, the construction cycle is long, reliability is poor, cost is large, maintainability is poor, can not meet the demand to research and development progress under existing large task amount.
Summary of the invention
The object of this invention is to provide a kind of USB/PCI/LANOC instruction satellite ground detection module, Satellite General is detected interface solidification, standardization, commercialization, modularization.
The technical solution adopted in the present invention is:
USB/PCI/LANOC instruction satellite ground detection module, is characterized in that:
Described module is formed by USB/PCI/LAN multibus core board and OC instruction general detection interface floor combination;
Described USB/PCI/LAN multibus core board includes FPGA device, DDRSDRAM device, FLASH device, PCI device, LAN device, USB device, core board power-supplying circuit and core board I/O;
Described OC instruction general detection interface base plate includes 5V and turns 28V circuit, OC instruction issue circuitry and OC command reception circuit.
Described USB/PCI/LAN multibus core board and described OC instruction general detection interface base plate complete structure and electrical connection by 2.0mm spacing double-row needle and 2.0mm spacing double-row hole linker; The OC command logic of described OC instruction general detection interface base plate, by described core board I/O, the PLB bus being articulated in described FPGA Embedded Soft Core Microblaze completes control and data communication.
The present invention has the following advantages:
The present invention changes in the past according to a satellite model detection demand, redesign, develop, debug, test the working method of a set of ground checkout equipment, by USB/PCI/LANOC instruction satellite ground detection module involved in the present invention, Satellite General is detected interface solidification, standardization, commercialization, modularization.Commercialization characteristic effectively reduces satellite ground checkout equipment construction cycle and cost of development; Solidification, normalized characteristic make the satellite ground checkout equipment that built by the present invention more stable, reliable; The satellite ground checkout equipment maintenance that modular nature makes to be built by the present invention and maintenance convenient and swift.
USB, PCI, LAN tri-kinds of standard industry Interface design on one piece of core board, can be met the satellite prosecutor equipment fast integration based on these three kinds of standard industry interfaces by the present invention.Core board utilizes the dirigibility of the self-defined IP of FPGA Embedded Soft Core Microblaze complete the integrated of USB, PCI, LAN tri-kinds of standard industry interfaces and control, break through the framework in the past adding the integrating control of FPGA with CPU, reduce cost of development, be conducive to the repair and upgrade of product.
Accompanying drawing explanation
Fig. 1 is USB/PCI/LANOC instruction satellite ground detection module block diagram.
Fig. 2 is USBOC instruction flow chart.
Fig. 3 is LANOC instruction flow chart.
Fig. 4 is PCIOC instruction flow chart.
Embodiment
Below in conjunction with embodiment, the present invention will be described in detail.
See Fig. 1, a kind of USB/PCI/LANOC instruction satellite ground detection module involved in the present invention, is formed by USB/PCI/LAN multibus core board and OC instruction general detection interface floor combination.Described USB/PCI/LAN multibus core board includes FPGA device (XILINXFPGASpartan6), DDRSDRAM device (MT47H64M16), FLASH device (JS28F640J3), PCI device (PLX9054), LAN device (W5300), USB device (CY7C68013), core board power-supplying circuit and core board I/O(6Microblaze customized IP core).Described OC instruction general detection interface base plate includes 5V and turns 28V circuit, OC instruction issue circuitry and OC command reception circuit.
Described USB/PCI/LAN multibus core board and described OC instruction general detection interface base plate complete structure and electrical connection by 2.0mm spacing double-row needle and 2.0mm spacing double-row hole linker; The OC command logic of described OC instruction general detection interface base plate, by described core board I/O, the PLB bus being articulated in described FPGA Embedded Soft Core Microblaze completes control and data communication.
USB, PCI, LAN tri-kinds of standard industry Interface design on one piece of core board, can be met the satellite prosecutor equipment fast integration based on these three kinds of standard industry interfaces by module.Core board utilizes the dirigibility of the self-defined IP of FPGA Embedded Soft Core Microblaze complete the integrated of USB, PCI, LAN tri-kinds of standard industry interfaces and control, break through the integrating control framework in the past adding FPGA with CPU, reduce cost of development, base plate is linked by 2.0mm spacing double-row needle and 2.0mm spacing double-row hole with core board, core board and base plate are solidified and commercialization respectively, is conducive to the repair and upgrade of product.
See the USB/PCI/LANOC instruction flow chart of Fig. 2-4, idiographic flow is as described below:
Module power up rear first by the procedural copy of FPGA Embedded Soft Core Microblaze in DDRSDRAM, Microblaze jumps to DDRSDRAM Program code section start and starts run time version, enter after Microblaze shown in Fig. 2 reads USB status register S1 and judge that USB receives FIFO and whether has several S2, read USB if any number by the PLB bus of Microblaze and receive FIFOS3, read a byte and judge whether it is OXEB95S4, read core board I/O status register and USB status register S7 in this way, judge that in USB status register, USB sends whether FIFO is sky S9, if not empty wait 1ms reads core board I/O status register and USB status register S7 again, if sky is by core board I/O status register, USB status register adds 0XEB97 frame head and data length framing write USB sends FIFOS11.Read a byte and judge whether it is OXEB95S4, if not being that OXEB95 judges whether reading one byte is OXEB90S5, read core board I/O status register in this way and judge that OC instruction sends whether FIFO is sky S10, as sky reads USB receiving data frames the 3rd byte, by its value read data frame content, write OC instruction sends FIFOS12, if not empty wait 1ms reads core board I/O status register S8 again.As S3 reads a byte neither OXEB95 neither just empty USB reception FIFOS6 by OXEB90.Data S2 is not had as USB receives in FIFO, just read core board I/O status register S13, judge whether OC command reception FIFO is empty, if not being that the empty USB status register that reads judges whether USB transmission FIFO is sky S16, if not being empty wait for that 1ms again reads USB status register and judges whether USB transmission FIFO is sky S16, the empty OC of reading command reception FIFO writes S17 in DDRSDRAM in this way, then read core board I/O status register and judge whether OC command reception FIFO is sky S19, sky will receive OC director data interpolation 0XEB96 frame head and data length framing write USB transmission FIFOS20 in write DDRSDRAM in this way, if not being empty wait for that 1ms again reads core board I/O status register and judges whether OC command reception FIFO is sky S19, as judged, OC command reception FIFO is sky S14, just return and enter LANOC instruction flow chart reading LAN status register as shown in Figure 3.
Fig. 2 USBOC instruction flow chart returns and enters after LANOC instruction flow chart reads LAN status register S22 as shown in Figure 3, judge that LAN receives FIFO and whether has several S23, read LAN if any number by the PLB bus of Microblaze and receive FIFOS24, read a byte and judge whether it is OXEB95S25, read core board I/O status register and LAN status register S27 in this way, judge that in LAN status register, LAN sends whether FIFO is sky S30, if not empty wait 1ms reads core board I/O status register and LAN status register S27 again, if sky is by core board I/O status register, LAN status register adds 0XEB97 frame head and data length framing write LAN sends FIFOS32.Read a byte and judge whether it is OXEB95S25, if not being that OXEB95 judges whether reading one byte is OXEB90S26, read core board I/O status register in this way and judge that OC instruction sends whether FIFO is sky S31, as sky reads LAN receiving data frames the 3rd byte, by its value read data frame content, write OC instruction sends FIFOS33, if not empty wait 1ms reads core board I/O status register S28 again.As S25 reads a byte neither OXEB95 neither just empty LAN reception FIFOS29 by OXEB90.Data S23 is not had as LAN receives in FIFO, just read core board I/O status register S34, judge whether OC command reception FIFO is sky S35, if not being that the empty LAN status register that reads judges whether LAN transmission FIFO is sky S37, if not being empty wait for that 1ms again reads LAN status register and judges whether LAN transmission FIFO is sky S37, the empty OC of reading command reception FIFO writes S38 in DDRSDRAM in this way, then read core board I/O status register and judge whether OC command reception FIFO is sky S40, sky will receive OC director data interpolation 0XEB96 frame head and data length framing write LAN transmission FIFOS41 in write DDRSDRAM in this way, if not being empty wait for that 1ms again reads core board I/O status register and judges whether OC command reception FIFO is sky S40, as judged, OC command reception FIFO is sky S35, just return and enter PCIOC instruction flow chart reading PCI status register as shown in Figure 4.
Fig. 3 LANOC instruction flow chart returns to enter after PCIOC instruction flow chart as shown in Figure 4 reads PCI status register S43 and judges that PCI receives FIFO and whether has several S44, read PCI if any number by the PLB bus of Microblaze and receive FIFOS45, read a byte and judge whether it is OXEB95S46, read core board I/O status register and PCI status register S49 in this way, judge that in PCI status register, PCI sends whether FIFO is sky S51, if not empty wait 1ms reads core board I/O status register and PCI status register S49 again, if sky is by core board I/O status register, PCI status register adds 0XEB97 frame head and data length framing write PCI sends FIFOS53.Read a byte and judge whether it is OXEB95S46, if not being that OXEB95 judges whether reading one byte is OXEB90S47, read core board I/O status register in this way and judge that OC instruction sends whether FIFO is sky S52, as sky reads PCI receiving data frames the 3rd byte, by its value read data frame content, write OC instruction sends FIFOS54, if not empty wait 1ms reads core board I/O status register S50 again.As S46 reads a byte neither OXEB95 neither just empty PCI reception FIFOS48 by OXEB90.Data S44 is not had as PCI receives in FIFO, just read core board I/O status register S55, judge whether OC command reception FIFO is sky S56, if not being that the empty PCI status register that reads judges whether PCI transmission FIFO is sky S58, if not being empty wait for that 1ms again reads PCI status register and judges whether PCI transmission FIFO is sky S58, the empty OC of reading command reception FIFO writes S59 in DDRSDRAM in this way, then read core board I/O status register and judge whether OC command reception FIFO is sky S61, sky adds 0XEB96 frame head and data length framing write PCI transmission FIFOS62 by receiving OC director data in write DDRSDRAM in this way, if not being empty wait for that 1ms again reads core board I/O status register and judges whether OC command reception FIFO is sky S61, as judged, OC command reception FIFO is sky S56, just return and enter USBOC instruction flow chart reading USB status register as shown in Figure 2.
PCIOC instruction flow chart enters Fig. 2 USBOC instruction flow chart and reads USB status register S1 after returning as shown in Figure 4, enters flow cycles until module power-down quits work.
Content of the present invention is not limited to cited by embodiment, and the conversion of those of ordinary skill in the art by reading instructions of the present invention to any equivalence that technical solution of the present invention is taked, is claim of the present invention and contains.
Claims (1)
1.USB/PCI/LANOC instruction satellite ground detection module, is characterized in that:
Described module is formed by USB/PCI/LAN multibus core board and OC instruction general detection interface floor combination;
Described USB/PCI/LAN multibus core board includes FPGA device, DDRSDRAM device, FLASH device, PCI device, LAN device, USB device, core board power-supplying circuit and core board I/O;
Described OC instruction general detection interface base plate includes 5V and turns 28V circuit, OC instruction issue circuitry and OC command reception circuit;
Described USB/PCI/LAN multibus core board and described OC instruction general detection interface base plate complete structure and electrical connection by 2.0mm spacing double-row needle and 2.0mm spacing double-row hole linker; The OC command logic of described OC instruction general detection interface base plate, by described core board I/O, the PLB bus being articulated in described FPGA Embedded Soft Core Microblaze completes control and data communication;
USB, PCI, LAN tri-kinds of standard industry interfaces are arranged on one piece of core board by described module, utilize the dirigibility of the self-defined IP of FPGA Embedded Soft Core Microblaze complete the integrated of USB, PCI, LAN tri-kinds of standard industry interfaces and control, its idiographic flow is:
Step one: module power up rear first by the procedural copy of FPGA Embedded Soft Core Microblaze in DDRSDRAM, Microblaze jumps to DDRSDRAM Program code section start and starts run time version, Microblaze judges after reading USB status register that USB receives FIFO and whether has number, reads USB receive FIFO if any number by the PLB bus of Microblaze;
Read a byte and judge whether it is OXEB95, read core board I/O status register and USB status register in this way, judge in USB status register, whether USB transmission FIFO is empty, if not empty wait 1ms reads core board I/O status register and USB status register again, as core board I/O status register, USB status register are added 0XEB97 frame head and data length framing write USB transmission FIFO by sky;
Read a byte and judge whether it is OXEB95, if not being that OXEB95 judges whether reading one byte is OXEB90, read core board I/O status register in this way and judge whether OC instruction transmission FIFO is empty, as sky reads USB receiving data frames the 3rd byte, by its value read data frame content, write OC instruction sends FIFO, if not empty wait 1ms reads core board I/O status register again;
OXEB95 reads a byte neither neither just empty USB reception FIFO by OXEB90, data are not had as USB receives in FIFO, just read core board I/O status register, judge whether OC command reception FIFO is empty, if not being whether be sky to the empty USB of reading status register if judging that USB sends FIFO, if not being that the empty 1ms of wait again reads USB status register whether judge that USB sends FIFO be sky, the empty OC of reading command reception FIFO writes in DDRSDRAM in this way, then read core board I/O status register and judge whether OC command reception FIFO is empty, sky will receive OC director data interpolation 0XEB96 frame head and data length framing write USB transmission FIFO in write DDRSDRAM in this way, if not being empty wait for that 1ms again reads core board I/O status register and judges whether OC command reception FIFO is sky, as judged, OC command reception FIFO is empty, just return and enter LANOC instruction flow reading LAN status register,
Step 2: USBOC instruction flow judges that LAN receives FIFO and whether has number, reads LAN receive FIFO if any number by the PLB bus of Microblaze after returning and entering LANOC instruction flow reading LAN status register;
Read a byte and judge whether it is OXEB95, read core board I/O status register and LAN status register in this way, judge in LAN status register, whether LAN transmission FIFO is empty, if not empty wait 1ms reads core board I/O status register and LAN status register again, as core board I/O status register, LAN status register are added 0XEB97 frame head and data length framing write LAN transmission FIFO by sky;
Read a byte and judge whether it is OXEB95, if not being that OXEB95 judges whether reading one byte is OXEB90, read core board I/O status register in this way and judge whether OC instruction transmission FIFO is empty, as sky reads LAN receiving data frames the 3rd byte, by its value read data frame content, write OC instruction sends FIFO, if not empty wait 1ms reads core board I/O status register again;
OXEB95 reads a byte neither neither just empty LAN reception FIFO by OXEB90, data are not had as LAN receives in FIFO, just read core board I/O status register, judge whether OC command reception FIFO is empty, if not being whether be sky to the empty LAN of reading status register if judging that LAN sends FIFO, if not being empty wait for that 1ms again reads LAN status register and judges whether LAN transmission FIFO is sky, the empty OC of reading command reception FIFO writes in DDRSDRAM in this way, then read core board I/O status register and judge whether OC command reception FIFO is empty, sky will receive OC director data interpolation 0XEB96 frame head and data length framing write LAN transmission FIFO in write DDRSDRAM in this way, if not being empty wait for that 1ms again reads core board I/O status register and judges whether OC command reception FIFO is sky, as judged, OC command reception FIFO is empty, just return and enter PCIOC instruction flow chart reading PCI status register,
Step 3: LANOC instruction flow returns to enter after PCIOC instruction flow reads PCI status register and judges that PCI receives FIFO and whether has number, reads PCI receive FIFO if any number by the PLB bus of Microblaze;
Read a byte and judge whether it is OXEB95, read core board I/O status register and PCI status register in this way, judge in PCI status register, whether PCI transmission FIFO is empty, if not empty wait 1ms reads core board I/O status register and PCI status register again, as core board I/O status register, PCI status register are added 0XEB97 frame head and data length framing write PCI transmission FIFO by sky;
Read a byte and judge whether it is OXEB95, if not being that OXEB95 judges whether reading one byte is OXEB90, read core board I/O status register in this way and judge whether OC instruction transmission FIFO is empty, as sky reads PCI receiving data frames the 3rd byte, by its value read data frame content, write OC instruction sends FIFO, if not empty wait 1ms reads core board I/O status register again;
OXEB95 reads a byte neither neither just empty PCI reception FIFO by OXEB90, data are not had as PCI receives in FIFO, just read core board I/O status register, judge whether OC command reception FIFO is empty, if not being whether be sky to the empty PCI of reading status register if judging that PCI sends FIFO, if not being that the empty 1ms of wait again reads PCI status register whether judge that PCI sends FIFO be sky, the empty OC of reading command reception FIFO writes in DDRSDRAM in this way, then read core board I/O status register and judge whether OC command reception FIFO is empty, sky adds 0XEB96 frame head and data length framing write PCI transmission FIFO by receiving OC director data in write DDRSDRAM in this way, if not being empty wait for that 1ms again reads core board I/O status register and judges whether OC command reception FIFO is sky, as judged, OC command reception FIFO is empty, just return and enter USBOC instruction flow reading USB status register, enter flow cycles until module power-down quits work.
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| CN107741545A (en) * | 2017-10-27 | 2018-02-27 | 深圳航天东方红海特卫星有限公司 | A kind of portable 24 road OC instructions isolation detector of microsatellite |
| CN113204188B (en) * | 2021-04-26 | 2022-07-19 | 中国人民解放军国防科技大学 | Multimode-driven quick-response satellite switching instruction system and design and application method thereof |
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