CN104009749B - Modularization self-organization configuration circuit for reconfigurable hardware circuit - Google Patents
Modularization self-organization configuration circuit for reconfigurable hardware circuit Download PDFInfo
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Abstract
The invention discloses a modularization self-organization configuration circuit for a reconfigurable hardware circuit. The modularization self-organization configuration circuit is characterized by being composed of a plurality of configuration modules which are in one-to-one correspondence connection with a reconfigurable circuit module through communication interfaces according to a topological structure. The modularization self-organization configuration circuit has the advantages that configuration module networks (configuration circuits) of different topological structures can be conveniently constructed according to different reconfigurable hardware circuits; secondly, all the configuration modules in the network can be organized in a self mode, the connection sequence of the configuration modules can be customized and can be established and deleted in the configuration process, it means that a configuration access can be modified midway according to needs and can be positioned to the specific configuration module or bypasses the specific configuration module, and therefore fault isolation is achieved; thirdly, the whole configuration module network can be controlled through any communication interface, so that the configuration of the whole reconfigurable hardware circuit can be finished, multiple communication interfaces can be selected to be configured in parallel, and the speed, flexibility and the like of configuration are improved.
Description
Technical field
The invention belongs to electronic technology and bionics techniques field, it is related to a kind of hardware circuit, particularly to a kind of restructural
The modularity self-organizing configuration circuit of hardware circuit.
Background technology
In electronic circuit field, programmable or reconfigurable hardware circuit, the motility being used with it, widely should obtain
With.Programmable hardware circuit refers to the circuit that logic function can be changed by specific configuration information, and fpga is exactly typical case
Programmable hardware circuit (device).Reconfigurable circuit to be allowed realizes specific logic function, needs for configuration information to pass through certain
The mode of kind is loaded in circuit, and conventional configuration information load mode has based on spi interface, based on jtag interface etc..
With the development of bionics techniques, design and realize to be capable of the bionical circuit of some mechanism of dynamic analog organism, such as
Nerve network circuit, reference multicellular tissue division and the Embryonic System of differentiation characteristic, become electronic technology one new
Application direction.Require can conveniently to realize the loading of configuration information, readings as Embryonic System, replicate and
Modification, bionical circuit typically requires system can local dynamic station configure.But the configuration mode based on spi interface, jtag interface
Collocation channel is difficult to change in circuit running, configuration information is freely organized and carries out multi-channel parallel operating difficultiess,
It is difficult to meet the configuration needs of bionical circuit.
In order to meet the requirement to configuration for the bionical circuit, with reference to configuration mode based on spi, jtag interface, design towards
Reconfigurable hardware circuit, the modularity self-organizing configuration circuit of particularly bionical circuit.
Content of the invention
It is an object of the invention to provide a kind of modularity self-organizing configuration circuit of the reconfigurable hardware circuit of flexible configuration.
Realize the modularity self-organizing configuration circuit that the object of the invention the technical scheme is that reconfigurable hardware circuit,
It is made up of according to topological structure by communication interface the configuration module that several are connected one to one with reconfigurable circuit module.
Described topological structure is preferably von Neumann structure.
Described configuration circuit, comprising one or more can be with the input communication interface of concurrent working.
Described configuration module, its input port and output port comprise 1 global synchronization input end of clock mouth, 1 overall situation
Synchronous reset input port, several communication interfaces and 1 configuration interface, several configuration modules described pass through communication interface phase
Connect network consisting；Its internal 1 input buffer of inclusion, 11 bit pattern depositor, 13 input interface select to post
The unique thing of storage, 14 output interface mask register, 1 command register, 1 data register, whole network
Reason address and some combinational logic circuits.
Described each communication interface, comprises 2 bit pattern inputs, 1 data input, 2 bit pattern outputs and 1 data output.
Described configuration interface, the address using including the data wire of read-write configuration information, read-write configuration information and control letter
Number line and interrupt application signal.
Described input buffer, comprises 2 input instruction buffers, 1 Input Data Buffer, 2 reverse inputs refer to
Make buffer and 1 reverse Input Data Buffer, described input interface mask register, is some bit widths, described output
Interface mask register, is some bit widths, and described command register is at least 2 bit widths, and described data register is at least 4
Bit width, in configuration module, the data of all depositors and buffer loads all on global synchronization input end of clock mouth rising edge edge
Carry out.
Described combinational logic circuit includes 5 application of logic circuit module, 4 MUX and 2 groups of decoders.
In described configuration module, all pattern inputs are connected to input instruction buffer by the first MUX, lead to
Cross the second MUX and be connected to reverse input instruction buffer；All data inputs are connected to by the 3rd MUX
Input Data Buffer, is connected to reverse Input Data Buffer by the 4th MUX；Described first MUX
Controlled by input interface mask register with the 3rd MUX, the 4th MUX and the second MUX are exported
Interface mask register controls；The input of mode register is input instruction buffer；The input of input interface mask register
For the second application of logic circuit module；The input of output interface mask register and command register is Input Data Buffer, is subject to
3rd application of logic circuit module controls；The input of data register is Input Data Buffer, output interface mask register, physics
Address, the data wire interrupting application signal or reading and writing configuration information, are controlled by the first application of logic circuit module；Second logic circuit
The input of module is that the 3rd application of logic circuit module, input interface mask register and all patterns input；3rd logic circuit mould
The input of block is reverse input instruction buffer and mode register；The input of the 4th application of logic circuit module is the 3rd logic circuit
Module, output interface mask register and input interface mask register；The input of the first application of logic circuit module is the 3rd logic
Circuit module and command register；The input of the 5th application of logic circuit module is reverse input instruction buffer and interrupts letter of application
Number；All pattern outputs are all obtained by the first decoder, and signal is originated as input instruction buffer, the 5th application of logic circuit module
Or 0, controlled by the 4th application of logic circuit module；All data outputs are all obtained by the second decoder, and signal is originated as reverse
Input Data Buffer, command register, data register or Input Data Buffer, by the 4th application of logic circuit module control
System；The signal of control signal wire is originated as command register and the first application of logic circuit module；Read-write configuration information data wire be
It is directly connected to data register during output.
The feature of the modularity self-organizing configuration circuit that the present invention provides is:
1st, it is mainly used in the configuration information management of modular reconfigurable hardware circuit, can be according to different reconfigurable hardwares
The convenient configuration module network (configuration circuit) building different topology structure of circuit.Each configuration module has multiple communications and connects
Mouth in that context it may be convenient to build the network of various topological structure, directly delete or input connects 0 by no communication interface.
2nd, each configuration module in network can with self-organizing, the order of connection of each configuration module can self-defined and
Configuration process creates, deletes it means that configuration path can be changed as required halfway, can navigate to and specifically join
Put module, or bypass specific configuration module, realize Fault Isolation.
3rd, whole configuration module network can be controlled from any one communication interface, to complete whole reconfigurable hardware circuit
Configuration.Multiple communication interface parallel deployments can also be selected, to improve speed and the motility of configuration.
4th, can by test pattern acquisition module mac address, collocation channel set up situation and interrupt signal.Mac ground
Location, the situation of setting up of configuration passband can use and the fault diagnosis of configuration module, and interrupt signal can be used for reconfigurable hardware circuit
Application etc. is interrupted in reconstruct.Interrupt signal can be coupled to the return circuit of control signal, realize automatically interrupting application.
5th, can by bypass dr by way of by quick-downloading for configuration data to specific configuration module, to complete restructural
The partial reconfiguration of hardware circuit module.Can pass through to read the configuration information of reconfigurable hardware circuit, shift in conjunction with data,
The part that the modes such as data register bypass quickly realize reconfigurable hardware circuit replicates.
The present invention will be further described below in conjunction with the accompanying drawings.
Brief description
Fig. 1 is the structural representation of the present invention.
Fig. 2 is the basic block diagram of configuration module in configuration circuit.
Fig. 3 is the configuration path schematic diagram that configuration module self-organizing is formed.
Specific embodiment
Fig. 1, Fig. 2 show one embodiment of the present of invention, and it is for 13 row 3 row reconfigurable circuit module composition
The configuration circuit of reconfigurable hardware circuit design, using the von Neumann structure of 3 row 3 row, this configuration circuit comprises 9
Individual configuration module, each configuration module corresponds to 1 reconfigurable circuit module.The configuration module of the i-th row jth row is designated as cbij, that is,
This configuration circuit includes cb00, cb01, cb02, cb10, cb11, cb12, cb20, cb21, cb22 totally 9 configuration modules, each
The mac address of configuration module is followed successively by 0000(binary system, and acquiescence is hereafter identical), 0001,0010,0100,0101,0110,
1000th, 1001,1010, with these configuration modules correspond the reconfigurable circuit module that is connected be designated as respectively rcb00,
rcb01、rcb02、rcb10、rcb11、rcb12、rcb20、rcb21、rcb22.The input port of each configuration module and output
Port comprises 1 global synchronization input end of clock mouth clk, 1 global synchronization the RESET input mouth rst, 7 communication interfaces
Cif1, cif2, cif3, cif4, cif5, cif6, cif7(configuration module is not limited to 7 communication interfaces) and 1 configuration interface
cfif.Described configuration module pass through 4 communication interfaces cif4, cif5, cif6, cif7 respectively with right, under, left, upper four direction
Configuration module communication interface docking, be connected with each other network consisting.3 communication interfaces that each configuration module does not use
Cif1, cif2, cif3 input directly connects in 0, Fig. 1 omits.Whole configuration circuit can select each configuration module in networking
There is no the communication interface (cif1, cif2, cif3) being used as input communication interface, for the input and output of configuration data.This
Communication interface cif5 of communication interface cif6 of example option and installment module cb00 and configuration module cb20 connects as input communication
Mouthful.
The structure of each configuration module is as shown in Fig. 2 its internal inclusion 1 input buffer ibuf, 11 bit pattern are posted
Storage m0,13 input interface mask register in_sel, 14 output interface mask register path, 1 instruction are posted
Storage ir, 1 data register dr, a unique physical address mac of whole network and some combinational logic circuits (include 5
Application of logic circuit module logic0, logic1, logic2, logic3 and logic4,4 MUX mux1, mux2, mux3,
Mux4 and 2 group of decoder dmuxs1 and dmuxs2).
Described input buffer ibuf, comprise 2 input instruction buffer mi*, 1 Input Data Buffer di*, 2
Reversely input instruction buffer mi# and 1 reverse Input Data Buffer di#.Described in_sel, is 3 bit widths, from low level to
A high position is designated as s0, s1, s2 successively, but is not limited to 3 bit widths.Described output interface mask register path, is 4 bit widths, from
Low level is designated as p0, p1, p2, f successively to a high position, and low 3 are collectively referred to as inputting mask register path, but are not limited to 4 bit widths.Institute
State command register ir, bit wide (being designated as x+1) at least 2, no maximum limit, be designated as successively from low level to a high position i0,
i1、……、ix.Described data register dr, bit wide (being designated as y+1) at least 4, no maximum limit, from low level to a high position according to
Secondary be designated as d0, d1 ..., dy.In configuration module, the data of all depositors and buffer loads all in global synchronization
Clock input port clk rising edge edge is carried out.
Described each communication interface, comprises 2 bit pattern input mi, 1 data input di, 2 bit patterns export mo and 1 data
Output do, the corresponding signal of each communication interface passes through later plus numbering distinguishes (mi, di, the mo and do difference as cif2
It is designated as mi2, di2, mo2, do2).
Described configuration interface, the address using including the data wire db of read-write configuration information, read-write configuration information and control
Holding wire ab and interruption application signal int.
Described configuration module, its annexation is as follows: 7 pattern input mi1 mi7 pass through MUX mux1
It is connected to input instruction buffer mi*, reverse input instruction buffer mi# is connected to by MUX mux4；7 data
Input di1 di7 is connected to Input Data Buffer di* by MUX mux2, by MUX mux3 even
It is connected to reverse Input Data Buffer di#；MUX mux1 and mux2 are controlled by input interface mask register in_sel,
MUX mux3 and mux4 are controlled by output interface mask register path；The input of mode register m0 is input instruction
Buffer mi*；The input of input interface mask register in_sle is logic0；Output interface mask register path and instruction
The input of depositor ir is Input Data Buffer di*, is controlled by logic1；The input of data register dr is input data
Buffer di*, input mask register path, physical address mac, the number interrupting application signal int or reading and writing configuration information
According to line db, controlled by logic3；The input of logic0 is logic1, input interface mask register in_sel and 7 patterns are defeated
Enter mi1 mi7；The input of logic1 is reverse input instruction buffer mi# and mode register m0；The input of logic2 is
Logic1, output interface mask register path and input interface mask register in_sel；The input of logic3 is logic1
With command register ir；The input of logic4 is reverse input instruction buffer mi# and interrupts application signal int；7 patterns are defeated
Go out mo1 mo7 all to obtain by decoder dmuxs1, signal is originated as input instruction buffer mi*, logic4 or 0, is subject to
Logic2 controls；7 data output do1 do7 are all obtained by decoder dmuxs2, and signal is originated as reverse input data
Buffer di#, command register ir, data register dr or Input Data Buffer di*, are controlled by logic2；Control letter
The signal of number line ab is originated as command register ir and logic3；The data wire db of read-write configuration information is to be directly connected to during output
To data register dr.7 pattern input mi1 mi7 constitute one group of bus, referred to as pattern input bus mib.7 data
Input di1 di7 constitutes one group of bus, referred to as data input bus (DIB) dib.
Described configuration module, including reset state, idle condition, seizure condition three state.
Described reset state, refers to when rst high level is effective, ibuf, m0, in_sel, path, if are reset to 0 state.
Described idle condition, refers to the transitive state between reset state to seizure condition.Described seizure condition, refers in sky
Under not busy state, after configuration module communication interface receives the mi of entry instruction shift mode, leave idle condition, but do not enter
State before row reset operation.Under non-reset state: the low level of mi moves into m0 at clk edge；If in_sel is not equal to
0, then the mi of the communication interface of in_sel numerical value reference numeral is loaded into mi*, di and is loaded into di*, otherwise mi* and di* is impartial
In 0；If f is equal to 1 and path is not equal to 0, the mi of the communication interface of path numerical value reference numeral is loaded into mi#, di and adds
It is downloaded to di#, otherwise mi# and di# is equal to 0.When idle condition transfers to seizure condition, receive entry instruction shift mode
Communication interface numbering is not loaded into in_sel.
Described seizure condition, including time-out, instruction shift, data displacement and 4 kinds of mode of operations of loading, is corresponding in turn to mi*
Corresponding state during equal to 0,1,2,3, but it is not limited only to this corresponded manner.When f is equal to 0, all communication interfaces
Mo is equal to 0.When f is equal to 1, the mo(of the communication interface of path numerical value reference numeral is designated as mo*) it is equal to mi*, if path
With in_sle, the mo(of the communication interface of in_sel numerical value reference numeral is designated as mo#) it is equal to mi#.When int is equal to 0,
Mo# is equal to mi#, if int is equal to the result that 1, mo# is equal to int and mi#, this is processed as all negating 2 of mi#,
But it is not limited to this kind of process.Non- mo* and mo# in all communication interfaces is equal to 0.
Described park mode, refers to the pattern that path, ir, dr keep constant.
Described instruction shift pattern, when f is equal to 0, di* moves into path from p0, and when f is equal to 1, di moves into ir, ir from i0
The do(of the communication interface that data is sent to path numerical value reference numeral from ix removal is designated as do*).If path and in_sel is not
Equal, the do(of the communication interface of in_sel numerical value reference numeral is designated as do#) it is equal to di#.
Described data shift mode, dr is from low level to high bit shift.Ir low 2 be equal to 0 when, be test pattern: move into d0
Data be di#, dy data is moved out to do#.Ir low 2 be equal to 2 when, be bypass mode: do* be equal to di*, if path with
In_sel is unequal, and do# will be equal to di#.Ir low 2 be equal to 1 or 3 when, be basic model: move into d0 data be di*, dy
Data is moved out to do*, if in_sel and path is low 3, do# will be equal to di#.
Described loading pattern, the data of dr is updated or writes Programmable Logic Device or module quilt by db, ab
Warm reset.When m0 is equal to 1, module warm reset, ibuf, in_sel, path, ir are by clear 0.When m0 is equal to 0: if ir is minimum
Position is 0, and mac, int and path are loaded into dr；If ir is low, and 2 data being equal to 1, db are loaded into dr；If id is low 2
Data equal to 3, dr writes reconfigurable logic circuit by db；If ir have high-order (except minimum 2) i2, i3 ..., ix,
This several can be used as the address read and write.
Operation principle:
The configuration information taking each reconfigurable circuit module comprises 2 groups, is referred to as depositor 0 and depositor 1, depositor
0 and depositor 1 be 8 bit widths, then need 2 addresses in ir, that is, after removing lowest order and time low level, also need to 1, therefore
Take ir to be 3, take dr to be 8.Initial time, the int input of all configuration interfaces is all taken as 0.Carry out following behaviour in turn below
Make.
(1) whole configuration circuit resets.Rst puts high at least one clk cycle.
(2) set up the collocation channel being sequentially connected cb00, cb10, cb11, cb01, cb02, and tested.Cb00's
Mi6 and di6 of cif6 adds following information: mi6=01(binary number), di6=01101_01100_01111_01100_01110
(binary number, " _ " meaningless, it is intended merely to display convenient), the value that concrete meaning is to maintain mi6 was 01 common di6 length week
Phase, in the meantime, order from a high position to low level for the data of di6 is moved into di6 successively, di6 goes to next after the length cycle
Individual operation or mi=00), above-mentioned input is abbreviated as cif6i=01-01101_01100_01111_01100_01110(hereinafter
It is also adopted by this shorthand method).Then cif6i=01-000_000_000_000_000, path configuration completes, i.e. collocation channel wound
Build and complete, now the path depositor of cb00.path=1101(cb00, acquiescence similarly hereinafter), cb10.path=1100, cb11.path
=1111, cb01.path=1100, cb02=1110, the ir of 5 configuration modules is 000, path simplification figure such as Fig. 3 institute of foundation
Show.Take cif6i==10-0；Mac, int, path are now loaded into dr by cif6i==11-0, and wherein high 4 is mac, low 3
For path, interposition is int.Take cif6i=10-123456789a16(expression latter half is 16 system numbers, identical hereinafter), this
The value of group data is meaningless, only and length has relation it is therefore an objective to result result in removal dr), remove the data in dr, result
Represent the mo6=10 of cb00, do=for cif6o=10-00000101_01000100_01010111_00010100_00110110(
00000101_01000100_01010111_00010100_00110110).If during reading dr, in this path
Any one int in 5 configuration modules is changed into 1, and the mo6 of output will negate, i.e. mo6=01.
(3) cb00, cb10, cb11, cb01, cb02 are configured: by 16 binary data a0, b0, c0, d0, e0 and a1,
B1, c1, d1, e1 originally do not write in the address 0,1 of above-mentioned 5 modules successively.Cif6i=01-011_011_011_011_011, if
Put 5 configuration modules and be and write as dr data pattern to address 0；cif6i=10-e0d0c0b0a016, configuration data is moved into dr；
Cif6i=11-0, by the configuration data writing address 0 in dr.Repeat the above steps, by the configuration data write of address 1: cif6i
=01-111_111_111_111_111, cif6i=10-e1d1c1b1a116, cif6i=11-0.
(4) during execution above-mentioned (2) (3), it is possible to use in addition 4 do not have the configuration module using to pass through to be similar to
Method configures the other parts of reconfigurable hardware.This step only configures rcb20, and the configuration data of address 0,1 is respectively 5016,
5116: cif5i=01-01101011, cif5i=10-5016, cif5i=11-0, cif5i=01-111, cif5i=10-5116,
cif5i=11-0.
(5) using the cif5 of cb20, rcb11 is moved to rcb12, rcb20 copies to rcb11.Due to management rcb11's
Cb11 is taken by the collocation channel of cb00, needs to delete this passage: cif6i=01-0, cif6i=11-0.Delete in (4) simultaneously
The passage set up: cif5i=01-0, cif5i=11-0.The cif5 of cb20 sets up the collocation channel of cb20, cb21, cb11, cb12,
And cb21 is set for dr bypass mode, cb20, cb11, cb12 are the data pattern reading address 0: cif5i=01-01100_
01111_01100_01110_001_001_010_001.Cb20, cb11 read register 0 data: cif5i=10-0, cif5i=11-
0.The data of reading is moved on to object module, cb20.dr will move to cb11.dr, cb11.dr and move to cb12.dr, then
Write: cif5i=01-011_011_010_001, cif5i=10-6616, cif5i=11-0.Execute operation similar to above, complete
The configuration data becoming depositor 1 replicates: cif5i=01-101_101_010_101, cif5i=10-0, cif5i=11-0, cif5i=
01-111_111_010_001, cif5i=01-8616, cif5i=11-0.Arrive this, successfully rcb11 is moved to rcb12, rcb20
Copy to rcb11.Now, the value of the component register in configuration module and reconfigurable circuit such as below table.
In xilinx ise software, realize above-mentioned design using verilog and emulated with ise.Simulation result with
Form is identical, shows that configuration information accurately can be write reconfigurable circuit by this configuration circuit, can be convenient, flexible
Complete the operation such as loading, duplication of configuration information.
The invention is not limited in any way for above-described embodiment, the technical side that all modes taking equivalent are obtained
Case, all falls within protection scope of the present invention.
Claims (3)
1. the modularity self-organizing configuration circuit of a kind of reconfigurable hardware circuit, is characterized in that by several and reconfigurable circuit mould
The configuration module that block connects one to one is passed through communication interface and is formed according to topological structure, and described topological structure is von Neumann
Structure, comprising one or more can be with the input communication interface of concurrent working, described configuration module, its input port and output
Port comprises 1 global synchronization input end of clock mouth, 1 global synchronization the RESET input mouth, several communication interfaces and 1 and joins
Put interface, several configuration modules described are connected with each other network consisting by communication interface；Its internal 1 input buffering of inclusion
Device, 11 bit pattern depositor, 13 input interface mask registers, 14 output interface mask registers, 1 instruction
Depositor, 1 data register, a unique physical address of whole network and some combinational logic circuits, described each communication connects
Mouthful, comprise 2 bit pattern inputs, 1 data input, 2 bit pattern outputs and 1 data output, described configuration interface, including read-write
Address and control signal wire and interruption application signal that the data wire of configuration information, read-write configuration information use, described input is delayed
Rush device, comprise 2 input instruction buffers, 1 Input Data Buffer, 2 reverse input instruction buffers and 1 reversely defeated
Enter data buffer, described input interface mask register, is some bit widths, described output interface mask register, if for
Dry bit width, described command register is at least 2 bit widths, and described data register is at least 4 bit widths, institute in configuration module
Depositor and the data loading of buffer is had all to carry out on global synchronization input end of clock mouth rising edge edge.
2. the modularity self-organizing configuration circuit of reconfigurable hardware circuit according to claim 1, is characterized in that described group
Combinational logic circuit includes 5 application of logic circuit module, 4 MUX and 2 groups of decoders.
3. the modularity self-organizing configuration circuit of reconfigurable hardware circuit according to claim 2, it is characterized in that described in join
Put in module, all pattern inputs are connected to input instruction buffer by the first MUX, by the second multi-path choice
Device is connected to reverse input instruction buffer；All data inputs are connected to input data buffering by the 3rd MUX
Device, is connected to reverse Input Data Buffer by the 4th MUX；Described first MUX and the choosing of the 3rd multichannel
Select device to be controlled by input interface mask register, the 4th MUX and the second MUX are selected to deposit by output interface
Device controls；The input of mode register is input instruction buffer；The input of input interface mask register is the second logic electricity
Road module；The input of output interface mask register and command register is Input Data Buffer, by the 3rd logic circuit
Module controls；The input of data register be Input Data Buffer, output interface mask register, physical address, interrupt Shen
Please signal or read-write configuration information data wire, controlled by the first application of logic circuit module；The input of the second application of logic circuit module
For the input of the 3rd application of logic circuit module, input interface mask register and all patterns；The input of the 3rd application of logic circuit module is
Reversely input instruction buffer and mode register；The input of the 4th application of logic circuit module is the 3rd application of logic circuit module, output
Interface mask register and input interface mask register；The input of the first application of logic circuit module be the 3rd application of logic circuit module and
Command register；The input of the 5th application of logic circuit module is reverse input instruction buffer and interrupts application signal；All patterns
Output is all obtained by the first decoder, and signal is originated as input instruction buffer, the 5th application of logic circuit module or 0, by the
Four application of logic circuit module control；All data outputs are all obtained by the second decoder, and signal is originated and delayed for reverse input data
Rush device, command register, data register or Input Data Buffer, controlled by the 4th application of logic circuit module；Control signal
The signal of line is originated as command register and the first application of logic circuit module；The data wire of read-write configuration information is directly to connect during output
It is connected to data register.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102361451A (en) * | 2011-09-06 | 2012-02-22 | 北京时代民芯科技有限公司 | FPGA (Field Programmable Gate Array) configuration circuit structure |
| CN102546317A (en) * | 2010-12-22 | 2012-07-04 | 华东计算技术研究所 | Method capable of reconstructing interconnection network based on FPGA (Field Programmable Gate Array) technology |
| CN102662805A (en) * | 2012-03-27 | 2012-09-12 | 中国人民解放军国防科学技术大学 | Structure and method of bus-structure-based embryonic biomimetic self-healing |
| KR20130118708A (en) * | 2012-04-20 | 2013-10-30 | 조선대학교산학협력단 | Self-repairing bio-inspired fault-tolerant fpga |
-
2014
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102546317A (en) * | 2010-12-22 | 2012-07-04 | 华东计算技术研究所 | Method capable of reconstructing interconnection network based on FPGA (Field Programmable Gate Array) technology |
| CN102361451A (en) * | 2011-09-06 | 2012-02-22 | 北京时代民芯科技有限公司 | FPGA (Field Programmable Gate Array) configuration circuit structure |
| CN102662805A (en) * | 2012-03-27 | 2012-09-12 | 中国人民解放军国防科学技术大学 | Structure and method of bus-structure-based embryonic biomimetic self-healing |
| KR20130118708A (en) * | 2012-04-20 | 2013-10-30 | 조선대학교산학협력단 | Self-repairing bio-inspired fault-tolerant fpga |
Non-Patent Citations (1)
| Title |
|---|
| 基于原核仿生阵列的自修复技术研究;王南天;《中国优秀硕士学位论文全文数据库》;20121231;9-50 * |
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