CN104009738A - Early termination comparator realized on the basis of static logic and control method thereof - Google Patents
Early termination comparator realized on the basis of static logic and control method thereof Download PDFInfo
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- CN104009738A CN104009738A CN201410201528.5A CN201410201528A CN104009738A CN 104009738 A CN104009738 A CN 104009738A CN 201410201528 A CN201410201528 A CN 201410201528A CN 104009738 A CN104009738 A CN 104009738A
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Abstract
The invention discloses an early termination comparator realized on the basis of the static logic. The early termination comparator comprises two static comparing units and a termination judging unit, and the static comparing units are cascaded and then connected with the termination judging unit. The invention further discloses a control method of the early termination comparator realized on the basis of the static logic. The method comprises the following steps that firstly, two pieces of data are input into a first input signal and a second input signal; secondly, an enable signal at the input end is connected with the level of a logic 1; thirdly, if a completion signal at the output end is the logic 1, a greater or equal output signal and a smaller output signal are observed, if the greater or equal output signal is the logic 1, the comparative result shows that the first input signal is greater than or equal to the second input signal, and if the smaller output signal is the logic 1, the comparative result shows that the first input signal is smaller than the second input signal; fourthly, the enable signal at the input end is connected with the level of a logic 0. The early termination comparator and the control method have the advantages that a circuit is symmetric in the vertical direction, and power consumption is reduced.
Description
Technical field
The present invention relates to electronic technology field, particularly a kind of premature termination comparator and control method thereof realizing based on static logic.
Background technology
Nowadays deep submicron process technology has been arrived in VLSI (very large scale integrated circuit) designs development, and characteristic size is constantly dwindled integrated level is constantly increased, and power consumption also increases thereupon.The power consumption of circuit discharges by being converted into heat, and too much heat raises the working temperature that causes device, then seriously reduces the reliability of system, makes circuit malfunction.And the chip high to working temperature can only ensure circuit performance with more expensive encapsulating material.So power consumption becomes the significant consideration of designing integrated circuit.In order to improve the reliability of chip and to reduce chip package cost, carry out design circuit in the urgent need to designer by the technology of low-power consumption.Therefore low power dissipation design becomes an important directions of integrated circuit (IC) design, through from system, logical design to physical Design and the whole design flow of integrated circuit realized of technique.On the other hand, the low power dissipation design of basic processing unit is the important content of low power dissipation design.Comparator is the important basic processing unit of digital system, and the power dissipation ratio that traditional comparator consumes is larger.The low power dissipation design of comparator is significant for the power consumption that reduces system.Tradition comparator great majority are parallel computations, as long as there is input, all data all can walk abreast and carry out computing, finally obtain comparative result.That is to say, each data of input all can be carried out computing.But according to the knowledge of probability theory, two random numbers compare, front 3 probability that just can compare result reach 87.5%.Along with the increase of bit wide, the computing that traditional comparator has increasing numerical digit there is no need, has therefore consumed very large power consumption.As can be seen here, prior art exists following shortcoming with not enough:
1, existing sync comparator is parallel comparator, need to compare each of data.For the larger data of data bit width comparatively speaking, sync comparator will operate all positions, and circuit is overturn frequently, has increased extra power consumption.
2, sync comparator generally forms by the cascade of multiple a few-bit comparator, and circuit unit is more, and circuit area is huge.
3, general asynchronous comparator is serial comparator, energy big-endian comparing data, the control signal using result relatively as next stage comparison.Although this comparator can reduce number of comparisons, final comparative result will could be exported through the transmission of all positions, and for the larger data comparison of data bit width, it has very large time delay and not low power consumption.
For these problems, in the urgent need to designing a kind of comparator of low-power consumption, fundamentally reduce the number of times of comparison operation, thereby reduce power consumption.
Summary of the invention
Primary and foremost purpose of the present invention is to overcome the shortcoming and deficiency that prior art exists, and proposes a kind of premature termination comparator of realizing based on static logic, and this comparator has reduced unnecessary computing, has reduced power consumption.
Another object of the present invention is to overcome shortcoming that prior art exists with not enough, propose the control method of the premature termination comparator that a kind of control realizes based on static logic, this control method can just draw comparative result at three, has greatly saved the relatively time.
Primary and foremost purpose of the present invention is achieved through the following technical solutions: a kind of premature termination comparator of realizing based on static logic, comprise that at least two two static comparisons are connected with termination judging unit after unit cascaded again, form multidigit comparator, after described two static comparisons are unit cascaded, each two static comparison unit be less than signal output part, be greater than signal output part respectively with stop judging unit be less than signal input part, being greater than signal input part connects, the equal signal output of two static comparison unit of high bit is connected with time equal signal input of two static comparison unit of a high position, the equal signal output of two static comparison unit of lowest order is connected with the equal signal input that stops judging unit, described termination judging unit is output as the output signal that is more than or equal to of the described premature termination comparator of realizing based on static logic, settling signal and be less than output signal, the data input pin of described two static comparison unit is used for inputting data-signal to be compared, the enable signal input of described each two static comparison unit is connected with the enable signal input that stops judging unit.
Described two static comparison unit comprise and are greater than comparison circuit, are less than comparison circuit and comparison of equalization circuit;
The described comparison circuit that is greater than comprises a PMOS pipe P
1, the 2nd PMOS pipe P
2, the 3rd PMOS pipe P
3, the 4th PMOS pipe P
4, the 5th PMOS pipe P
5, the 6th PMOS pipe P
6, the 7th PMOS pipe P
7, the 8th PMOS pipe P
8, the 9th PMOS pipe P
9, a NMOS pipe N
1, the 2nd NMOS pipe N
2, the 3rd NMOS pipe N
3, the 4th NMOS pipe N
4, the 5th NMOS pipe N
5, the 6th NMOS pipe N
6, the 7th NMOS pipe N
7, the 8th NMOS pipe N
8, the 9th NMOS pipe N
9, the first inverter 1; Described P represents PMOS pipe, and N represents NMOS pipe; A described PMOS pipe P
1source electrode, the 3rd PMOS pipe P
3source electrode, the 4th PMOS pipe P
4source electrode, the 6th PMOS pipe P
6source electrode, the 8th PMOS pipe P
8source electrode and the 9th PMOS pipe P
9source electrode all connect power supply, the 9th NMOS pipe N
9source ground;
The one PMOS pipe P
1drain electrode and the 2nd PMOS pipe P
2source electrode join, the 2nd PMOS pipe P
2drain electrode and NMOS pipe N
1, the 2nd NMOS pipe N
2drain electrode join;
The 3rd PMOS pipe P
3, the 4th PMOS pipe P
4drain electrode and the 5th PMOS pipe P
5source electrode join, the 5th PMOS pipe P
5drain electrode and the 5th NMOS pipe N
5drain electrode join, the 5th NMOS pipe N
5source electrode and the 3rd NMOS pipe N
3, the 4th NMOS pipe N
4drain electrode join;
The 6th PMOS pipe P
6drain electrode and the 7th PMOS pipe P
7source electrode join, the 7th PMOS pipe P
7drain electrode and the 6th NMOS pipe N
6drain electrode join, the 6th NMOS pipe N
6source electrode and the 7th NMOS pipe N
7drain electrode join;
The 8th PMOS pipe P
8, the 9th PMOS pipe P
9drain electrode and the input of the first inverter 1 join.
The 2nd PMOS pipe P
2drain electrode and the 5th PMOS pipe P
5, the 5th NMOS pipe N
5grid join, the 5th PMOS pipe P
5drain electrode and the 7th PMOS pipe P
7drain electrode join, the 7th PMOS pipe P
7drain electrode and the input of the first inverter 1 join;
The one NMOS pipe N
1, the 2nd NMOS pipe N
2, the 3rd NMOS pipe N
3, the 4th NMOS pipe N
4, the 7th NMOS pipe N
7source electrode all with the 8th NMOS pipe N
8drain electrode join, the 8th NMOS pipe N
8source electrode and the 9th NMOS pipe N
9drain electrode join;
The one PMOS pipe P
1with a NMOS pipe N
1grid all connect the non-signal of the first data low level
the 2nd PMOS pipe P
2with the 2nd NMOS pipe N
2grid all connect the second data low level signal B
0; The 3rd PMOS pipe P
3with the 3rd NMOS pipe N
3grid all connect the first data high signal A
1; The 4th PMOS pipe P
4grid and the 4th NMOS pipe N
4grid all connect the high-order non-signal of the second data
the 6th PMOS pipe P
6with the 6th NMOS pipe N
6grid all connect the first data high signal A
1; The 7th PMOS pipe P
7with the 7th NMOS pipe N
7grid all connect the high-order non-signal of the second data
the 8th PMOS pipe P
8with the 8th NMOS pipe N
8grid all connect the input EQin of equal signal; The 9th PMOS pipe P
9with the 9th NMOS pipe N
9grid all connect enable signal EN; The output of the first inverter 1 is as the output that is greater than signal GTout;
The described comparison circuit that is less than comprises the tenth PMOS pipe P
10, the 11 PMOS pipe P
11, the 12 PMOS pipe P
12, the 13 PMOS pipe P
13, the 14 PMOS pipe P
14, the 15 PMOS pipe P
15, the 16 PMOS pipe P
16, the 17 PMOS pipe P
17, the 18 PMOS pipe P
18, the tenth NMOS pipe N
10, the 11 NMOS pipe N
11, the 12 NMOS pipe N
12, the 13 NMOS pipe N
13, the 14 NMOS pipe N
14, the 15 NMOS pipe N
15, the 16 NMOS pipe N
16, the 17 NMOS pipe N
17, the 18 NMOS pipe N
18with the second inverter 2; Described P represents PMOS pipe, and N represents NMOS pipe.Described the tenth PMOS pipe P
10source electrode, the 12 PMOS pipe P
12source electrode, the 13 PMOS pipe P
13source electrode, the 15 PMOS pipe P
15source electrode, the 17 PMOS pipe P
17source electrode, the 18 PMOS pipe P
18source electrode all connect power supply, the 18 NMOS pipe N
18source ground;
The tenth PMOS pipe P
10drain electrode and the 11 PMOS pipe P
11source electrode join, the tenth NMOS pipe N
10drain electrode and the 11 NMOS pipe N
11drain electrode all with the 11 PMOS pipe P
11drain electrode join;
The 12 PMOS pipe P
12drain electrode and the 13 PMOS pipe P
13drain electrode all with the 14 PMOS pipe P
14source electrode join, the 14 PMOS pipe P
14drain electrode and the 14 NMOS pipe N
14drain electrode join, the 12 NMOS pipe N
12drain electrode and the 13 NMOS pipe N
13drain electrode all with the 14 NMOS pipe N
14source electrode join;
The 15 PMOS pipe P
15drain electrode and the 16 PMOS pipe P
16source electrode join, the 16 PMOS pipe P
16drain electrode and the 15 NMOS pipe N
15drain electrode join, the 15 NMOS pipe N
15source electrode and the 16 NMOS pipe N
16drain electrode join;
The 17 NMOS pipe N
17drain electrode and the 18 NMOS pipe N
18drain electrode all join with the input of the second inverter 2;
The 14 PMOS pipe P
14grid and the 14 NMOS pipe N
14grid all with the 11 PMOS pipe P
11drain electrode join, the 14 PMOS pipe P
14drain electrode and the 16 PMOS pipe P
16drain electrode join, the 16 PMOS pipe P
16drain electrode and the input of the second inverter 2 join;
The tenth NMOS pipe N
10source electrode, the 11 NMOS pipe N
11source electrode, the 12 NMOS pipe N
12source electrode, the 13 NMOS pipe N
13source electrode, the 16 NMOS pipe N
16source electrode all with the 17 NMOS pipe N
17drain electrode join, the 17 NMOS pipe N
17source electrode and the 18 NMOS pipe N
18drain electrode join;
The tenth PMOS pipe P
10grid and the tenth NMOS pipe N
10grid all connect the first data low level signal A
0; The 11 PMOS pipe P
11, the 11 NMOS pipe N
11grid connect the non-signal of the second data low level
the 12 PMOS pipe P
12grid and the 12 NMOS pipe N
12grid all connect the high-order non-signal of the first data
the 13 PMOS pipe P
13grid and the 13 NMOS pipe N
13grid all connect the second data high signal B
1; The 15 PMOS pipe P
15grid and the 15 NMOS pipe N
15grid all connect the high-order non-signal of the first data
the 16 PMOS pipe P
16grid and the 16 NMOS pipe N
16grid all connect the second data high signal B
1; The 17 PMOS pipe P
17grid and the 17 NMOS pipe N
17grid all connect the input EQin of equal signal; The 18 PMOS pipe P
18grid and the 18 NMOS pipe N
18grid all connect enable signal EN; The output of the second inverter 2 is as the output that is less than signal LTout;
Described comparison of equalization circuit comprises the 19 PMOS pipe P
19, the 20 PMOS pipe P
20, the 21 PMOS pipe P
21, the 22 PMOS pipe P
22, the 23 PMOS pipe P
23, the 24 PMOS pipe P
24, the 25 PMOS pipe P
25, the 26 PMOS pipe P
26, the 27 PMOS pipe P
27, the 28 PMOS pipe P
28, the 19 NMOS pipe N
19, the 20 NMOS pipe N
20, the 21 NMOS pipe N
21, the 22 NMOS pipe N
22, the 23 NMOS pipe N
23, the 24 NMOS pipe N
24, the 25 NMOS pipe N
25, the 26 NMOS pipe N
26, the 27 NMOS pipe N
27, the 28 NMOS pipe N
28with the 3rd inverter 3; Described the 19 PMOS pipe P
19source electrode, the 21 PMOS pipe P
21source electrode, the 23 PMOS pipe P
23source electrode, the 25 PMOS pipe P
25source electrode, the 27 PMOS pipe P
27source electrode, the 28 PMOS pipe P
28source electrode all connect power supply, the 28 NMOS pipe N
28source ground;
The 19 PMOS pipe P
19drain electrode and the 20 PMOS pipe P
20source electrode join, the 21 PMOS pipe P
21drain electrode and the 22 PMOS pipe P
22source electrode join, the 19 PMOS pipe P
19drain electrode and the 21 PMOS pipe P
21drain electrode join; The 23 PMOS pipe P
23drain electrode and the 24 PMOS pipe P
24source electrode join, the 25 PMOS pipe P
25drain electrode and the 26 PMOS pipe P
26source electrode join, the 23 PMOS pipe P
23drain electrode and the 25 PMOS pipe P
25drain electrode join;
The 20 PMOS pipe P
20drain electrode, the 22 PMOS pipe P
22drain electrode, the 24 PMOS pipe P
24drain electrode, the 26 PMOS pipe P
26drain electrode, the 27 PMOS pipe P
27drain electrode and the 28 PMOS pipe P
28drain electrode all join with the input of the 3rd inverter 3;
The 20 PMOS pipe P
20drain electrode and the 19 NMOS pipe N
19drain electrode join, the 19 NMOS pipe N
19source electrode and the 21 NMOS pipe N
21drain electrode join, the 21 NMOS pipe N
21source electrode and the 23 NMOS pipe N
23drain electrode join, the 23 NMOS pipe N
23source electrode and the 25 NMOS pipe N
25drain electrode join; The 26 PMOS pipe P
26drain electrode and the 20 NMOS pipe N
20drain electrode join, the 20 NMOS pipe N
20source electrode and the 22 NMOS pipe N
22drain electrode join, the 22 NMOS pipe N
22source electrode and the 24 NMOS pipe N
24drain electrode join, the 24 NMOS pipe N
24source electrode and the 26 NMOS pipe N
26drain electrode join; The 21 NMOS pipe N
21drain electrode and the 22 NMOS pipe N
22drain electrode join, the 25 NMOS pipe N
25source electrode and the 26 NMOS pipe N
26source electrode all with the 27 NMOS pipe N
27drain electrode join, the 27 NMOS pipe N
27source electrode and the 28 NMOS pipe N
28drain electrode join;
The 19 PMOS pipe P
19grid and the 19 NMOS pipe N
19grid all connect the first data low level signal A
0; The 20 PMOS pipe P
20grid and the 20 NMOS pipe N
20grid all connect the non-signal of the first data low level
the 21 PMOS pipe P
21grid and the 21 NMOS pipe N
21grid all connect the second data low level signal B
0; The 22 PMOS pipe P
22grid and the 22 NMOS pipe N
22grid all connect the non-signal of the second data low level
the 23 PMOS pipe P
23grid and the 23 NMOS pipe N
23grid all connect the first data high signal A
1; The 24 PMOS pipe P
24grid and the 24 NMOS pipe N
24grid all connect the high-order non-signal of the first data
the 25 PMOS pipe P
25grid and the 25 NMOS pipe N
25grid all connect the second data high signal B
1; The 26 PMOS pipe P
26grid and the 26 NMOS pipe N
26grid all connect the high-order non-signal of the second data
the 27 PMOS pipe P
27grid and the 27 NMOS pipe N
27grid all connect the input EQin of equal signal; The 28 PMOS pipe P
28grid and the 28 NMOS pipe N
28grid all connect enable signal EN; The output of the 3rd inverter 3 is as the output of equal signal EQout.
Described termination judging unit comprises and is more than or equal to signal judging circuit, is less than signal judging circuit and logic sum gate OR1;
Be more than or equal to signal judging circuit and comprise that equaling signal PMOS manages PE
q, the 0th be greater than signal PMOS pipe P
gT0, the 1st be greater than signal PMOS pipe P
gT1, N-1 is greater than signal PMOS pipe P
gTn-1, the first enable signal PMOS pipe P
eN1, equal signal NMOS pipe N
eQ, the 0th be greater than signal NMOS pipe N
gT0, the 1st be greater than signal NMOS pipe N
gT1, N-1 is greater than signal NMOS pipe N
gTn-1, the first enable signal NMOS pipe N
eN1with the 4th inverter 4;
The described signal PMOS pipe P that equals
eQ, the 0th be greater than signal PMOS pipe P
gT0, the 1st be greater than signal PMOS pipe P
gT1be greater than signal PMOS pipe P with N-1
gTn-1series connection;
Described N-1 is greater than signal PMOS pipe P
gTn-1source electrode and the first enable signal PMOS pipe P
eN1source electrode connect, equal signal PMOS pipe P
eQdrain electrode and the first enable signal PMOS pipe P
eN1drain electrode connect, the first enable signal PMOS pipe P
eN1source electrode connect power supply;
The described signal NMOS pipe N that equals
eQ, the 0th be greater than signal NMOS pipe N
gT0, the 1st be greater than signal NMOS pipe N
gT1be greater than signal NMOS pipe N with N-1
gTn-1in parallel;
The described signal NMOS pipe N that equals
eQsource electrode, the 0th be greater than signal NMOS pipe N
gT0source electrode, the 1st be greater than signal NMOS pipe N
gT1source electrode, N-1 be greater than signal NMOS pipe N
gTn-1source electrode all with the first enable signal NMOS pipe N
eN1drain electrode connect, the first enable signal NMOS pipe N
eN1source ground;
The described signal NMOS pipe N that equals
eQdrain electrode be connected with the input of the 4th inverter 4;
The described signal PMOS pipe P that equals
eQgrid and equal signal NMOS pipe N
eQgrid all connect equate input signal EQ; The 0th is greater than signal PMOS pipe P
gT0grid and the 0th be greater than signal NMOS pipe N
gT0grid all connect the 0th and be greater than signal GT[0]; The 1st is greater than signal PMOS pipe P
gT1grid and the 1st be greater than signal NMOS pipe N
gT1grid all connect the 1st and be greater than signal GT[1]; N-1 is greater than signal PMOS pipe P
gTn-1grid and N-1 be greater than signal NMOS pipe N
gTn-1grid all connect N-1 and be greater than signal GT[N-1]; The first enable signal PMOS pipe P
eN1grid and the first enable signal NMOS pipe N
eN1grid all connect enable signal EN; The 4th inverter 4 is output as and is more than or equal to signal GT or EQ;
The described signal judging circuit that is less than comprises that the 0th is less than signal PMOS pipe P
lT0, the 1st be less than signal PMOS pipe P
lT1, N-1 is less than signal PMOS pipe P
lTn-1, the second enable signal PMOS pipe P
eN2, the 0th be less than signal NMOS pipe N
lT0, the 1st be less than signal NMOS pipe N
lT1, N-1 is less than signal NMOS pipe N
lTn-1, the second enable signal NMOS pipe N
eN2with the 5th inverter 5;
The described the 0th is less than signal PMOS pipe P
lT0, the 1st be less than signal PMOS pipe P
lT1be less than signal PMOS pipe P with N-1
lTn-1series connection.
Described N-1 is less than signal PMOS pipe P
lTn-1source electrode and the second enable signal PMOS pipe P
eN2source electrode connect, the 0th is less than signal PMOS pipe P
lT0drain electrode and the second enable signal PMOS pipe P
eN2drain electrode connect, the second enable signal PMOS pipe P
eN2source electrode connect power supply;
The described the 0th is less than signal NMOS pipe N
lT0, the 1st be less than signal NMOS pipe N
lT1be less than signal NMOS pipe N with N-1
lTn-1in parallel.
The described the 0th is less than signal NMOS pipe N
lT0source electrode, the 1st be less than signal NMOS pipe N
lT1source electrode, N-1 be less than signal NMOS pipe N
lTn-1source electrode and the second enable signal NMOS pipe N
eN2source electrode all with the second enable signal NMOS pipe N
eN2drain electrode connect, the second enable signal NMOS pipe N
eN2source ground;
The described the 0th is less than signal NMOS pipe N
lT0drain electrode be connected with the input of the 5th inverter 5;
The described the 0th is less than signal PMOS pipe P
lT0grid and the 0th be less than signal NMOS pipe N
lT0grid all connect the 0th and be less than signal LT[0]; The 1st is less than signal PMOS pipe P
lT1grid and the 1st be less than signal NMOS pipe N
lT1grid all connect the 1st and be less than signal LT[1]; N-1 is less than signal PMOS pipe P
lTn-1grid and N-1 be less than signal NMOS pipe N
lTn-1grid all connect N-1 and be less than signal LT[N-1]; The second enable signal PMOS pipe P
eN2grid and the second enable signal NMOS pipe N
eN2grid all connect enable signal EN; The 5th inverter 5 is output as and is less than signal LT;
The output that the output of described the 4th inverter 4 is more than or equal to signal GT or EQ, the 5th inverter 5 is less than signal LT and is connected with the input of logic sum gate OR1, and the output of logic sum gate OR1 is settling signal DONE.
Another object of the present invention is achieved through the following technical solutions: a kind of control method of the premature termination comparator of realizing based on static logic, comprises the following steps:
Step 1: the data of two same bit-width that will compare are inputted respectively the first input signal Data1 and the second input signal Data2;
Step 2: the enable signal En of input is connected to logical one level, start comparator work;
Step 3: wait for the settling signal DONE of output, if logical one, observation is more than or equal to output signal GT or EQ, is less than output signal LT; If being more than or equal to output signal GT or EQ is logical one, comparative result is that the first input signal is more than or equal to the second input signal; Be logical one if be less than output signal LT, comparative result is that the first input signal is less than the second input signal;
Step 4: after completing relatively, the enable signal En of input is connected to logical zero level, comparator is resetted, to work next time.
The present invention has following advantage and effect with respect to prior art:
1, the present invention is based on knowwhy and the experimental result of probability theory, design can premature termination the comparator of comparison, for most data, can just draw comparative result at three, greatly saved the relatively time.
2, the comparing unit of the present invention design and stop judging unit, can just judge size of data not identical first of data, and stop follow-up judgement, has reduced unnecessary computing, and then has reduced power consumption.
3, the present invention selects two static comparison unit as basic comparing unit, and because its circuit is simple, transistor used is few, so have less power consumption and suitable area.And two basic comparing units just can complete the comparison of most data, thus this static comparison unit balance circuit performance, area and power consumption.
4, comparing unit of the present invention has used CMOS static logic design, and circuit has symmetry, and quiescent dissipation is extremely low, is almost 0, thereby total power consumption further reduces, and is suitable for very much in large scale integrated circuit.
Brief description of the drawings
Fig. 1 is a kind of schematic diagram of the premature termination comparator of realizing based on static logic.
Fig. 2 is a kind of structure chart of the premature termination comparator of realizing based on static logic.
Fig. 3 (a) is the structure chart that is greater than comparison circuit.
Fig. 3 (b) is the structure chart that is less than comparison circuit.
Fig. 3 (c) is the structure chart of comparison of equalization circuit.
Fig. 4 is the structure chart that stops judging unit in Fig. 2.
Fig. 5 is the function realization flow figure of the premature termination comparator based on static logic realization.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the present invention is described in further detail, but embodiments of the present invention are not limited to this.
Embodiment
As shown in Figure 1, be a kind of schematic diagram of the premature termination comparator of realizing based on static logic, input signal is enable signal En, the first input signal Data1, the second input signal Data2.Wherein enable signal En is the signal of control circuit work, and the first input signal Data1 and the second input signal Data2 are the data-signals that need to compare computing.Described output signal is settling signal DONE, is more than or equal to output signal GT or EQ and is less than output signal LT.Wherein settling signal DONE represents that comparison operation completes, and comparator is no longer worked.Be more than or equal to output signal GT or EQ and represent that the first input signal is more than or equal to the second input signal.Be less than output signal LT and represent that the first input signal is less than the second input signal.
As shown in Figure 2, be a kind of structure chart of the premature termination comparator of realizing based on static logic, this comparator comprises at least one two static comparison unit and a termination judging unit.After plural two static comparisons are unit cascaded, form multidigit comparator with termination judging unit, after described two static comparisons are unit cascaded, each two static comparison unit be less than signal output part, be greater than signal output part and the signal input part that is less than that stops judging unit, being greater than signal input part connects, the equal signal output of two static comparison unit of high bit is connected with time equal signal input of two static comparison unit of a high position, the equal signal output of two static comparison unit of lowest order is connected with the equal signal input that stops judging unit, described termination judging unit is output as the output signal that is more than or equal to of the described premature termination comparator of realizing based on static logic, settling signal, be less than output signal, data-signal to be compared is input to the data input pin of each two static comparison unit, the enable signal input of described each two static comparison unit is connected with the enable signal input that stops judging unit.
Two static comparison unit in Fig. 2 comprise and are greater than comparison circuit, are less than comparison circuit and three electronic circuits of comparison of equalization circuit.
As shown in Fig. 3 (a), for being greater than comparison circuit.The described comparison circuit that is greater than comprises a PMOS pipe P
1, the 2nd PMOS pipe P
2, the 3rd PMOS pipe P
3, the 4th PMOS pipe P
4, the 5th PMOS pipe P
5, the 6th PMOS pipe P
6, the 7th PMOS pipe P
7, the 8th PMOS pipe P
8, the 9th PMOS pipe P
9, a NMOS pipe N
1, the 2nd NMOS pipe N
2, the 3rd NMOS pipe N
3, the 4th NMOS pipe N
4, the 5th NMOS pipe N
5, the 6th NMOS pipe N
6, the 7th NMOS pipe N
7, the 8th NMOS pipe N
8, the 9th NMOS pipe N
9, the first inverter 1.Described P represents PMOS pipe, and N represents NMOS pipe.A wherein PMOS pipe P
1, the 3rd PMOS pipe P
3, the 4th PMOS pipe P
4, the 6th PMOS pipe P
6, the 8th PMOS pipe P
8, the 9th PMOS pipe P
9source electrode connect power supply, the 9th NMOS pipe N
9source ground.
The one PMOS pipe P
1drain electrode and the 2nd PMOS pipe P
2source electrode join, the 2nd PMOS pipe P
2drain electrode and NMOS pipe N
1, the 2nd NMOS pipe N
2drain electrode join.
The 3rd PMOS pipe P
3, the 4th PMOS pipe P
4drain electrode and the 5th PMOS pipe P
5source electrode join, the 5th PMOS pipe P
5drain electrode and the 5th NMOS pipe N
5drain electrode join, the 5th NMOS pipe N
5source electrode and the 3rd NMOS pipe N
3, the 4th NMOS pipe N
4drain electrode join.
The 6th PMOS pipe P
6drain electrode and the 7th PMOS pipe P
7source electrode join, the 7th PMOS pipe P
7drain electrode and the 6th NMOS pipe N
6drain electrode join, the 6th NMOS pipe N
6source electrode and the 7th NMOS pipe N
7drain electrode join.
The 8th PMOS pipe P
8, the 9th PMOS pipe P
9drain electrode and the input of the first inverter 1 join.
The 2nd PMOS pipe P
2drain electrode and the 5th PMOS pipe P
5, the 5th NMOS pipe N
5grid join, the 5th PMOS pipe P
5drain electrode and the 7th PMOS pipe P
7drain electrode join, the 7th PMOS pipe P
7drain electrode and the input of the first inverter 1 join.
The one NMOS pipe N
1, the 2nd NMOS pipe N
2, the 3rd NMOS pipe N
3, the 4th NMOS pipe N
4, the 7th NMOS pipe N
7source electrode and the 8th NMOS pipe N
8drain electrode join, the 8th NMOS pipe N
8source electrode and the 9th NMOS pipe N
9drain electrode join.
The one PMOS pipe P
1, a NMOS pipe N
1grid connect the non-signal of the first data low level
the 2nd PMOS pipe P
2, the 2nd NMOS pipe N
2grid meet the second data low level signal B
0; The 3rd PMOS pipe P
3, the 3rd NMOS pipe N
3grid meet the first data high signal A
1; The 4th PMOS pipe P
4, the 4th NMOS pipe N
4the high-order non-signal of grid the second data connect the high-order non-signal of the second data
the 6th PMOS pipe P
6, the 6th NMOS pipe N
6grid meet the first data high signal A
1; The 7th PMOS pipe P
7, the 7th NMOS pipe N7 grid connect the high-order non-signal of the second data
the 8th PMOS pipe P
8, the 8th NMOS pipe N
8grid meet the input EQin of equal signal; The 9th PMOS pipe P
9, the 9th NMOS pipe N
9grid meet enable signal EN; The output of the first inverter 1 is as the output that is greater than signal GTout.
As shown in Fig. 3 (b), for being less than comparison circuit.The described comparison circuit that is less than comprises the tenth PMOS pipe P
10, the 11 PMOS pipe P
11, the 12 PMOS pipe P
12, the 13 PMOS pipe P
13, the 14 PMOS pipe P
14, the 15 PMOS pipe P
15, the 16 PMOS pipe P
16, the 17 PMOS pipe P
17, the 18 PMOS pipe P
18, the tenth NMOS pipe N
10, the 11 NMOS pipe N
11, the 12 NMOS pipe N
12, the 13 NMOS pipe N
13, the 14 NMOS pipe N
14, the 15 NMOS pipe N
15, the 16 NMOS pipe N
16, the 17 NMOS pipe N
17, the 18 NMOS pipe N
18, the second inverter 2.Described P represents PMOS pipe, and N represents NMOS pipe.Wherein the tenth PMOS pipe P
10, the 12 PMOS pipe P
12, the 13 PMOS pipe P
13, the 15 PMOS pipe P
15, the 17 PMOS pipe P
17, the 18 PMOS pipe P
18source electrode connect power supply, the 18 NMOS pipe N
18source ground.
The tenth PMOS pipe P
10drain electrode and the 11 PMOS pipe P
11source electrode join, the 11 PMOS pipe P
11drain electrode and the tenth NMOS pipe N
10, the 11 NMOS pipe N
11drain electrode join.
The 12 PMOS pipe P
12, the 13 PMOS pipe P
13drain electrode and the 14 PMOS pipe P
14source electrode join, the 14 PMOS pipe P
14drain electrode and the 14 NMOS pipe N
14drain electrode join, the 14 NMOS pipe N
14source electrode and the 12 NMOS pipe N
12, the 13 NMOS pipe N
13drain electrode join.
The 15 PMOS pipe P
15drain electrode and the 16 PMOS pipe P
16source electrode join, the 16 PMOS pipe P
16drain electrode and the 15 NMOS pipe N
15drain electrode join, the 15 NMOS pipe N
15source electrode and the 16 NMOS pipe N
16drain electrode join.
The 17 NMOS pipe N
17, the 18 NMOS pipe N
18drain electrode and the input of the second inverter 2 join.
The 11 PMOS pipe P
11drain electrode and the 14 PMOS pipe P
14, the 14 NMOS pipe N
14grid join, the 14 PMOS pipe P
14drain electrode and the 16 PMOS pipe P
16drain electrode join, the 16 PMOS pipe P
16drain electrode and the input of the second inverter 2 join.
The tenth NMOS pipe N
10, the 11 NMOS pipe N
11, the 12 NMOS pipe N
12, the 13 NMOS pipe N
13, the 16 NMOS pipe N
16source electrode and the 17 NMOS pipe N
17drain electrode join, the 17 NMOS pipe N
17source electrode and the 18 NMOS pipe N
18drain electrode join.
The tenth PMOS pipe P
10, the tenth NMOS pipe N
10grid meet the first data low level signal A
0; The 11 PMOS pipe P
11, the 11 NMOS pipe N
11grid connect the high-order non-signal of the second data
the 12 PMOS pipe P
12, the 12 NMOS pipe N
12grid connect the high-order non-signal of the first data
the 13 PMOS pipe P
13, the 13 NMOS pipe N
13grid meet the second data high signal B
1; The 15 PMOS pipe P
15, the 15 NMOS pipe N
15grid connect the high-order non-signal of the first data
the 16 PMOS pipe P
16, the 16 NMOS pipe N
16grid meet the second data high signal B
1; The 17 PMOS pipe P
17, the 17 NMOS pipe N
17grid meet the input EQin of equal signal; The 18 PMOS pipe P
18, the 18 NMOS pipe N
18grid meet enable signal EN; The output of the second inverter 2 is as the output that is less than signal LTout.
As shown in Fig. 3 (c), it is comparison of equalization circuit.Described comparison of equalization circuit comprises the 19 PMOS pipe P
19, the 20 PMOS pipe P
20, the 21 PMOS pipe P
21, the 22 PMOS pipe P
22, the 23 PMOS pipe P
23, the 24 PMOS pipe P
24, the 25 PMOS pipe P
25, the 26 PMOS pipe P
26, the 27 PMOS pipe P
27, the 28 PMOS pipe P
28, the 19 NMOS pipe N
19, the 20 NMOS pipe N
20, the 21 NMOS pipe N
21, the 22 NMOS pipe N
22, the 23 NMOS pipe N
23, the 24 NMOS pipe N
24, the 25 NMOS pipe N
25, the 26 NMOS pipe N
26, the 27 NMOS pipe N
27, the 28 NMOS pipe N
28, the 3rd inverter 3.Described P represents PMOS pipe, and N represents NMOS pipe.Wherein the 19 PMOS pipe P
19, the 21 PMOS pipe P
21, the 23 PMOS pipe P
23, the 25 PMOS pipe P
25, the 27 PMOS pipe P
27, the 28 PMOS pipe P
28source electrode connect power supply, the 28 NMOS pipe N
28source ground.
The 19 PMOS pipe P
19drain electrode and the 20 PMOS pipe P
20source electrode join, the 21 PMOS pipe P
21drain electrode and the 22 PMOS pipe P
22source electrode join, the 19 PMOS pipe P
19drain electrode and the 21 PMOS pipe P
21drain electrode join; The 23 PMOS pipe P
23drain electrode and the 24 PMOS pipe P
24source electrode join, the 25 PMOS pipe P
25drain electrode and the 26 PMOS pipe P
26source electrode join, the 23 PMOS pipe P
23drain electrode and the 25 PMOS pipe P
25drain electrode join.
The 20 PMOS pipe P
20, the 22 PMOS pipe P
22, the 24 PMOS pipe P
24, the 26 PMOS pipe P
26, the 27 PMOS pipe P
27, the 28 PMOS pipe P
28drain electrode and the input of the 3rd inverter 3 join.
The 20 PMOS pipe P
20drain electrode and the 19 NMOS pipe N
19drain electrode join, the 19 NMOS pipe N
19source electrode and the 21 NMOS pipe N
21drain electrode join, the 21 NMOS pipe N
21source electrode and the 23 NMOS pipe N
23drain electrode join, the 23 NMOS pipe N
23source electrode and the 25 NMOS pipe N
25drain electrode join; The 26 PMOS pipe P
26drain electrode and the 20 NMOS pipe N
20drain electrode join, the 20 NMOS pipe N
20source electrode and the 22 NMOS pipe N
22drain electrode join, the 22 NMOS pipe N
22source electrode and the 24 NMOS pipe N
24drain electrode join, the 24 NMOS pipe N
24source electrode and the 26 NMOS pipe N
26drain electrode join; The 21 NMOS pipe N
21drain electrode and the 22 NMOS pipe N
22drain electrode join, the 25 NMOS pipe N
25, the 26 NMOS pipe N
26source electrode and the 27 NMOS pipe N
27drain electrode join, the 27 NMOS pipe N
27source electrode and the 28 NMOS pipe N
28drain electrode join.
The 19 PMOS pipe P
19, the 19 NMOS pipe N
19grid meet the first data low level signal A
0; The 20 PMOS pipe P
20, the 20 NMOS pipe N
20grid connect the non-signal of the first data low level
the 21 PMOS pipe P
21, the 21 NMOS pipe N
21grid meet the second data low level signal B
0; The 22 PMOS pipe P
22, the 22 NMOS pipe N
22grid connect the non-signal of the second data low level
the 23 PMOS pipe P
23, the 23 NMOS pipe N
23grid meet the first data high signal A
1; The 24 PMOS pipe P
24, the 24 NMOS pipe N
24grid connect the high-order non-signal of the first data
the 25 PMOS pipe P
25, the 25 NMOS pipe N
25grid meet the second data high signal B
1; The 26 PMOS pipe P
26, the 26 NMOS pipe N
26grid connect the high-order non-signal of the second data
the 27 PMOS pipe P
27, the 27 NMOS pipe N
27grid meet the input EQin of equal signal; The 28 PMOS pipe P
28, the 28 NMOS pipe N
28grid meet enable signal EN; The output of the 3rd inverter 3 is as the output of equal signal EQout.
As shown in Figure 4, for stopping the structure chart of judging unit.Described termination judging unit comprises and is more than or equal to signal judging circuit, is less than signal judging circuit and a logic sum gate OR1.
Be more than or equal to signal judging circuit and comprise that equaling signal PMOS manages P
eQ, the 0th be greater than signal PMOS pipe P
gT0, the 1st be greater than signal PMOS pipe P
gT1, the first enable signal PMOS pipe P
eN1, equal signal NMOS pipe N
eQ, the 0th be greater than signal NMOS pipe N
gT0, the 1st be greater than signal NMOS pipe N
gT1, the first enable signal NMOS pipe N
eN1with the 4th inverter 4.
Wherein, equal signal PMOS pipe P
eQ, the 0th be greater than signal PMOS pipe P
gT0, the 1st be greater than signal PMOS pipe P
gT1series connection.
The 1st is greater than signal PMOS pipe P
gT1source electrode and the first enable signal PMOS pipe P
eN1source electrode connect, equal signal PMOS pipe P
eQdrain electrode and the first enable signal PMOS pipe P
eN1 drain electrode connects, the first enable signal PMOS pipe P
eN1source electrode connect power supply.
Equal signal NMOS pipe N
eQ, the 0th be greater than signal NMOS pipe N
gT0, the 1st be greater than signal NMOS pipe N
gT1in parallel.
Equal signal NMOS pipe N
eQ, the 0th be greater than signal NMOS pipe N
gT0, the 1st be greater than signal NMOS pipe N
gT1source electrode and the first enable signal NMOS pipe N
eN1drain electrode connect, the first enable signal NMOS pipe N
eN1source ground.
Equal signal NMOS pipe N
eQdrain electrode be connected with the input of the 4th inverter 4.
Equal signal PMOS pipe P
eQwith equal signal NMOS pipe N
eQgrid connect equate input signal EQ; The 0th is greater than signal PMOS pipe P
gT0, the 0th be greater than signal NMOS pipe N
gT0grid connect the 0th and be greater than signal GT[0]; The 1st is greater than signal PMOS pipe P
gT1, the 1st be greater than signal NMOS pipe N
gT1grid connect the 1st and be greater than signal GT[1]; The first enable signal PMOS pipe P
eN1, the first enable signal NMOS pipe N
eN1grid meet enable signal EN; The 4th inverter 4 is output as and is more than or equal to signal GT orEQ.
Be less than signal judging circuit and comprise that the 0th is less than signal PMOS pipe P
lT0, the 1st be less than signal PMOS pipe P
lT1, the second enable signal PMOS pipe P
eN2, the 0th be less than signal NMOS pipe N
lT0, the 1st be less than signal NMOS pipe N
lT1, the second enable signal NMOS pipe N
eN2with the 5th inverter 5.
Wherein, the 0th is less than signal PMOS pipe P
lT0, the 1st be less than signal PMOS pipe P
lT1series connection.
The 1st is less than signal PMOS pipe P
lT1source electrode and the second enable signal PMOS pipe P
eN2source electrode connect, the 0th is less than signal PMOS pipe P
lT0drain electrode and the second enable signal PMOS pipe P
eN2drain electrode connect, the second enable signal PMOS pipe P
eN2source electrode connect power supply.
The 0th is less than signal NMOS pipe N
lT0, the 1st be less than signal NMOS pipe N
lT1in parallel.
The 0th is less than signal NMOS pipe N
lT0, the 1st be less than signal NMOS pipe N
lT1, the second enable signal NMOS pipe N
eN2source electrode and the second enable signal NMOS pipe N
eN2drain electrode connect, the second enable signal NMOS pipe N
eN2source ground.
The 0th is less than signal NMOS pipe N
lT0drain electrode be connected with the input of the 5th inverter 5.
The 0th is less than signal PMOS pipe P
lT0, the 0th be less than signal NMOS pipe N
lT0grid connect the 0th and be less than signal LT[0]; The 1st is less than signal PMOS pipe P
lT1, the 1st be less than signal NMOS pipe N
lT1grid connect the 1st and be less than signal LT[1]; The second enable signal PMOS pipe P
eN2, the second enable signal NMOS pipe N
eN2grid meet enable signal EN; The 5th inverter 5 is output as and is less than signal LT.
The output that the output of the 4th inverter 4 is more than or equal to signal GT or EQ, the 5th inverter 5 is less than signal LT and is connected with the input of logic sum gate OR1, and the output of logic sum gate OR1 is settling signal DONE.
In conjunction with Fig. 3, the function of two static comparison unit is achieved as follows: A
1a
0with B
1b
0for identical two of two data that will compare, be input to the data input pin of two static comparison unit.When enable signal EN or equal input signal EQin have one for low level, this not computing of circuit; In the time that enable signal EN or equal input signal EQin are high level, circuit carries out work.If A
1a
0be greater than B
1b
0, be greater than signal GTout and be output as high level, equate defeated signal EQout and be less than signal LT
outoutput is low level; If A
1a
0be less than B
1b
0, be less than signal LTout and be output as high level, be greater than signal GTout output and equal signal EQout and export and be low level; If A
1a
0equal B
1b
0, equal signal EQout is output as high level, is greater than the output of GTout signal and is less than signal LTout output to be low level.
As shown in Figure 5, taking 4 bit data, relatively as example, realization flow is as follows in detail for the function realization flow of the premature termination comparator of realizing based on static logic:
1, idle condition;
Without any input in the situation that, the premature termination comparator of realizing based on static logic is not worked, in idle condition.
2, input data;
Two four figures that will compare are according to being input to respectively first signal input Data1 and secondary signal input Data2.
3, send enable signal;
Input enable signal En is 1, controls whole circuit and starts working.
4, two static comparison cell operation;
First work in two high-order static comparison unit, the highest two of the data that compare are compared, and draws operation result.
If the equal output signal of this element is 0, represent data high two unequal, at this moment the value that is greater than output signal and is less than output signal of this element is delivered to termination judging unit.
If the equal output signal of this element is 1, represent that high two of data equate, at this moment the value that equals output signal of this element is delivered to two static comparison unit of low level.
What two static comparison unit of low level received that two high-order static comparison unit transmit equal output signal be 1 after, just start working, the value that is greater than output signal, is less than output signal and equals output signal of this element is passed to termination judging unit.
5, stop judging unit judgement;
Stopping judging unit is 1 o'clock at enable signal En, just starts working.When the output signal that receives two static comparison unit just judges.
In the time receiving being greater than output signal and being 1 of any one two static comparison unit, stop judging unit to be more than or equal to output signal GT or EQ be 1, being less than output signal LT is 0, represents that Data1 is more than or equal to Data2.
In the time receiving being less than output signal and being 1 of any one two static comparison unit, the output signal LT that is less than that stops judging unit is 1, and being more than or equal to output signal GT or EQ is 0, represents that Data1 is less than Data2.
In the time receiving the equaling output signal and be 1 of two static comparison unit of lowest order, stop judging unit to be more than or equal to output signal GT or EQ be 1, being less than output signal LT is 0, represents that Data1 is more than or equal to Data2.
6, complete comparison;
In the time stopping being more than or equal to signal GT or EQ and being less than signal LT and having at least one to be 1 of comparing unit, settling signal DONE is just output as 1, represents relatively completing of current data, and circuit is no longer worked.
Above-described embodiment is preferably execution mode of the present invention; but embodiments of the present invention are not limited by the examples; other any do not deviate from change, the modification done under Spirit Essence of the present invention and principle, substitutes, combination, simplify; all should be equivalent substitute mode, within being included in protection scope of the present invention.
Claims (6)
1. a premature termination comparator of realizing based on static logic, it is characterized in that, comprise at least two two static comparison unit and at least one termination judging unit, described two static comparisons are unit cascaded to be connected with termination judging unit again, after described two static comparisons are unit cascaded, each two static comparison unit be less than signal output part, be greater than signal output part respectively with stop judging unit be less than signal input part, being greater than signal input part connects, the equal signal output of two static comparison unit of high bit is connected with time equal signal input of two static comparison unit of a high position, the equal signal output of two static comparison unit of lowest order is connected with the equal signal input that stops judging unit, described termination judging unit is output as the output signal that is more than or equal to of the described premature termination comparator of realizing based on static logic, settling signal and be less than output signal, the data input pin of described two static comparison unit is used for inputting data-signal to be compared, the enable signal input of described each two static comparison unit is connected with the enable signal input that stops judging unit.
2. the premature termination comparator of realizing based on static logic according to claim 1, is characterized in that, described two static comparison unit comprise and are greater than comparison circuit, are less than comparison circuit and comparison of equalization circuit;
The described comparison circuit that is greater than comprises a PMOS pipe (P
1), the 2nd PMOS pipe (P
2), the 3rd PMOS pipe (P
3), the 4th PMOS pipe (P
4), the 5th PMOS pipe (P
5), the 6th PMOS pipe (P
6), the 7th PMOS pipe (P
7), the 8th PMOS pipe (P
8), the 9th PMOS pipe (P
9), a NMOS pipe (N
1), the 2nd NMOS pipe (N
2), the 3rd NMOS pipe (N
3), the 4th NMOS pipe (N
4), the 5th NMOS pipe (N
5), the 6th NMOS pipe (N
6), the 7th NMOS pipe (N
7), the 8th NMOS pipe (N
8), the 9th NMOS pipe (N
9), the first inverter (1); A described PMOS pipe (P
1) source electrode, the 3rd PMOS pipe (P
3) source electrode, the 4th PMOS pipe (P
4) source electrode, the 6th PMOS pipe (P
6) source electrode, the 8th PMOS pipe (P
8) source electrode and the 9th PMOS pipe (P
9) source electrode all connect power supply, the 9th NMOS pipe (N
9) source ground;
The one PMOS pipe (P
1) drain electrode and the 2nd PMOS pipe (P
2) source electrode join, the 2nd PMOS pipe (P
2) drain electrode and NMOS pipe (N
1), the 2nd NMOS pipe (N
2) drain electrode join;
The 3rd PMOS pipe (P
3), the 4th PMOS pipe (P
4) drain electrode and the 5th PMOS pipe (P
5) source electrode join, the 5th PMOS pipe (P
5) drain electrode and the 5th NMOS pipe (N
5) drain electrode join, the 5th NMOS pipe (N
5) source electrode and the 3rd NMOS pipe (N
3), the 4th NMOS pipe (N
4) drain electrode join;
The 6th PMOS pipe (P
6) drain electrode and the 7th PMOS pipe (P
7) source electrode join, the 7th PMOS pipe (P
7) drain electrode and the 6th NMOS pipe (N
6) drain electrode join, the 6th NMOS pipe (N
6) source electrode and the 7th NMOS pipe (N
7) drain electrode join;
The 8th PMOS pipe (P
8), the 9th PMOS pipe (P
9) drain electrode and the input of the first inverter (1) join;
The 2nd PMOS pipe (P
2) drain electrode and the 5th PMOS pipe (P
5), the 5th NMOS pipe (N
5) grid join, the 5th PMOS pipe (P
5) drain electrode and the 7th PMOS pipe (P
7) drain electrode join, the 7th PMOS pipe (P
7) drain electrode and the input of the first inverter (1) join;
The one NMOS pipe (N
1), the 2nd NMOS pipe (N
2), the 3rd NMOS pipe (N
3), the 4th NMOS pipe (N
4), the 7th NMOS pipe (N
7) source electrode all with the 8th NMOS pipe (N
8) drain electrode join, the 8th NMOS pipe (N
8) source electrode and the 9th NMOS pipe (N
9) drain electrode join;
The one PMOS pipe (P
1) and NMOS pipe (N
1) grid all connect the non-signal of the first data low level
the 2nd PMOS pipe (P
2) and the 2nd NMOS pipe (N
2) grid all connect the second data low level signal (B
0); The 3rd PMOS pipe (P
3) and the 3rd NMOS pipe (N
3) grid all connect the first data high signal (A
1); The 4th PMOS pipe (P
4) grid and the 4th NMOS pipe (N
4) grid all connect the high-order non-signal of the second data
the 6th PMOS pipe (P
6) and the 6th NMOS pipe (N
6) grid all connect the first data high signal (A
1); The 7th PMOS pipe (P
7) and the 7th NMOS pipe (N
7) grid all connect the high-order non-signal of the second data
the 8th PMOS pipe (P
8) and the 8th NMOS pipe (N
8) grid all connect the input (EQin) of equal signal; The 9th PMOS pipe (P
9) and the 9th NMOS pipe (N
9) grid all connect enable signal (EN); The output of the first inverter (1) is as the output that is greater than signal (GTout).
3. the premature termination comparator of realizing based on static logic according to claim 2, is characterized in that, described in be less than comparison circuit and comprise the tenth PMOS pipe (P
10), the 11 PMOS pipe (P
11), the 12 PMOS pipe (P
12), the 13 PMOS pipe (P
13), the 14 PMOS pipe (P
14), the 15 PMOS pipe (P
15), the 16 PMOS pipe (P
16), the 17 PMOS pipe (P
17), the 18 PMOS pipe (P
18), the tenth NMOS pipe (N
10), the 11 NMOS pipe (N
11), the 12 NMOS pipe (N
12), the 13 NMOS pipe (N
13), the 14 NMOS pipe (N
14), the 15 NMOS pipe (N
15), the 16 NMOS pipe (N
16), the 17 NMOS pipe (N
17), the 18 NMOS pipe (N
18) and the second inverter (2); Described the tenth PMOS pipe (P
10) source electrode, the 12 PMOS pipe (P
12) source electrode, the 13 PMOS pipe (P
13) source electrode, the 15 PMOS pipe (P
15) source electrode, the 17 PMOS pipe (P
17) source electrode, the 18 PMOS pipe (P
18) source electrode all connect power supply, the 18 NMOS pipe (N
18) source ground;
The tenth PMOS pipe (P
10) drain electrode and the 11 PMOS pipe (P
11) source electrode join, the tenth NMOS pipe (N
10) drain electrode and the 11 NMOS pipe (N
11) drain electrode all with the 11 PMOS pipe (P
11) drain electrode join;
The 12 PMOS pipe (P
12) drain electrode and the 13 PMOS pipe (P
13) drain electrode all with the 14 PMOS pipe (P
14) source electrode join, the 14 PMOS pipe (P
14) drain electrode and the 14 NMOS pipe (N
14) drain electrode join, the 12 NMOS pipe (N
12) drain electrode and the 13 NMOS pipe (N
13) drain electrode all with the 14 NMOS pipe (N
14) source electrode join;
The 15 PMOS pipe (P
15) drain electrode and the 16 PMOS pipe (P
16) source electrode join, the 16 PMOS pipe (P
16) drain electrode and the 15 NMOS pipe (N
15) drain electrode join, the 15 NMOS pipe (N
15) source electrode and the 16 NMOS pipe (N
16) drain electrode join;
The 17 NMOS pipe (N
17) drain electrode and the 18 NMOS pipe (N
18) drain electrode all join with the input of the second inverter (2);
The 14 PMOS pipe (P
14) grid and the 14 NMOS pipe (N
14) grid all with the 11 PMOS pipe (P
11) drain electrode join, the 14 PMOS pipe (P
14) drain electrode and the 16 PMOS pipe (P
16) drain electrode join, the 16 PMOS pipe (P
16) drain electrode and the input of the second inverter (2) join;
The tenth NMOS pipe (N
10) source electrode, the 11 NMOS pipe (N
11) source electrode, the 12 NMOS pipe (N
12) source electrode, the 13 NMOS pipe (N
13) source electrode, the 16 NMOS pipe (N
16) source electrode all with the 17 NMOS pipe (N
17) drain electrode join, the 17 NMOS pipe (N
17) source electrode and the 18 NMOS pipe (N
18) drain electrode join;
The tenth PMOS pipe (P
10) grid and the tenth NMOS pipe (N
10) grid all connect the first data low level signal (A
0); The 11 PMOS pipe (P
11), the 11 NMOS pipe (N
11) grid connect the non-signal of the second data low level
the grid of the 12 PMOS pipe (P12) and the 12 NMOS pipe (N
12) grid all connect the high-order non-signal of the first data
the 13 PMOS pipe (P
13) grid and the 13 NMOS pipe (N
13) grid all connect the second data high signal (B
1); The 15 PMOS pipe (P
15) grid and the 15 NMOS pipe (N
15) grid all connect the high-order non-signal of the first data
the 16 PMOS pipe (P
16) grid and the 16 NMOS pipe (N
16) grid all connect the second data high signal (B
1); The 17 PMOS pipe (P
17) grid and the 17 NMOS pipe (N
17) grid all connect the input (EQin) of equal signal; The 18 PMOS pipe (P
18) grid and the 18 NMOS pipe (N
18) grid all connect enable signal (EN); The output of the second inverter (2) is as the output that is less than signal (LTout).
4. the premature termination comparator of realizing based on static logic according to claim 2, is characterized in that, described comparison of equalization circuit comprises the 19 PMOS pipe (P
19), the 20 PMOS pipe (P
20), the 21 PMOS pipe (P
21), the 22 PMOS pipe (P
22), the 23 PMOS pipe (P
23), the 24 PMOS pipe (P
24), the 25 PMOS pipe (P
25), the 26 PMOS pipe (P
26), the 27 PMOS pipe (P
27), the 28 PMOS pipe (P
28), the 19 NMOS pipe (N
19), the 20 NMOS pipe (N
20), the 21 NMOS pipe (N
21), the 22 NMOS pipe (N
22), the 23 NMOS pipe (N
23), the 24 NMOS pipe (N
24), the 25 NMOS pipe (N
25), the 26 NMOS pipe (N
26), the 27 NMOS pipe (N
27), the 28 NMOS pipe (N
28) and the 3rd inverter (3); Described the 19 PMOS pipe (P
19) source electrode, the 21 PMOS pipe (P
21) source electrode, the 23 PMOS pipe (P
23) source electrode, the 25 PMOS pipe (P
25) source electrode, the 27 PMOS pipe (P
27) source electrode, the 28 PMOS pipe (P
28) source electrode all connect power supply, the 28 NMOS pipe (N
28) source ground;
The 19 PMOS pipe (P
19) drain electrode and the 20 PMOS pipe (P
20) source electrode join, the 21 PMOS pipe (P
21) drain electrode and the 22 PMOS pipe (P
22) source electrode join, the 19 PMOS pipe (P
19) drain electrode and the 21 PMOS pipe (P
21) drain electrode join; The 23 PMOS pipe (P
23) drain electrode and the 24 PMOS pipe (P
24) source electrode join, the 25 PMOS pipe (P
25) drain electrode and the 26 PMOS pipe (P
26) source electrode join, the 23 PMOS pipe (P
23) drain electrode and the 25 PMOS pipe (P
25) drain electrode join;
The 20 PMOS pipe (P
20) drain electrode, the 22 PMOS pipe (P
22) drain electrode, the 24 PMOS pipe (P
24) drain electrode, the 26 PMOS pipe (P
26) drain electrode, the 27 PMOS pipe (P
27) drain electrode and the 28 PMOS pipe (P
28) drain electrode all join with the input of the 3rd inverter (3);
The 20 PMOS pipe (P
20) drain electrode and the 19 NMOS pipe (N
19) drain electrode join, the 19 NMOS pipe (N
19) source electrode and the 21 NMOS pipe (N
21) drain electrode join, the 21 NMOS pipe (N
21) source electrode and the 23 NMOS pipe (N
23) drain electrode join, the 23 NMOS pipe (N
23) source electrode and the 25 NMOS pipe (N
25) drain electrode join; The 26 PMOS pipe (P
26) drain electrode and the 20 NMOS pipe (N
20) drain electrode join, the 20 NMOS pipe (N
20) source electrode and the 22 NMOS pipe (N
22) drain electrode join, the 22 NMOS pipe (N
22) source electrode and the 24 NMOS pipe (N
24) drain electrode join, the 24 NMOS pipe (N
24) source electrode and the 26 NMOS pipe (N
26) drain electrode join; The 21 NMOS pipe (N
21) drain electrode and the 22 NMOS pipe (N
22) drain electrode join, the 25 NMOS pipe (N
25) source electrode and the 26 NMOS pipe (N
26) source electrode all with the 27 NMOS pipe (N
27) drain electrode join, the 27 NMOS pipe (N
27) source electrode and the 28 NMOS pipe (N
28) drain electrode join;
The 19 PMOS pipe (P
19) grid and the 19 NMOS pipe (N
19) grid all connect the first data low level signal (A
0); The 20 PMOS pipe (P
20) grid and the 20 NMOS pipe (N
20) grid all connect the non-signal of the first data low level
the 21 PMOS pipe (P
21) grid and the 21 NMOS pipe (N
21) grid all connect the second data low level signal (B
0); The 22 PMOS pipe (P
22) grid and the 22 NMOS pipe (N
22) grid all connect the non-signal of the second data low level
the 23 PMOS pipe (P
23) grid and the 23 NMOS pipe (N
23) grid all connect the first data high signal (A
1); The 24 PMOS pipe (P
24) grid and the 24 NMOS pipe (N
24) grid all connect the high-order non-signal of the first data
the 25 PMOS pipe (P
25) grid and the 25 NMOS pipe (N
25) grid all connect the second data high signal (B
1); The 26 PMOS pipe (P
26) grid and the 26 NMOS pipe (N
26) grid all connect the high-order non-signal of the second data
the 27 PMOS pipe (P
27) grid and the 27 NMOS pipe (N
27) grid all connect the input (EQin) of equal signal; The 28 PMOS pipe (P
28) grid and the 28 NMOS pipe (N
28) grid all connect enable signal (EN); The output of the 3rd inverter (3) is as the output of equal signal (EQout).
5. the premature termination comparator of realizing based on static logic according to claim 1, is characterized in that, described termination judging unit comprises and is more than or equal to signal judging circuit, is less than signal judging circuit and logic sum gate (OR1);
The described signal judging circuit that is more than or equal to comprises that equaling signal PMOS manages (P
eQ), the 0th be greater than signal PMOS pipe (P
gT0), the 1st be greater than signal PMOS pipe (P
gT1), N-1 is greater than signal PMOS pipe (P
gTn-1), the first enable signal PMOS pipe (P
eN1), equal signal NMOS pipe (N
eQ), the 0th be greater than signal NMOS pipe (N
gT0), the 1st be greater than signal NMOS pipe (N
gT1), N-1 is greater than signal NMOS pipe (N
gTn-1), the first enable signal NMOS pipe (N
eN1) and the 4th inverter (4);
The described signal PMOS pipe (P that equals
eQ), the 0th be greater than signal PMOS pipe (P
gT0), the 1st be greater than signal PMOS pipe (P
gT1) and N-1 be greater than signal PMOS pipe (P
gTn-1) series connection;
Described N-1 is greater than signal PMOS pipe (P
gTn-1) source electrode and the first enable signal PMOS pipe (P
eN1) source electrode connect, equal signal PMOS pipe (P
eQ) drain electrode and the first enable signal PMOS pipe (P
eN1) drain electrode connect, the first enable signal PMOS pipe (P
eN1) source electrode connect power supply;
The described signal NMOS pipe (NE that equals
q), the 0th be greater than signal NMOS pipe (N
gT0), the 1st be greater than signal NMOS pipe (N
gT1) and N-1 be greater than signal NMOS pipe (N
gTn-1) parallel connection;
The described signal NMOS pipe (NE that equals
q) source electrode, the 0th be greater than signal NMOS pipe (N
gT0) source electrode, the 1st be greater than signal NMOS pipe (N
gT1) source electrode, N-1 be greater than signal NMOS pipe (N
gTn-1) source electrode all with the first enable signal NMOS pipe (N
eN1) drain electrode connect, the first enable signal NMOS pipe (N
eN1) source ground;
The described signal NMOS pipe (N that equals
eQ) drain electrode be connected with the input of the 4th inverter (4);
The described signal PMOS pipe (P that equals
eQ) grid and equal signal NMOS pipe (N
eQ) grid all connect equal input signal (EQ); The 0th is greater than signal PMOS pipe (P
gT0) grid and the 0th be greater than signal NMOS pipe (N
gT0) grid all connect the 0th and be greater than signal (GT[0]); The 1st is greater than signal PMOS pipe (P
gT1) grid and the 1st be greater than signal NMOS pipe (N
gT1) grid all connect the 1st and be greater than signal (GT[1]); N-1 is greater than signal PMOS pipe (P
gTn-1) grid and N-1 be greater than signal NMOS pipe (N
gTn-1) grid all connect N-1 and be greater than signal (GT[N-1]); The first enable signal PMOS pipe (P
eN1) grid and the first enable signal NMOS pipe (N
eN1) grid all connect enable signal (EN); The 4th inverter (4) is output as and is more than or equal to signal (GT or EQ);
The described signal judging circuit that is less than comprises that the 0th is less than signal PMOS pipe (P
lT0), the 1st be less than signal PMOS pipe (P
lT1), N-1 is less than signal PMOS pipe (P
lTn-1), the second enable signal PMOS pipe (P
eN2), the 0th be less than signal NMOS pipe (N
lT0), the 1st be less than signal NMOS pipe (N
lT1), N-1 is less than signal NMOS pipe (N
lTn-1), the second enable signal NMOS pipe (N
eN2) and the 5th inverter (5);
The described the 0th is less than signal PMOS pipe (P
lT0), the 1st be less than signal PMOS pipe (P
lT1) and N-1 be less than signal PMOS pipe (P
lTn-1) series connection;
Described N-1 is less than signal PMOS pipe (P
lTn-1) source electrode and the second enable signal PMOS pipe (P
eN2) source electrode connect, the 0th is less than signal PMOS pipe (P
lT0) drain electrode and the second enable signal PMOS pipe (P
eN2) drain electrode connect, the second enable signal PMOS pipe (P
eN2) source electrode connect power supply;
The described the 0th is less than signal NMOS pipe (N
lT0), the 1st be less than signal NMOS pipe (N
lT1) and N-1 be less than signal NMOS pipe (N
lTn-1) parallel connection;
The described the 0th is less than signal NMOS pipe (N
lT0) source electrode, the 1st be less than signal NMOS pipe (N
lT1) source electrode, N-1 be less than signal NMOS pipe (N
lTn-1) source electrode and the second enable signal NMOS pipe (N
eN2) source electrode all with the second enable signal NMOS pipe (N
eN2) drain electrode connect, the second enable signal NMOS pipe (N
eN2) source ground;
The described the 0th is less than signal NMOS pipe (N
lT0) drain electrode be connected with the input of the 5th inverter (5);
The described the 0th is less than signal PMOS pipe (P
lT0) grid and the 0th be less than signal NMOS pipe (N
lT0) grid all connect the 0th and be less than signal (LT[0]); The 1st is less than signal PMOS pipe (P
lT1) grid and the 1st be less than signal NMOS pipe (N
lT1) grid all connect the 1st and be less than signal (LT[1]); N-1 is less than signal PMOS pipe (P
lTn-1) grid and N-1 be less than signal NMOS pipe (N
lTn-1) grid all connect N-1 and be less than signal (LT[N-1]); The second enable signal PMOS pipe (P
eN2) grid and the second enable signal NMOS pipe (N
eN2) grid all connect enable signal (EN); The 5th inverter (5) is output as and is less than signal (LT);
The output that the output of described the 4th inverter (4) is more than or equal to signal (GT or EQ), the 5th inverter (5) is less than signal (LT) and is connected with the input of logic sum gate (OR1), and the output of logic sum gate (OR1) is settling signal (DONE).
6. a control method of controlling the premature termination comparator of realizing based on static logic described in claim 1, is characterized in that, comprises the following steps:
Step 1: the data of two same bit-width that will compare are inputted respectively the first input signal (Data1) and the second input signal (Data2);
Step 2: the enable signal of input (En) is connected to logical one level, start comparator work;
Step 3: wait for the settling signal (DONE) of output, if logical one, observation is more than or equal to output signal (GT or EQ), is less than output signal (LT); If be more than or equal to output signal (GT or EQ) for logical one, comparative result is that the first input signal is more than or equal to the second input signal; If be less than output signal (LT) for logical one, comparative result is that the first input signal is less than the second input signal;
Step 4: the enable signal of input (En) is connected to logical zero level, comparator is resetted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410201528.5A CN104009738A (en) | 2014-05-13 | 2014-05-13 | Early termination comparator realized on the basis of static logic and control method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410201528.5A CN104009738A (en) | 2014-05-13 | 2014-05-13 | Early termination comparator realized on the basis of static logic and control method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104009738A true CN104009738A (en) | 2014-08-27 |
Family
ID=51370255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410201528.5A Pending CN104009738A (en) | 2014-05-13 | 2014-05-13 | Early termination comparator realized on the basis of static logic and control method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104009738A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1964190A (en) * | 2006-12-12 | 2007-05-16 | 北京中星微电子有限公司 | A method and device to reduce power loss of comparator |
| US7782093B2 (en) * | 2007-05-23 | 2010-08-24 | Infineon Technologies Ag | Integrated circuit and method of detecting a signal edge transition |
| CN203984376U (en) * | 2014-05-13 | 2014-12-03 | 华南理工大学 | A kind of premature termination comparator of realizing based on static logic |
-
2014
- 2014-05-13 CN CN201410201528.5A patent/CN104009738A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1964190A (en) * | 2006-12-12 | 2007-05-16 | 北京中星微电子有限公司 | A method and device to reduce power loss of comparator |
| US7782093B2 (en) * | 2007-05-23 | 2010-08-24 | Infineon Technologies Ag | Integrated circuit and method of detecting a signal edge transition |
| CN203984376U (en) * | 2014-05-13 | 2014-12-03 | 华南理工大学 | A kind of premature termination comparator of realizing based on static logic |
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| Title |
|---|
| 叶德盛: "低功耗异步LDPC解码器设计", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
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Application publication date: 20140827 |