CN104009071B - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN104009071B CN104009071B CN201310454662.1A CN201310454662A CN104009071B CN 104009071 B CN104009071 B CN 104009071B CN 201310454662 A CN201310454662 A CN 201310454662A CN 104009071 B CN104009071 B CN 104009071B
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- groove
- auxiliary tank
- link slot
- circumferential groove
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 92
- 230000005684 electric field Effects 0.000 claims description 44
- 230000010354 integration Effects 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 106
- 229920005591 polysilicon Polymers 0.000 abstract description 103
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 230000002093 peripheral effect Effects 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 127
- 238000010276 construction Methods 0.000 description 21
- 239000011229 interlayer Substances 0.000 description 13
- 238000000034 method Methods 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 230000009471 action Effects 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 7
- 230000009467 reduction Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 230000000116 mitigating effect Effects 0.000 description 3
- 239000004744 fabric Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Abstract
The invention provides a semiconductor device. In a groove gate-shaped semiconductor device, a pressureproof structure can be realized in a simple manufacturing method. A groove (10) is provided with a connecting groove (13) which extends to an upper side (an end side of a chip or an opposite side of a device groove (11)) from a peripheral groove (12). The end of an opposite side of one side of the peripheral groove (12) connected to the connecting groove (13) is provided with an auxiliary groove (14) which is oval and has a short shaft wider than the connecting groove (13). A total lie contact point (511) is formed right above the auxiliary groove (14), and accordingly a total line wiring (35) and a polysilicon layer (polysilicon wiring) are connected in the auxiliary groove (14).
Description
Technical field
The present invention relates to semiconductor device, more particularly to the structure that the semiconductor device of switch motion can be carried out with high current
Make.
Background technology
In recent years, can be with the power MOSFET of large driven current density（Metal Oxide Semiconductor Field
Effect Transistor：Metal-oxide semiconductor (MOS)）, igbt（Insulated Gate Bipolar
Transistor, hereinafter referred to as IGBT）It has been used as switch element.
In this power semiconductor, according to the conduction and cut-off of gate voltage control action electric current.In power MOSFET
In, the action current refers to the electric current between source-leakage, in IGBT, in addition to carrying out with power MOSFET identical actions also
The action of bipolar transistor is carried out simultaneously, and the action current flows through in emitter stage-inter-collector.
In groove grid（trench gate）In the IGBT of type, on the surface of semiconductor layer a plurality of groove portion is formed（trench）,
In groove portion formed gate insulating film, as the polysilicon layer of gate electrode, the inner surface of each groove plays a role as MOSFET.With each groove
The corresponding each gate electrode in portion connects side by side, and is connected with route bus.Route bus are for applying to gate electrode in action
Alive wiring.Figure 15 is the vertical view viewed from above of of the structure of the groove in the IGBT for show schematically groove gate type
Figure.In the figure, the flat shape of groove and the relation of route bus are schematically illustrated.
Figure 15's（a）In, the polycrystalline silicon cloth in groove 80 and route bus 35 position relationship in the plane and groove 80
Line and the position relationship that the connecting portion of route bus 35 is bus contact 911.
Figure 15's（b）In the flat shape of groove 80 is shown.7 device grooves that groove 80 is extended by the above-below direction in figure
81 and the upper direction in figure is by the connection of these device grooves and left and right directions extends in figure circumferential groove 82 is constituted, these grooves
It is integrated.End of each device groove 81 towards chip（Upside in figure）Extend parallel to, a circumferential groove 82 is designed to
In the end side of chip, device groove 81 is vertical is connected with these.
Figure 15's（c）In illustrate within and around groove 80 formed polysilicon layer 32,90 flat shape.Such as
It is described afterwards, here, polysilicon layer 32 is the polysilicon layer in device groove 81.Therefore, the flat shape and device of polysilicon layer 32
The flat shape of groove 81 is substantially uniform.On the other hand, polysilicon layer 90 is the polysilicon layer of circumferential groove 82 and its surrounding, and than outer
Circumferential groove 82 is big.These polysilicon layers are integrated in groove 80, and are adulterated in the way of raising electrical conductivity, thus make
Play a role for wiring.
Figure 15's（d）In the position relationship of polysilicon layer 90 and bus contact 911 is shown, such as Figure 15（a）It is shown,
The position of bus contact 911 connects polysilicon layer 90 and route bus 35.In addition, Figure 15's（a）In, omit and touched with bus
The description of the polysilicon layer 32 in 911 unrelated device grooves 81 of point.
Below, using Figure 15's（a）In the section in C-C directions illustrate in greater detail the construction.Figure 16 is to represent this section
The figure in face.Here, for convenience, the section of the left and right directions in the side of device groove 81 illustrates Figure 15, illustrates in the side of circumferential groove 82
The section of the above-below direction in Figure 15, the single dotted broken line in Figure 16 represents the position of the vertical curve of C-C.As shown in figure 16, groove
80（Device groove 81, circumferential groove 82）Be formed as the surface insertion p layers 21 from semiconductor layer 20, the semiconductor layer 20 is in face side
With p layers（Basalis）21、n-Layer 22, n+Layer 23.n-Layer 22 is formed only in the side with device groove 81, thus device groove 81
Lower end reach n-Layer 22, the lower end of circumferential groove 82 reaches n+Layer 23.Wherein, the width of device groove 81（Figure 15's（b）In a left side
The width of right direction）With the width of circumferential groove 82（Figure 15's（b）In above-below direction width）It is identical.In addition, actually in n+The downside of layer 23 is formed with collector layer or colelctor electrode etc., but, omit about their record in figure 16.
As shown in figure 16, across relatively thin gate insulating film 31, the shape in device groove 81 inside device groove 81, circumferential groove 82
Into there is polysilicon layer（Gate electrode）32, it is formed with polysilicon layer in circumferential groove 82（Polysilicon wire）90.Polysilicon layer（Grid electricity
Pole）32nd, polysilicon layer（Polysilicon wire）90 are formed as filling device groove 81, circumferential groove respectively across relatively thin gate insulating film 31
82。
Wherein, the n of the source region as MOSFET is formed with the both sides of device groove 81+Layer 24.Therefore, in device groove 81
In, by controlling polysilicon layer（Gate electrode）32 current potential, is capable of the n of the inner side of control device groove 81+Layer 24 and n-Layer 22 it
Between p layers 21 in raceway groove conduction and cut-off.
Also, the side of device groove 81 is being formed with, in whole p layers 21 and n+Layer 24 is formed with the transmitting formed by aluminium etc.
Pole 33.Wherein, polysilicon layer（Gate electrode）32 are insulated by interlayer insulating film 34 with emitter stage 33.According to this construction, pass through
The current potential of control grid electrode 32, can control in emitter stage 33 and the colelctor electrode for being located at downside（It is not shown）Between the electric current that flows through
Conduction and cut-off.
On the other hand, in circumferential groove 82, due to not forming n+Layer 24, thus do not carry out this action.But,
As shown in figure 15, because device groove 81 and circumferential groove 82 are connected, thus the polysilicon layer in each device groove 81（Gate electrode）32
With the polysilicon layer in circumferential groove 82（Polysilicon wire）90 are actually integrated.That is, circumferential groove 82 be in order to will with it is a plurality of
The corresponding polysilicon layer of device groove 81（Gate electrode）32 connect side by side, and it are connected with route bus 35 and are formed.
This, as shown in figure 16, the polysilicon layer in circumferential groove 82（Polysilicon wire）90 not only fill circumferential groove 82, and expand it to
Around, the right side of circumferential groove 82 in figure 16 is connected with route bus 35.Route bus 35 are utilized and the identical of emitter stage 33
Material is constituted, again by the insulation such as interlayer insulating film 91,92 and p layers 21.Therefore, interlayer insulating film 91 be open out bus touch
Point 911.Figure 15 illustrates groove 80（Device groove 81, circumferential groove 82）, polysilicon layer（Polysilicon wire）33rd, bus contact 911
And the position relationship in the plane of route bus 35.
According to this construction, polysilicon layer can be passed through（Polysilicon wire）The multiple polysilicon layers of 90 connections（Gate electrode）
32, control whole polysilicon layers by route bus 35（Gate electrode）32 current potential.
Figure 17's（a）（b）, Figure 18（c）（d）, Figure 19（e）It is to represent the polysilicon layer to be formed in above-mentioned construction（Grid
Electrode）32nd, polysilicon layer（Polysilicon wire）The operation sectional view of manufacturing process when 90.Here, illustrating and the device in Figure 16
The relevant section in part groove 81, the respective position of circumferential groove 82.
First, such as Figure 17（a）It is shown, device groove 81, periphery is formed on the surface of semiconductor layer 20 by dry-etching
Groove 82, then forms gate insulating film 31.Now, form Figure 15's（b）The photoresist of the shown shape by opening grooving 80
Agent pattern, by carrying out dry-etching, while forming device groove 81, circumferential groove 82.Now, if device groove 81, circumferential groove 82
Width it is identical, then easily enter to exercise their depth also identical dry-etching.Also, by thermal oxide, established
The inside of device groove 81, circumferential groove 82, it is also possible to form uniform and relatively thin gate insulating film 31.
Then, such as Figure 17（b）It is shown, after interlayer dielectric 92 are formed in the side of circumferential groove 82, formed using CVD etc.
Uniform and thicker polysilicon layer 40.Thus, device groove 81, the inside of circumferential groove 82 are filled by polysilicon layer 40, and entirely
Surface is also covered by polysilicon layer 40.
Then, such as Figure 18（c）It is shown, with Figure 15's（c）Shown polysilicon layer（Polysilicon wire）90 shape pair
Ying Di, forms the photoresist layer 100 for covering the region for including circumferential groove 82.Now, light is not formed in the side of device groove 81
Cause resist layer 100.
Then, in the state of photoresist layer 100 is formed with, the dry-etching of polysilicon layer 40 is carried out（Eat-back）.
Thus, in addition to being formed with the position of photoresist layer 100, the polysilicon layer 40 on surface is uniformly removed, final
Arrive Figure 18's（d）Shown shape.Then, by removing photoresist layer 100, such as Figure 19（e）It is shown, in device groove 81
Side forms polysilicon layer（Gate electrode）32, form polysilicon layer in the side of circumferential groove 82（Polysilicon wire）90.The side of device groove 81
Polysilicon layer（Gate electrode）32 inside for only remaining in device groove 81.Then, insulating barrier is formed in entire surface and is patterned,
It is consequently formed interlayer insulating film 34,91.Now, the bus contact 911 in interlayer insulating film 91 is also formed.
That is, above-mentioned construction can be manufactured easily with the method shown in Figure 17～19.
But, there are the problem points of following explanation in above-mentioned construction.
Figure 20 be schematically enlarged representation by the shape after eat-back（Figure 19's（e））The figure in the region of middle use dotted line.
In the figure, the structure of the upper end of circumferential groove 82 is exaggerated and represents.As described above, gate insulating film 31 is shape by thermal oxide
Into, and be uniform and relatively thinly form in device groove 81, the inside of circumferential groove 82.But, it is device groove 81 on surface, outer
The corner of circumferential groove 82 is also formed uniformly gate insulating film 31, actually highly difficult, as shown in figure 20, in their corner,
Gate insulating film 31 is generally thin than other regions.Therefore, the polysilicon layer of the corner portion on the surface of circumferential groove 82（Polysilicon wire）90
With semiconductor layer 20（P layers 21）Between pressure reduction.On the other hand, such as Figure 18（d）It is shown, in the side of device groove 81, at it
Corner, polysilicon layer 40 is removed by eat-back, and, as shown in figure 16, later the part is covered by interlayer insulating film 34, because
This, even if gate insulating film 31 is thinning in corner, the insulation in the region is pressure will not also to become problem.On the other hand, Figure 15,16
In shown construction, in order to arrange bus contact 911, polysilicon layer in the outside of circumferential groove 82（Polysilicon wire）90 is certain logical
Cross the corner.
That is, in above-mentioned construction, the grid of IGBT or power MOSFET it is pressure unrelated with original action, by order to
The restriction of the gate insulating film 31 in the circumferential groove 82 for connecting and arranging.If making the thickness of gate insulating film 31 integrally thickening, though
So its it is pressure substantially improved, but in order to carry out good switch motion, need to make the gate insulating film 31 in device groove 81
It is thinning.
Thus, for example what the gate insulating film that the corner portion for making periphery rooved face is recorded in patent document 1 was locally thicker
Construction.In addition, recorded in patent document 2 being constructed as below：Circumferential groove is not used, by the terminal part for increasing device groove, is disappeared
Except the uneven thickness of the gate insulating film of this corner portion, and polysilicon wire is taken out from the terminal part.
【Patent document 1】Japanese Unexamined Patent Publication 07-249769 publication
【Patent document 2】Japanese Unexamined Patent Publication 2000-200901 publications
But, in the technology that patent document 1 is recorded, manufacturing process substantially becomes complicated.
In addition, in the technology that patent document 2 is recorded, although the thickness of gate insulating film of groove corner portion can be improved not
, but, make the thickness substantially uniformity of the gate insulating film in the groove of this cross sectional shape, it is actually highly difficult.The opposing party
Face, in the art, forms polysilicon wire on the gate insulating film for be formed at the corner, and this point is not changed in.Therefore, adopt
It also is difficult to fully improve pressure with the technology.
That is, in the semiconductor device of groove gate type（IGBT, power MOSFET）In, it is difficult with simple manufacture method and realizes
Construction pressure enough can be obtained.
The content of the invention
What the present invention was exactly proposed in view of the above problems, its object is to, there is provided the invention for solving the above problems.
The present invention is solved the above problems using the structure of described below.
The semiconductor device of the present invention has following structure：Respective inside being formed on the surface of semiconductor layer, there is grid electricity
The a plurality of device groove of pole, a plurality of device groove is the groove portion on the surface for extending in one direction and being formed at semiconductor layer, multiple
The gate electrode is connected side by side with route bus, it is characterised in that be formed with the device on the surface of the semiconductor layer
Groove obtained from the integration of part groove, circumferential groove, link slot and auxiliary tank, the circumferential groove is that edge intersects with one direction
The groove portion that extends of direction, connect the respective one end of a plurality of device groove, the link slot is extended along one direction
Groove portion, be connected with the circumferential groove in the opposition side of the side for being connected with the device groove of the circumferential groove, the auxiliary
Groove is described by constituting in the groove located at the end of the opposition side of the side being connected with the circumferential groove of the link slot
The wiring material of gate electrode is filled into the position lower than the surface of the semiconductor layer, and the wiring is connected in the auxiliary tank
Material and the route bus.
The semiconductor device of the present invention is characterised by, in the groove, link slot described in the width ratio of the auxiliary tank
The direction vertical with bearing of trend on width width.
The semiconductor device of the present invention is characterised by that in the groove, phase is compared at the interval of 2 adjacent link slots
The interval width of 2 adjacent device grooves.
The semiconductor device of the present invention is characterised by, in the groove, the link slot is hanging down with one direction
Do not connect the position of the device groove and the circumferential groove on straight direction, be connected with the circumferential groove.
The semiconductor device of the present invention is characterised by, electric field is formed between 2 adjacent auxiliary tanks and is relaxed
Groove, it is to extend along one direction and be formed at the surface and inside of the semiconductor layer filled with described that the electric field relaxes groove
The groove portion of wiring material.
The semiconductor device of the present invention is characterised by that the electric field mitigation groove is formed in the semiconductor layer must be than institute
State auxiliary tank and/or the link slot is shallow.
The semiconductor device of the present invention is characterised by that the electric field is relaxed on the direction vertical with bearing of trend of groove
Width broadens in the position local adjacent with the auxiliary tank.
The present invention is configured as described above, thus in the semiconductor device of groove gate type, can be using simple manufacture
Method realizes that construction pressure enough can be obtained.
Description of the drawings
Fig. 1 is the flat shape for representing the groove periphery used in the semiconductor device of the 1st embodiment of the present invention
Top view.
Fig. 2 is the sectional view in the A-A directions of the semiconductor device of the 1st embodiment of the present invention.
Fig. 3 is the sectional view in the B-B directions of the semiconductor device of the 1st embodiment of the present invention.
Fig. 4 is the flat shape for representing the groove periphery used in the semiconductor device of the 1st embodiment of the present invention
The top view of another.
Fig. 5 is the figure of the Potential distribution in the semiconductor layer for show schematically groove bottom.
Fig. 6 is to be schematically illustrated at the figure using the Potential distribution in semiconductor layer during electric field relaxation layer.
Fig. 7 is the flat shape for representing the groove periphery used in the semiconductor device of the 2nd embodiment of the present invention
Top view.
Fig. 8 is the 1st variation periphery for representing the groove used in the semiconductor device of the 2nd embodiment of the present invention
The top view of flat shape.
Fig. 9 is the 2nd variation periphery for representing the groove used in the semiconductor device of the 2nd embodiment of the present invention
The top view of flat shape.
Figure 10 is the 3rd variation periphery for representing the groove used in the semiconductor device of the 2nd embodiment of the present invention
Flat shape top view.
Figure 11 is the 4th variation periphery for representing the groove used in the semiconductor device of the 2nd embodiment of the present invention
Flat shape top view.
Figure 12 is the 5th variation periphery for representing the groove used in the semiconductor device of the 2nd embodiment of the present invention
Flat shape top view.
Figure 13 is the 6th variation periphery for representing the groove used in the semiconductor device of the 2nd embodiment of the present invention
Flat shape top view.
Figure 14 is the 7th variation periphery for representing the groove used in the semiconductor device of the 2nd embodiment of the present invention
Flat shape top view.
Figure 15 is the top view of the flat shape for representing the groove periphery used in past semiconductor device.
Figure 16 is the sectional view in the C-C directions of past semiconductor device.
Figure 17 is the operation sectional view of the manufacture method for representing past semiconductor device（One of）.
Figure 18 is the operation sectional view of the manufacture method for representing past semiconductor device（Two）.
Figure 19 is the operation sectional view of the manufacture method for representing past semiconductor device（Three）.
Figure 20 is the sectional view of the construction of the circumferential groove upper end of the past semiconductor device of enlarged representation.
Label declaration
1 semiconductor device（IGBT）；10th, 70,71,80 groove；11st, 81 device groove；12nd, 82 circumferential groove；13 link slots；14、
72 auxiliary tanks；15th, 73 electric fields relax groove；20 semiconductor layers；21p layers（Basalis：Semiconductor layer）；22n-Layer（Semiconductor layer）；
23n+Layer（Semiconductor layer）；24n+Layer（Source region）；31 gate insulating films；32 polysilicon layers（Gate electrode）；33 emitter stages；34、51、
91st, 92 interlayer insulating film；35 route bus；40 polysilicon layers；50th, 90 polysilicon layer（Polysilicon wire）；100 photoresists
Layer；151 part 1s；152 part 2s；153 third portions；511st, 911 bus contact.
Specific embodiment
Below, the semiconductor device of embodiments of the present invention is illustrated.The semiconductor device is by gate control raceway groove
Conduction and cut-off carrys out the semiconductor element of the conduction and cut-off of control electric current.Also, it is formed with extend in parallel in one direction many
Individual groove portion（Device groove）, gate electrode is in each device groove.Each gate electrode connects side by side in the end side of chip with route bus
Connect.Identically with the example of Figure 15, in addition to device groove, the circumferential groove for gate electrode to be connected side by side is additionally provided with, by device
Groove and groove obtained from circumferential groove integration are formed at the surface of semiconductor layer.
（1st embodiment）
Below, the semiconductor device of the 1st embodiment of the present invention is illustrated.The semiconductor device is IGBT.Fig. 1 is to illustrate
Ground represents shape, the top view of position relationship of the groove 10 and route bus 35 of the semiconductor device 1 etc..In addition, Fig. 2, Fig. 3 are
The A-A directions of the semiconductor device 1, the sectional view in B-B directions.
Fig. 1 corresponds to Figure 15, Fig. 1's（a）In illustrate groove 10, route bus 35, the flat shape of bus contact 511,
Position relationship.
Such as Fig. 1（b）Shown, the groove 10 being formed in the semiconductor device 1 also is provided with the above-below direction in figure（One side
To）The 7 device grooves 11 for extending and upper end in these figures（One end）It is connected and the right and left in figure with these device grooves 11
To（The direction intersected with a direction）The circumferential groove 12 of extension.This point is identical with the structure of Figure 15.The inside of device groove 10
And the construction that is adjacent is also identical.That is, the structure phase of semiconductor layer 20, gate insulating film 31 for being used etc. and Figure 15, Figure 16
Together.Polysilicon layer in device groove 11（Gate electrode）32nd, the shape of interlayer insulating film 34 etc. is also identical.Additionally, it is preferred that circumferential groove
12 width（The width of the above-below direction in Fig. 1）With the width of device groove 11（The width of the left and right directions in Fig. 1）It is equal.
Wherein, link slot 13 is additionally provided with the groove 10, the link slot 13 is from circumferential groove 12 towards upper side（The end of chip
Portion side or the opposition side of device groove 11）Extend.It is preferred that link slot 13 is parallel with device groove 11, its width（Right and left in Fig. 1
To width）It is identical with device groove 11.And, it is assumed that the connecting portion of link slot 13 and circumferential groove 12 and device groove 11 and periphery
The connecting portion of groove 12 is different.Therefore, in the flat shape of the groove 10（Fig. 1's（b））In be formed with road junction footpath without shape
Into four branch road footpaths（Become the part of cross shape）.Therefore, link slot 13 is between 2 adjacent device grooves 11, from circumferential groove
12 to the opposition side of this 2 device grooves 11 extends.Also, in the gap of 2 adjacent link slots 13 across circumferential groove 12
Opposition side has three device grooves 11.That is, the interval of 2 adjacent link slots 13 is configured to than 2 adjacent device grooves 11
Interval width.
Auxiliary tank 14 is formed with the end of the opposition side of the side being connected with circumferential groove 12 of link slot 13, the auxiliary tank
14 is oval, and its short axle is wider than link slot 13.Auxiliary tank 14 becomes a part for link slot 13.
Polysilicon layer is also formed with circumferential groove 12, link slot 13, auxiliary tank 14（Polysilicon wire）50.But, this
When polysilicon layer（Polysilicon wire）50 cross sectional shape and aforesaid polysilicon layer（Polysilicon wire）90 is different, only formed
In the inside of these grooves.This point is equally applicable to the polysilicon layer in device groove 11（Gate electrode）32.Therefore, polysilicon layer
（Polysilicon wire）50 and polysilicon layer（Gate electrode）32 are integrated, and this point is identical with the structure of Figure 15, but, polysilicon
Layer 32,50 is all the inside for being only formed at groove 10, and this point differs widely with the structure of Figure 15.Therefore, polysilicon layer 32,50
Flat shape such as Fig. 1（c）It is shown roughly the same with the flat shape of groove 10.
In addition, as shown in Figure 2 and Figure 3, surround auxiliary tank 14 and form interlayer insulating film 51, open on interlayer insulating film 51
Mouth goes out bus contact 511.Route bus 35 and polysilicon layer（Polysilicon wire）50 are connected by bus contact 511.Such as Fig. 1
's（d）Shown, bus contact 511 is formed in auxiliary tank 14 and less than auxiliary tank 14 when overlooking.
In this configuration, bus contact 511 is formed at the surface of auxiliary tank 14, thus route bus 35 and polysilicon
Layer（Polysilicon wire）50 connections in auxiliary tank 14.Therefore, there is no need to the polysilicon layer in the construction such as Figure 15（Polycrystalline silicon cloth
Line）90 like that, by polysilicon layer（Polysilicon wire）50 extend to groove 10（Circumferential groove 12, link slot 13, auxiliary tank 14）
Outside.Due to bus contact 511 is located in auxiliary tank 14, thus polysilicon layer is only formed in auxiliary tank 14（Polysilicon
Wiring）50.
Therefore, there is no need to photoresist layer 100 be formed the manufacture method as shown in Figure 17～19 and to polysilicon
Layer（Polysilicon wire）50 are patterned.As long as forming above-mentioned groove 10, it becomes possible to the polysilicon layer in device groove 11（Grid electricity
Pole）32 polysilicon layers for forming structure shown in Fig. 2 by being etched back in the same manner（Polysilicon wire）50.That is, Figure 18 is not required the use of
In photoresist layer 100 can be formed Fig. 1～Fig. 3 described in construction.Therefore, there is no need to for forming photoresist layer
100 photo-mask process.
In addition, in this case, due to not requiring the use of photoresist layer 100 by carry out the eat-back of polysilicon layer,
Thus the situation during eat-back is not changed in the side of device groove 11, the side of circumferential groove 12, the side of link slot 13, the side of auxiliary tank 14.Therefore,
In this case, as shown in Figure 2 and Figure 3, the polysilicon layer in its section and device groove 11（Gate electrode）32 in the same manner, polycrystalline
Silicon layer（Polysilicon wire）50 only remain in circumferential groove 12, link slot 13, the inside of auxiliary tank 14, can make it topmost than outer
Circumferential groove 12, link slot 13, the corner of auxiliary tank 14（The surface of semiconductor layer 20）It is low.Therefore, even if on the surface of semiconductor layer 20
Circumferential groove 12, link slot 13, the corner portion of auxiliary tank 14 the local of gate insulating film 31 it is thinning in the case of, the thinning grid are exhausted
Velum 31 and polysilicon layer（Polysilicon wire）50 also will not contact, and at the position interlayer insulating film shown in Fig. 2, Fig. 3 is formed
51.As shown in Fig. 2 being same in this construction and device groove 11.Therefore, even if the gate insulation of the corner portion in auxiliary tank 14
In the case that the local of film 31 is thinning, polysilicon layer（Polysilicon wire）50 with semiconductor layer 20（P layers 21）Between it is pressure not yet
Can reduce.
That is, can obtain pressure enough in the semiconductor device 1, and can be somebody's turn to do using simple manufacture method
Semiconductor device 1.
In addition, in said structure, making the width of device groove 11, circumferential groove 12, link slot 13 identical, auxiliary tank 14 is made
Width（The width of the left and right directions in Fig. 1：Oval short axle）It is wider than the width.This is to pass through to increase bus contact
511 area, reduces polysilicon layer（Polysilicon wire）Contact resistance between 50 and route bus 35.This structure causes to connect
Interval between access slot 13 is wider than the interval between device groove 11, it is thus possible to easily realize.In addition, according to this structure,
Easily realization is formed in the opening of the bus contact 511 on auxiliary tank 14（The dry-etching of interlayer insulating film 51）.
Alternatively, it is also possible to make auxiliary tank 14 broaden while the interval for making link slot 13 is identical with device groove 11.Fig. 4's
（a）Groove, route bus 35, the flat shape of bus contact 511, position relationship now is represented, Fig. 4's（b）Groove is only shown
Flat shape.The figure corresponds respectively to Fig. 1's（a）（b）.In this configuration, between 2 adjacent device grooves 11, from outer
12 opposition sides in device groove 11 of circumferential groove extend to form link slot 13.Auxiliary tank 14 is provided with the end of each link slot 13,
But, the distance between auxiliary tank 14 and circumferential groove 12（The length of link slot 13）It is configured to according to adjacent auxiliary tank 14
It is different.In the structure of Fig. 4, the distance is configured to three kinds of distances.According to this structure, even if broadening in auxiliary tank 14 and increasing
In the case of the area of big single bus contact 511, it is also possible to increase sum, the gross area of bus contact 511.Accordingly, it is capable to
It is enough further to reduce route bus 35 and polysilicon layer（Polysilicon wire）Resistance between 50.
In said structure, dry-etching is adopted in order to form groove 10 in semiconductor layer 20, but, now typically lose
Carve speed fast in the region of wider width in groove 10.Therefore, the position that generally there is wider width in groove 10 deepens, width compared with
The narrow position tendency more shallow than the position of wider width.As described later, the situation of pressure reduction is even so there is also, thus it is excellent
Choosing makes the width of device groove 11, circumferential groove 12, link slot 13 identical.In addition, in the examples described above, the width ratio of auxiliary tank 14 should
Width width, however, it is possible to so that the width of auxiliary tank 14 is identical with their width.In this case, link slot itself
End essentially becomes auxiliary tank.In this case, bus contact is less than the width, but, as long as the part can be made
Contact resistance is sufficiently small, then can also adopt this construction.
In addition, as it was previously stated, the connection of the connecting portion of link slot 13 and circumferential groove 12 and device groove 11 and circumferential groove 12
Position is different, thus road junction footpath is formed in the flat shape of the groove 10 without forming four branch road footpaths.This is to suppress
In the case where four branch road footpaths are defined, width substantially broadens on the diagonal of its crossover sites, and suppresses groove 10 to exist
The part deepens or etches shape defect.But, in the pressure reduction due to the part and due to aforementioned thinning grid
The pressure reduction of dielectric film compare it is negligible in the case of, it is also possible to four branch road footpaths are formed in groove 10.
In addition, in above-mentioned construction, the flat shape of auxiliary tank is set to into ellipse, but, as long as being capable of shape thereon
Into bus contact, then its shape can be arbitrary shape.For example, it is also possible to be circular, rectangle.In addition, adopting in the examples described above
Connect the structure of a plurality of link slot used in a circumferential groove, but it is also possible to it is multiple using circumferential groove is divided into, outside each
Circumferential groove connects the structure of multiple link slots.
（2nd embodiment）
In the semiconductor device of the 2nd embodiment, it is further improved due to the uneven pressure reduction of groove depth.
In the semiconductor device, the flat shape of groove is different from aforesaid semiconductor device 1.
First, illustrate due to the uneven pressure reduction of groove depth.Fig. 5 is represented in semiconductor substrate 20 at equal intervals simultaneously
There is the situation of 4 grooves 70 in row（a）Situation that is lower and there is wider than a groove 70 and deep groove 71（b）Under semiconductor substrate 20
Potential distribution at interior section.With regard to this point, but in device groove side, auxiliary tank side etc. be all likewise, here auxiliary
Groove side is particularly problematic.Here, dotted line represents an equipotential line, equipotential line is presented portion jumpy in left and right directions
Point it is the part of electric-field enhancing.In addition, in Figure 5 to polysilicon layer（Polysilicon wire）The incomplete structure of 50 upsides is recorded.Such as
Shown in figure, in the situation that there is a wide and deep groove 71（b）Under, particularly form the equipotential line near the bottom of groove 71
Become steep region.Therefore, for the region for suppressing to form electric field local enhancement, the uniform depth of groove is preferably made as previously mentioned.
But, in the case where making the width of auxiliary tank 14 of aforementioned semiconductor device 1 broaden, by dry-etching shape
During grooving 10, the part of auxiliary tank 14 forms and must compare other parts（Device groove 11, circumferential groove 12, link slot 13）It is deep.Therefore, such as
Fig. 5's（b）It is shown, it is possible to form the region of electric field local enhancement, it is pressure in this region to be restricted.That is, aforementioned half
It is pressure to be likely due to the auxiliary tank 14 that broadens of local and reduce in conductor device 1.
In order to eliminate such case, other grooves are configured in the both sides of auxiliary tank more effective.The section of this construction and electricity
Bit distribution is as shown in Figure 6.Wherein, here, emphasizing that the depth difference of groove is described than actual conditions.In such configuration, exist
The both sides of wide and deep auxiliary tank 72 are formed with narrower than its and shallow electric field and relax groove 73.The void of the such as Fig. 6 of equipotential line now
Shown in line, the side equipotential line part jumpy near the bottom of auxiliary tank 72 is removed, thus does not exist
Equipotential line is presented part jumpy.That is, in the construction of Fig. 6, even if in the case of using wide and deep auxiliary tank 72,
Also the region of electric field local enhancement will not be formed, thus pressure raising.Wherein, it is not necessary to make the depth ratio of electric field mitigation groove 73 auxiliary
Help groove 72 shallow.In the case of their depth identical, can realize Fig. 5's（a）Situation, can still relax electric field collection
In, thus their depth can also be identical.
Therefore, in order to obtain above-mentioned effect, in aforesaid groove 10, formed vertically between adjacent auxiliary tank 14
The electric field that direction extends relaxes groove.Now, electric field relaxes the cross sectional shape inside groove and device groove 11, circumferential groove 12, company
Access slot 13, auxiliary tank 14 are identical.The one of the flat shape of this groove is for example shown in Fig. 7.Fig. 7 is and Fig. 1（a）（b）Accordingly
The top view of the groove is represented, Fig. 7's（a）The shaped position relation of groove and the grade of route bus 35 is represented, Fig. 7's（b）Only represent groove
Flat shape.
In this configuration, it is provided with electric field in every auxiliary tank and relaxes groove 15.Electric field relaxes groove 15 and is formed as from left and right two
Side clamps the auxiliary tank 14 to be formed that locally broadens.Therefore, such as Fig. 7（b）Shown, electric field relaxes groove 15 to be had in left side be close to auxiliary
Help the part 1 151 and the part 2 152 in the close auxiliary tank 14 in right side of groove 14.Also, have in the opposition side of circumferential groove 12
There is third portion 153, part 1 151 and part 2 152 are linked into an integrated entity by third portion 153.
It is preferred that the width that electric field relaxes groove 15 is identical with device groove 11, circumferential groove 12, link slot 13, in this case,
The narrow width of its width ratio auxiliary tank 14.Also, whole electric fields relax groove 15 and are connected with circumferential groove 12.According to this structure, show
The situation shown in Figure 16 is so realized around auxiliary tank 14.I.e., thus, the electric field of the periphery of auxiliary tank 14 is concentrated and delayed
With.Further it is evident that the groove of structure shown in Fig. 7 can be identically formed with aforesaid groove 10, and can be same in an identical manner
Sample ground forms polysilicon layer（Gate electrode）32nd, polysilicon layer（Polysilicon wire）50.
Even if in addition, simplifying the structure that electric field relaxes groove 15, adopting and eliminating the third portion 153 that electric field is relaxed in groove 15
Structure afterwards, it is clear that also can obtain relaxing the effect that electric field is concentrated.Fig. 8 is to represent this structure identically with Fig. 7（1st becomes
Shape example）Groove shape figure.In this case, compared with the structure of Fig. 7, groove entirety can be reduced, chip can be reduced
Size.
In addition, the polysilicon layer in by auxiliary tank 72（Polysilicon wire）50 are set to swim in the case of current potential, also can
Access the effect of Fig. 6.Thus, it is also possible to using making auxiliary tank 14 not become one with device groove 11, circumferential groove 12, link slot 13
The structure of body.Fig. 9 is to represent that the electric field in structure shown in Fig. 7 is relaxed into groove 15 separates identically with Fig. 7 so as to not with device groove
11st, circumferential groove 12, example when link slot 13 is integrally formed（2nd variation）Figure.Equally, Figure 10 is earth's surface identical with Fig. 7
Show the example when electric field mitigation groove 15 in structure shown in Fig. 8 is separated（3rd variation）Figure.In addition, electric field relaxes groove 15
Obviously for link slot 13 also plays identical effect, thus in the case of the overall relatively depth of link slot 13, it is also possible to form ratio
Its shallow electric field relaxes groove 15.
In above-mentioned example, electric field is set to relax the width of groove 15（Depth）Less than auxiliary tank 14, but, make theirs
In the case of width identical, as it was previously stated, can still relax electric field concentration.Accordingly it is also possible to make electric field relax the shape of groove 15
Shape is identical with auxiliary tank 14.Figure 11 represents the example that the so deformation of part 1 151, part 2 152 is made in structure shown in Fig. 7
（4th variation）.This structure is deformed, identically with the 1st variation, electric field relaxes groove 15 and is configured to only in left and right bag
Enclose the example of auxiliary tank 14（5th variation）As shown in figure 12.In addition, to structure shown in Figure 11（4th variation）Deformed,
Identically with the 2nd variation, electric field is relaxed into the detached example of groove 15（6th variation）As shown in figure 13.In addition, by Figure 12 institutes
Show structure（5th variation）In electric field relax groove 15 separate when example（7th variation）As shown in figure 14.
So, in the 2nd embodiment, it is being possible to produce the electric field concentration of the auxiliary tank to be formed that broadens due to local
In the case of, groove is relaxed by the appropriately configured electric field around auxiliary tank, the electric field can be relaxed and concentrated.Obviously can be with
1 embodiment is identically formed the groove of aforesaid any shape.That is, thus without photo-mask process is especially added, groove is only changed
Shape be capable of achieving above-mentioned construction.Therefore, it is possible to be easily manufactured above-mentioned semiconductor device.
In addition, in the overall structure of chip, only can concentrate most debatable position that electric field is set in electric field and relax groove,
Electric field need not be arranged in correspondence with whole auxiliary tanks relax groove.
Above-mentioned semiconductor device is IGBT, but, as long as the semiconductor device of the groove gate type with many bar grooves, above-mentioned
Structure is obviously exactly effective.For example, said structure is also effective in power MOSFET.
Claims (7)
1. a kind of semiconductor device, it has following structure：Respective inside being formed on the surface of semiconductor layer, there is gate electrode
A plurality of device groove, a plurality of device groove is the groove portion on the surface for extending in one direction and being formed at semiconductor layer, Duo Gesuo
State gate electrode to be connected with route bus side by side, it is characterised in that
It is formed with the surface of the semiconductor layer and obtains the integration of the device groove, circumferential groove, link slot and auxiliary tank
The groove for arriving,
The circumferential groove is the groove portion extended along the direction intersected with one direction, connects a plurality of device groove respective
One end,
The link slot is the groove portion extended along one direction, in the side for being connected with the device groove of the circumferential groove
Opposition side be connected with the circumferential groove,
The auxiliary tank is located at the end of the opposition side of the side being connected with the circumferential groove of the link slot,
In the groove obtained from by the integration of the device groove, the circumferential groove, the link slot and the auxiliary tank,
The wiring material for constituting the gate electrode is filled into into the position lower than the surface of the semiconductor layer,
Connect the wiring material and the route bus in the auxiliary tank.
2. semiconductor device according to claim 1, it is characterised in that by the device groove, circumferential groove, described
Obtained from link slot and auxiliary tank integration in the groove, link slot described in the width ratio of the auxiliary tank with prolong
Stretch the width width on the vertical direction in direction.
3. semiconductor device according to claim 2, it is characterised in that by the device groove, circumferential groove, described
Obtained from link slot and auxiliary tank integration in the groove, the interval of adjacent 2 link slots is than adjacent 2
The interval width of device groove described in bar.
4. semiconductor device according to claim 3, it is characterised in that by the device groove, circumferential groove, described
In link slot and the groove obtained from auxiliary tank integration, the link slot is in the side vertical with one direction
Do not connect the position of the device groove and the circumferential groove upwards, be connected with the circumferential groove.
5. the semiconductor device described in any one in Claims 1 to 4, it is characterised in that described in adjacent 2
Electric field is formed between auxiliary tank and relaxes groove, it is to extend along one direction and be formed at the semiconductor that the electric field relaxes groove
The surface of layer and the internal groove portion filled with the wiring material.
6. semiconductor device according to claim 5, it is characterised in that the electric field relaxes groove in the semiconductor layer
Being formed must be more shallow than the auxiliary tank and/or the link slot.
7. semiconductor device according to claim 5, it is characterised in that the electric field relaxes the vertical with bearing of trend of groove
Direction on width broaden in adjacent with auxiliary tank position local.
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| WO2016098409A1 (en) * | 2014-12-19 | 2016-06-23 | 富士電機株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| CN107210322B (en) | 2015-07-07 | 2020-11-06 | 富士电机株式会社 | Semiconductor device with a plurality of semiconductor chips |
| DE112016000210T5 (en) | 2015-07-16 | 2017-09-07 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the semiconductor device |
| US10559663B2 (en) * | 2016-10-14 | 2020-02-11 | Fuji Electric Co., Ltd. | Semiconductor device with improved current flow distribution |
| JP2018074126A (en) * | 2016-11-04 | 2018-05-10 | トヨタ自動車株式会社 | Semiconductor device |
| WO2022070304A1 (en) * | 2020-09-30 | 2022-04-07 | 三菱電機株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| CN112086517A (en) * | 2020-10-29 | 2020-12-15 | 珠海迈巨微电子有限责任公司 | Groove gate power semiconductor device and preparation method thereof |
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| DE19501556A1 (en) * | 1994-01-20 | 1995-07-27 | Mitsubishi Electric Corp | Semiconductor component with trench structure |
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| JP4048628B2 (en) * | 1999-01-05 | 2008-02-20 | 富士電機デバイステクノロジー株式会社 | Trench type MOS semiconductor device |
| US6838722B2 (en) * | 2002-03-22 | 2005-01-04 | Siliconix Incorporated | Structures of and methods of fabricating trench-gated MIS devices |
| JP4093852B2 (en) * | 2002-12-10 | 2008-06-04 | 株式会社豊田中央研究所 | Semiconductor device and manufacturing method thereof |
| JP4398185B2 (en) * | 2003-06-24 | 2010-01-13 | セイコーインスツル株式会社 | Vertical MOS transistor |
| JP2007134625A (en) * | 2005-11-14 | 2007-05-31 | Mitsubishi Electric Corp | Semiconductor device and its process for fabrication |
| JP2008085278A (en) * | 2006-09-29 | 2008-04-10 | Ricoh Co Ltd | Semiconductor device and manufacturing method thereof |
| US7989887B2 (en) * | 2009-11-20 | 2011-08-02 | Force Mos Technology Co., Ltd. | Trench MOSFET with trenched floating gates as termination |
| US20110233605A1 (en) * | 2010-03-26 | 2011-09-29 | Force Mos Technology Co. Ltd. | Semiconductor power device layout for stress reduction |
| JP5775268B2 (en) * | 2010-06-09 | 2015-09-09 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
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| DE19501556A1 (en) * | 1994-01-20 | 1995-07-27 | Mitsubishi Electric Corp | Semiconductor component with trench structure |
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