CN104009071A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN104009071A CN104009071A CN201310454662.1A CN201310454662A CN104009071A CN 104009071 A CN104009071 A CN 104009071A CN 201310454662 A CN201310454662 A CN 201310454662A CN 104009071 A CN104009071 A CN 104009071A
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- groove
- auxiliary tank
- semiconductor device
- circumferential groove
- link slot
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 93
- 230000005684 electric field Effects 0.000 claims description 44
- 230000000116 mitigating effect Effects 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 106
- 229920005591 polysilicon Polymers 0.000 abstract description 106
- 238000004519 manufacturing process Methods 0.000 abstract description 12
- 230000002093 peripheral effect Effects 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 127
- 239000011229 interlayer Substances 0.000 description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 238000000034 method Methods 0.000 description 10
- 238000001312 dry etching Methods 0.000 description 7
- 230000009467 reduction Effects 0.000 description 6
- 230000009471 action Effects 0.000 description 5
- 239000012141 concentrate Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000008719 thickening Effects 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Thyristors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a semiconductor device. In a groove gate-shaped semiconductor device, a pressureproof structure can be realized in a simple manufacturing method. A groove (10) is provided with a connecting groove (13) which extends to an upper side (an end side of a chip or an opposite side of a device groove (11)) from a peripheral groove (12). The end of an opposite side of one side of the peripheral groove (12) connected to the connecting groove (13) is provided with an auxiliary groove (14) which is oval and has a short shaft wider than the connecting groove (13). A total lie contact point (511) is formed right above the auxiliary groove (14), and accordingly a total line wiring (35) and a polysilicon layer (polysilicon wiring) are connected in the auxiliary groove (14).
Description
Technical field
The present invention relates to semiconductor device, relate in particular to the structure that can carry out with large electric current the semiconductor device of switch motion.
Background technology
In recent years, can be used as switch element with the power MOSFET of large driven current density (Metal Oxide Semiconductor Field Effect Transistor: metal-oxide semiconductor (MOS)), igbt (Insulated Gate Bipolar Transistor, hereinafter to be referred as making IGBT).
In this power semiconductor, according to the conduction and cut-off of gate voltage control action electric current.In power MOSFET, this operating current refers to the electric current between source-leakage, in IGBT, also carries out the action of bipolar transistor except carrying out the action identical with power MOSFET simultaneously, and this operating current flows through at emitter-inter-collector.
In the IGBT of groove grid (trench gate) type, form many slot parts (trench) on the surface of semiconductor layer, in slot part, form gate insulating film, polysilicon layer as gate electrode, the inner surface of each groove plays a role as MOSFET.The each gate electrode corresponding with each slot part connects side by side, and is connected with route bus.Route bus is for gate electrode being executed to alive wiring in the time moving.Figure 15 is the vertical view of observing from above that schematically represents an example of the structure of the groove in the IGBT of groove gate type.In the figure, the flat shape of groove and the relation of route bus are schematically shown.
In Figure 15 (a), the polysilicon wire in groove 80 and route bus 35 position relationship and groove 80 in the plane and the connecting portion of route bus 35 are the position relationship of bus contact 911.
In the flat shape of groove 80 shown in (b) of Figure 15.Groove 80 is made up of with the circumferential groove 82 that upper direction is connected these device grooves and left and right directions extends in the drawings in the drawings 7 device grooves 81 that above-below direction extends in the drawings, and these grooves are integrated.Each device groove 81 extends abreast towards the end of chip (upside in figure), and circumferential groove 82 is designed to that device groove 81 is vertical is connected with these in the end side of chip.
Shown in (c) of Figure 15 the inside of groove 80 and around the flat shape of the polysilicon layer 32,90 that forms.As described later, at this, polysilicon layer 32 is the polysilicon layers in device groove 81.Therefore, the flat shape of polysilicon layer 32 is roughly consistent with the flat shape of device groove 81.On the other hand, polysilicon layer 90 is circumferential groove 82 and polysilicon layer around thereof, and larger than circumferential groove 82.These polysilicon layers are integrated in groove 80, and adulterate in the mode that improves conductivity, thereby play a role as wiring.
Position relationship at polysilicon layer 90 shown in (d) of Figure 15 with bus contact 911, as shown in Figure 15 (a), is connected polysilicon layer 90 at the position of bus contact 911 with route bus 35.In addition, in Figure 15 (a), omit the description of the polysilicon layer 32 in the device groove 81 irrelevant with bus contact 911.
Below, the cross section of the C-C direction in use Figure 15 (a) illustrates in greater detail this structure.Figure 16 is the figure that represents this cross section.At this, for convenient, in device groove 81 sides, the cross section of the left and right directions in Figure 15 is shown, in circumferential groove 82 sides, the cross section of the above-below direction in Figure 15 is shown, the single-point line in Figure 16 represents the position of the vertical curve of C-C.As shown in figure 16, groove 80(device groove 81, circumferential groove 82) be formed as the surface perforation p layer 21 from semiconductor layer 20, this semiconductor layer 20 has p layer (basalis) 21, n in face side
-layer 22, n
+layer 23.N
-22, layer is formed at a side with device groove 81, thereby the lower end of device groove 81 arrives n
-layer 22, the lower end of circumferential groove 82 arrives n
+layer 23.Wherein, the width of device groove 81 (width of the left and right directions in Figure 15 (b)) is identical with the width (width of the above-below direction in Figure 15 (b)) of circumferential groove 82.In addition, in fact at n
+the downside of layer 23 is formed with collector layer or collector electrode etc., still, omits the record about them in Figure 16.
As shown in figure 16, across thinner gate insulating film 31, in device groove 81, be formed with polysilicon layer (gate electrode) 32 in device groove 81, circumferential groove 82 inside, in circumferential groove 82, be formed with polysilicon layer (polysilicon wire) 90.Polysilicon layer (gate electrode) 32, polysilicon layer (polysilicon wire) 90 are formed as across thinner gate insulating film 31 landfill device groove 81, circumferential groove 82 respectively.
Wherein, be formed with the n as the source region of MOSFET in the both sides of device groove 81
+layer 24.Therefore, in device groove 81, by controlling polysilicon layer (gate electrode) 32 current potential, n that can control device groove 81 inner side
+layer 24 and n
-the conduction and cut-off of the raceway groove in the p layer 21 between layer 22.
And, be formed with a side of device groove 81, at whole p layers 21 and n
+layer 24 is formed with the emitter 33 being formed by aluminium etc.Wherein, polysilicon layer (gate electrode) 32 insulate by interlayer insulating film 34 and emitter 33.According to this structure, by the current potential of control grid electrode 32, can be controlled at emitter 33 and be positioned at the conduction and cut-off of the electric current flowing through between the collector electrode (not shown) of downside.
On the other hand, in circumferential groove 82, owing to not forming n
+layer 24, thereby do not carry out this action.But as shown in figure 15, because device groove 81 and circumferential groove 82 are connected, thereby in fact polysilicon layer (polysilicon wire) 90 in polysilicon layer (gate electrode) 32 and circumferential groove 82 in each device groove 81 is integrated., circumferential groove 82 is for the polysilicon layer (gate electrode) 32 corresponding with many device grooves 81 connected side by side, and it is connected and is formed with route bus 35.At this, as shown in figure 16, the not only landfill circumferential groove 82 of polysilicon layer (polysilicon wire) 90 in circumferential groove 82, and expand to around it, the right side of the circumferential groove 82 in Figure 16 is connected with route bus 35.Route bus 35 utilizes the material identical with emitter 33 to form, equally by insulation such as interlayer insulating film 91,92 and p layers 21.Therefore, go out bus contact 911 at interlayer insulating film 91 openings.Groove 80(device groove 81 shown in Figure 15, circumferential groove 82), polysilicon layer (polysilicon wire) 33, bus contact 911 and route bus 35 position relationship in the plane.
According to this structure, can pass through polysilicon layer (polysilicon wire) 90 and connect multiple polysilicon layers (gate electrode) 32, control the current potential of whole polysilicon layers (gate electrode) 32 by route bus 35.
(a) of Figure 17 (b), Figure 18 (c) (d), Figure 19 (e) represent to form the polysilicon layer (gate electrode) 32 in above-mentioned structure, the operation sectional view of polysilicon layer (polysilicon wire) manufacturing process of 90 o'clock.At this, the cross section relevant with device groove 81, circumferential groove 82 position separately in Figure 16 is shown.
First, as shown in Figure 17 (a), form device groove 81, circumferential groove 82 by dry-etching on the surface of semiconductor layer 20, then form gate insulating film 31.Now, form shown in (b) of Figure 15 by the photoresist pattern of the shape of opening grooving 80, by carrying out dry-etching, form device groove 81, circumferential groove 82 simultaneously.Now, if the width of device groove 81, circumferential groove 82 is identical, also identical dry-etching of the degree of depth that easily makes them.And, by thermal oxidation, in the inside of established device groove 81, circumferential groove 82, also can form even and thinner gate insulating film 31.
Then,, as shown in Figure 17 (b), when forming after interlayer dielectric 92 in circumferential groove 82 sides, utilize the even and thicker polysilicon layers 40 of formation such as CVD method.Thus, the inside of device groove 81, circumferential groove 82 is filled by polysilicon layer 40, and whole surface is also covered by polysilicon layer 40.
Then, as shown in Figure 18 (c), with the shape of the polysilicon layer (polysilicon wire) 90 shown in (c) of Figure 15 accordingly, form the photoresist layer 100 that covers the region that comprises circumferential groove 82.Now, do not form photoresist layer 100 in device groove 81 sides.
Then, be formed with under the state of photoresist layer 100, carrying out the dry-etching (eat-backing) of polysilicon layer 40.Thus, except being formed with the position of photoresist layer 100, the polysilicon layer 40 on surface is uniformly removed, and finally obtains the shape shown in (d) of Figure 18.Then, by removing photoresist layer 100, as shown in Figure 19 (e), form polysilicon layer (gate electrode) 32 in device groove 81 sides, form polysilicon layer (polysilicon wire) 90 in circumferential groove 82 sides.The polysilicon layer (gate electrode) 32 of device groove 81 sides only remains in the inside of device groove 81.Then, on whole, form insulating barrier and carry out composition, form thus interlayer insulating film 34,91.Now, also form the bus contact 911 in interlayer insulating film 91.
, can easily utilize the method shown in Figure 17～19 to manufacture above-mentioned structure.
But there is the problem points of following explanation in above-mentioned structure.
Figure 20 schematically amplifies to represent in the shape after eat-backing (Figure 19 (e)), to use the figure in the region of dotted line.In the figure, the structure of the upper end of circumferential groove 82 is exaggerated expression.As mentioned above, gate insulating film 31 forms by thermal oxidation, and is evenly and is formed on device groove 81, circumferential groove 82 inside compared with unfertile land.But, be also formed uniformly gate insulating film 31 in the bight of surperficial device groove 81, circumferential groove 82, be actually very difficult, as shown in figure 20, in their bight, gate insulating film 31 is conventionally thin than other region.Therefore, the polysilicon layer (polysilicon wire) 90 at the bight place on circumferential groove 82 surfaces and semiconductor layer 20(p layer 21) between withstand voltage reduction.On the other hand, as shown in Figure 18 (d), in device groove 81 sides, in its bight, polysilicon layer 40 is removed by eat-backing, and, as shown in figure 16, this part is covered by interlayer insulating film 34 later, therefore, even if gate insulating film 31 is in bight attenuation, the dielectric voltage withstand in this region can not become problem yet.On the other hand, in the structure shown in Figure 15,16, for the arranged outside bus contact 911 in circumferential groove 82, polysilicon layer (polysilicon wire) 90 is certain for this bight.
,, in above-mentioned structure, the withstand voltage and original action of the grid of IGBT or power MOSFET is irrelevant, the restriction of the gate insulating film 31 in the circumferential groove 82 that is subject to arranging in order to connect.If make the thickness entirety thickening of gate insulating film 31, although it withstand voltagely obviously improves, in order to carry out good switch motion, need to make gate insulating film 31 attenuation in device groove 81.
Therefore, for example in patent documentation 1, record the structure of the local thickening of gate insulating film at the bight place that makes circumferential groove surface.In addition, in patent documentation 2, record following structure: do not use circumferential groove, by increasing the terminal part of device groove, eliminate the uneven thickness of the gate insulating film at this bight place, and take out polysilicon wire from this terminal part.
[patent documentation 1] Japanese kokai publication hei 07-249769 communique
[patent documentation 2] TOHKEMY 2000-200901 communique
But in the technology of recording at patent documentation 1, it is complicated that manufacturing process obviously becomes.
In addition, in the technology of recording at patent documentation 2, although can improve the uneven thickness of the gate insulating film at groove angle portion place,, make the thickness of the gate insulating film in the groove of this cross sectional shape completely even, be actually very difficult.On the other hand, in this technology, on the gate insulating film that is formed at this bight, form polysilicon wire, this point does not change.Therefore, adopt this technology to be also difficult to substantially improve withstand voltage.
,, in the semiconductor device (IGBT, power MOSFET) of groove gate type, be difficult to utilize simple manufacture method to realize and can obtain enough withstand voltage structure.
Summary of the invention
The present invention proposes just in view of the above problems, and its object is, the invention addressing the above problem is provided.
The present invention adopts the structure of the following stated to solve the problems referred to above.
Semiconductor device of the present invention has following structure: many device grooves that form inside separately on the surface of semiconductor layer and have gate electrode, these many device grooves are the surperficial slot parts that are formed at semiconductor layer along a direction extension, multiple described gate electrodes are connected with route bus side by side, it is characterized in that, be formed with on the surface of described semiconductor layer described device groove, circumferential groove, integrated and the groove that obtains of link slot and auxiliary tank, described circumferential groove is the slot part along the direction extension intersecting with a described direction, connect described many device grooves one end separately, described link slot is the slot part extending along a described direction, opposition side in a side of the described device groove of being connected with of described circumferential groove is connected with described circumferential groove, described auxiliary tank is located at the end of the opposition side of the side being connected with described circumferential groove of described link slot, in described groove, the wiring material that forms described gate electrode is filled into the position lower than the surface of described semiconductor layer, in described auxiliary tank, connect described wiring material and described route bus.
Semiconductor device of the present invention is characterised in that, in described groove, the width of described auxiliary tank is wider than the width in the direction vertical with bearing of trend of described link slot.
Semiconductor device of the present invention is characterised in that, in described groove, the interval of 2 adjacent described link slots is wider than the interval of 2 adjacent described device grooves.
Semiconductor device of the present invention is characterised in that, in described groove, described link slot is not connected the position of described device groove and described circumferential groove in the direction vertical with a described direction, is connected with described circumferential groove.
Semiconductor device of the present invention is characterised in that, between 2 adjacent described auxiliary tanks, be formed with electric field and relax groove, it is surface and the inner slot part that is filled with described wiring material that is formed at described semiconductor layer along described direction extension that this electric field relaxes groove.
Semiconductor device of the present invention is characterised in that, described electric field relaxes groove and in described semiconductor layer, forms more shallowly than described auxiliary tank and/or described link slot.
Semiconductor device of the present invention is characterised in that, the width that described electric field relaxes in the direction vertical with bearing of trend of groove broadens in the part, position adjacent with described auxiliary tank.
The present invention forms as mentioned above, thereby in the semiconductor device of groove gate type, can utilize simple manufacture method to realize and can obtain enough withstand voltage structure.
Brief description of the drawings
Fig. 1 is the vertical view that is illustrated in the flat shape of the groove periphery using in the semiconductor device of the 1st execution mode of the present invention.
Fig. 2 is the sectional view of the A-A direction of the semiconductor device of the 1st execution mode of the present invention.
Fig. 3 is the sectional view of the B-B direction of the semiconductor device of the 1st execution mode of the present invention.
Fig. 4 is another the routine vertical view that is illustrated in the flat shape of the groove periphery using in the semiconductor device of the 1st execution mode of the present invention.
Fig. 5 is the figure that schematically represents the Potential distribution in the semiconductor layer of groove bottom.
Fig. 6 is the figure of the Potential distribution in the semiconductor layer being schematically illustrated in while using electric field relaxation layer.
Fig. 7 is the vertical view that is illustrated in the flat shape of the groove periphery using in the semiconductor device of the 2nd execution mode of the present invention.
Fig. 8 is the vertical view that is illustrated in the flat shape of the 1st variation periphery of the groove using in the semiconductor device of the 2nd execution mode of the present invention.
Fig. 9 is the vertical view that is illustrated in the flat shape of the 2nd variation periphery of the groove using in the semiconductor device of the 2nd execution mode of the present invention.
Figure 10 is the vertical view that is illustrated in the flat shape of the 3rd variation periphery of the groove using in the semiconductor device of the 2nd execution mode of the present invention.
Figure 11 is the vertical view that is illustrated in the flat shape of the 4th variation periphery of the groove using in the semiconductor device of the 2nd execution mode of the present invention.
Figure 12 is the vertical view that is illustrated in the flat shape of the 5th variation periphery of the groove using in the semiconductor device of the 2nd execution mode of the present invention.
Figure 13 is the vertical view that is illustrated in the flat shape of the 6th variation periphery of the groove using in the semiconductor device of the 2nd execution mode of the present invention.
Figure 14 is the vertical view that is illustrated in the flat shape of the 7th variation periphery of the groove using in the semiconductor device of the 2nd execution mode of the present invention.
Figure 15 is the vertical view that is illustrated in the flat shape of the groove periphery using in semiconductor device in the past.
Figure 16 is the sectional view of the C-C direction of semiconductor device in the past.
Figure 17 be the operation sectional view that represents the manufacture method of semiconductor device in the past (one of).
Figure 18 is the operation sectional view that represents the manufacture method of semiconductor device in the past (two).
Figure 19 is the operation sectional view that represents the manufacture method of semiconductor device in the past (three).
Figure 20 is the sectional view that amplifies the structure of the circumferential groove upper end that represents semiconductor device in the past.
Label declaration
1 semiconductor device (IGBT); 10,70,71,80 grooves; 11,81 device grooves; 12,82 circumferential groove; 13 link slots; 14,72 auxiliary tanks; 15,73 electric fields relax groove; 20 semiconductor layers; 21p layer (basalis: semiconductor layer); 22n
-layer (semiconductor layer); 23n
+layer (semiconductor layer); 24n
+layer (source region); 31 gate insulating films; 32 polysilicon layers (gate electrode); 33 emitters; 34,51,91,92 interlayer insulating films; 35 route bus; 40 polysilicon layers; 50,90 polysilicon layers (polysilicon wire); 100 photoresist layers; 151 part 1s; 152 part 2s; 153 the 3rd parts; 511,911 bus contact.
Embodiment
The semiconductor device of embodiments of the present invention is described below.This semiconductor device is the semiconductor element of controlling the conduction and cut-off of electric current by the conduction and cut-off of grid-control raceway groove processed.And, being formed with the multiple slot parts (device groove) that extend in parallel along a direction, gate electrode is located in each device groove.Each gate electrode is connected with route bus side by side in the end side of chip.With the example of Figure 15 in the same manner, except device groove, be also provided with the circumferential groove for gate electrode is connected side by side, device groove and circumferential groove groove integrated and that obtain are formed to the surface of semiconductor layer.
(the 1st execution mode)
The semiconductor device of the 1st execution mode of the present invention is described below.This semiconductor device is IGBT.Fig. 1 is the shape that schematically represents groove 10 and the route bus 35 etc. of this semiconductor device 1, the vertical view of position relationship.In addition, Fig. 2, Fig. 3 are the A-A direction of this semiconductor device 1, the sectional view of B-B direction.
Fig. 1 is corresponding to Figure 15, at groove 10 shown in (a) of Fig. 1, route bus 35, the flat shape of bus contact 511, position relationship.
As shown in Fig. 1 (b), 7 device grooves 11 that are formed on that groove 10 in this semiconductor device 1 is also provided with that above-below direction (direction) in the drawings extends and the upper end (one end) in these figure are connected also the circumferential groove 12 of left and right directions in the drawings (direction of intersecting with a direction) extension with these device grooves 11.This point is identical with the structure of Figure 15.The inside of device groove 10 and the structure being adjacent are also identical.The semiconductor layer 20, the gate insulating film 31 etc. that, use are identical with the structure of Figure 15, Figure 16.The shape of polysilicon layer (gate electrode) 32, interlayer insulating film 34 etc. in device groove 11 is also identical.In addition, preferably the width (width of the above-below direction in Fig. 1) of circumferential groove 12 and the width (width of the left and right directions in Fig. 1) of device groove 11 equate.
Wherein, in this groove 10, be also provided with link slot 13, this link slot 13 extends towards upside (opposition side of the end side of chip or device groove 11) more from circumferential groove 12.Preferably link slot 13 is parallel with device groove 11, and its width (width of the left and right directions in Fig. 1) is identical with device groove 11.And, suppose that the connecting portion of link slot 13 and circumferential groove 12 is different from the connecting portion of device groove 11 and circumferential groove 12.Therefore, in the flat shape (Fig. 1 (b)) of this groove 10, be formed with road junction footpath and do not form four footpaths, branch road (becoming the part of cross shape).Therefore, link slot 13 is between 2 adjacent device grooves 11, and extend the opposition side from circumferential groove 12 to these 2 device grooves 11.And, there are three device grooves 11 in the opposition side across circumferential groove 12 in the gap of 2 adjacent link slots 13., the interval of 2 adjacent link slots 13 is configured to wider than the interval of 2 adjacent device grooves 11.
End in the opposition side of the side being connected with circumferential groove 12 of link slot 13 is formed with auxiliary tank 14, and this auxiliary tank 14 is oval-shaped, and its minor axis is wider than link slot 13.Auxiliary tank 14 becomes a part for link slot 13.
In circumferential groove 12, link slot 13, auxiliary tank 14, be also formed with polysilicon layer (polysilicon wire) 50.But the cross sectional shape of polysilicon layer (polysilicon wire) 50 is now different from aforesaid polysilicon layer (polysilicon wire) 90, be only formed at the inside of these grooves.This point is equally applicable to the polysilicon layer (gate electrode) 32 in device groove 11.Therefore, polysilicon layer (polysilicon wire) 50 and polysilicon layer (gate electrode) 32 are integrated, and this point is identical with the structure of Figure 15, and still, polysilicon layer 32,50 is all the inside that is only formed at groove 10, and the structure of this point and Figure 15 differs widely.Therefore, the flat shape of polysilicon layer 32,50 is roughly the same with the flat shape of groove 10 as shown in Fig. 1 (c).
In addition, as shown in Figure 2 and Figure 3, surround auxiliary tank 14 and formation interlayer insulating film 51, go out bus contact 511 in interlayer insulating film 51 upper sheds.Route bus 35 is connected by bus contact 511 with polysilicon layer (polysilicon wire) 50.As shown in Fig. 1 (d), bus contact 511 is formed in auxiliary tank 14 and is less than auxiliary tank 14 in the time overlooking.
In this structure, bus contact 511 be formed at auxiliary tank 14 directly over, thereby route bus 35 and polysilicon layer (polysilicon wire) 50 are in the interior connection of auxiliary tank 14.Therefore, do not need, as the polysilicon layer in the structure of Figure 15 (polysilicon wire) 90, polysilicon layer (polysilicon wire) 50 to be extended to groove 10(circumferential groove 12, link slot 13, auxiliary tank 14) outside.Due to bus contact 511 is located in auxiliary tank 14, thereby only at the interior formation polysilicon layer of auxiliary tank 14 (polysilicon wire) 50.
Therefore, do not need to form photoresist layer 100 and polysilicon layer (polysilicon wire) 50 is carried out to composition the manufacture method shown in Figure 17～19.As long as form above-mentioned groove 10, just can with device groove 11 in polysilicon layer (gate electrode) 32 in the same manner by eat-backing to form the polysilicon layer (polysilicon wire) 50 of structure shown in Fig. 2., do not need to use photoresist layer 100 in Figure 18 can form the structure described in Fig. 1～Fig. 3.Therefore, do not need to be used to form the photo-mask process of photoresist layer 100.
In addition, in this case, owing to not needing to use photoresist layer 100 can carry out eat-backing of polysilicon layer, thereby this situation while eat-backing does not change in device groove 11 sides, circumferential groove 12 sides, link slot 13 sides, auxiliary tank 14 sides.Therefore, in this case, as shown in Figure 2 and Figure 3, polysilicon layer (gate electrode) 32 in its cross section and device groove 11 in the same manner, polysilicon layer (polysilicon wire) 50 only remains in the inside of circumferential groove 12, link slot 13, auxiliary tank 14, can make it lower than the bight of circumferential groove 12, link slot 13, auxiliary tank 14 (surface of semiconductor layer 20) topmost.Therefore, even in the case of the local attenuation of gate insulating film 31 at the bight place of the circumferential groove 12 on semiconductor layer 20 surfaces, link slot 13, auxiliary tank 14, the gate insulating film 31 of this attenuation also can not contact with polysilicon layer (polysilicon wire) 50, forms the interlayer insulating film 51 shown in Fig. 2, Fig. 3 at this position.As shown in Figure 2, this structure with in device groove 11, be same.Therefore, even in the case of the local attenuation of gate insulating film 31 at the bight place of auxiliary tank 14, polysilicon layer (polysilicon wire) 50 and semiconductor layer 20(p layer 21) between withstand voltagely also can not reduce.
That is, in this semiconductor device 1, can obtain enough withstand voltagely, and can utilize simple manufacture method to obtain this semiconductor device 1.
In addition, in said structure, make the width of device groove 11, circumferential groove 12, link slot 13 identical, make the width (width of the left and right directions in Fig. 1: oval-shaped minor axis) of auxiliary tank 14 wider than this width.This is for by the area that increases bus contact 511, reduces the contact resistance between polysilicon layer (polysilicon wire) 50 and route bus 35.This structure makes the interval between link slot 13 wider than the interval between device groove 11, thereby can easily realize.In addition, according to this structure, also easily realize the opening (dry-etching of interlayer insulating film 51) that is formed on the bus contact 511 on auxiliary tank 14.
In addition, also can when the interval that makes link slot 13 is identical with device groove 11, auxiliary tank 14 be broadened.(a) of Fig. 4 represents groove, route bus 35, the flat shape of bus contact 511, position relationship now, and (b) of Fig. 4 only illustrates the flat shape of groove.This figure correspond respectively to Fig. 1's (a) (b).In this structure, between 2 adjacent device grooves 11, from circumferential groove 12, extend to form link slot 13 in the opposition side of device groove 11.Be provided with auxiliary tank 14 at the end of each link slot 13, still, the distance (length of link slot 13) between auxiliary tank 14 and circumferential groove 12 is configured to according to adjacent auxiliary tank 14 and is different.In the structure of Fig. 4, this distance is configured to three kinds of distances.According to this structure, even increase the area of single bus contact 511 in the case of auxiliary tank 14 broadens, also can increase sum, the gross area of bus contact 511.Therefore, can further reduce the resistance between route bus 35 and polysilicon layer (polysilicon wire) 50.
In said structure, adopt dry-etching in order to form groove 10 at semiconductor layer 20, still, now normally fast in the region of etching speed wider width in groove 10.Therefore, conventionally exist the position of wider width in groove 10 to deepen, the position tendency more shallow than the position of wider width that width is narrower.As described later, even so also there is the situation of withstand voltage reduction, thereby preferably make the width of device groove 11, circumferential groove 12, link slot 13 identical.In addition, in above-mentioned example, the width of auxiliary tank 14 is wider than this width, still, also can make the width of auxiliary tank 14 identical with their width.In this case, the end of link slot self becomes in fact auxiliary tank.In this case, bus contact is less than this width, still, as long as can make the contact resistance of this part enough little, also can adopt this structure.
In addition, as previously mentioned, the connecting portion of link slot 13 and circumferential groove 12 is different from the connecting portion of device groove 11 and circumferential groove 12, thereby in the flat shape of this groove 10, forms road junction footpath and do not form four footpaths, branch road.This is that width broadens in fact on the diagonal of its crossover sites in order to be suppressed in the situation that has formed four footpaths, branch road, and restrain tank 10 deepens or etching shape defect in this part.But, result from this part withstand voltage reduction with result from compared with the withstand voltage reduction of gate insulating film of aforementioned attenuation in negligible situation, also can in groove 10, form four footpaths, branch road.
In addition, in above-mentioned structure, the flat shape of auxiliary tank is made as to ellipse, still, as long as can form bus contact thereon, its shape can be arbitrary shape.For example, can be also circular, rectangle.In addition, in above-mentioned example, adopt the structure that connects many link slots circumferential groove, still, also can adopt circumferential groove to be divided into multiple, connect the structure of multiple link slots in each circumferential groove.
(the 2nd execution mode)
In the semiconductor device of the 2nd execution mode, the withstand voltage reduction of groove depth inequality of resulting from is further improved.In this semiconductor device, the flat shape of groove is different from aforesaid semiconductor device 1.
First, illustrate and result from the withstand voltage reduction of groove depth inequality.Fig. 5 is illustrated in semiconductor substrate 20 and exists side by side the situation (a) of 4 grooves 70 to descend and exist the Potential distribution of the section in the semiconductor substrate 20 in the situation (b) of a groove 71 wide and darker than groove 70 with equal intervals.About this point, be all same in device groove side, auxiliary tank side etc., still, especially become problem in this auxiliary tank side.At this, dotted line represents an equipotential line, and it is the part that electric field strengthens that equipotential line presents part jumpy at left and right directions.In addition, in Fig. 5, the incomplete structure of polysilicon layer (polysilicon wire) 50 upsides is recorded.As shown in the figure, exist in the situation (b) of a wide and dark groove 71, be formed with especially near the high region of equipotential line steepening, bottom of groove 71.Therefore,, in order to suppress to form the region of electric field local enhancement, preferably make as previously mentioned the degree of depth of groove even.
But in the case of making the width of auxiliary tank 14 of aforementioned semiconductor device 1 broadens, in the time forming groove 10 by dry-etching, the part of auxiliary tank 14 forms deeplyer than other parts (device groove 11, circumferential groove 12, link slot 13).Therefore, as shown in Fig. 5 (b), likely form the region of electric field local enhancement, withstand voltage being restricted in this region.,, in aforementioned semiconductor device 1, the withstand voltage auxiliary tank 14 likely broadening due to part reduces.
In order to eliminate this situation, configure other groove in the both sides of auxiliary tank more effective.The cross section of this structure and Potential distribution are as shown in Figure 6.Wherein, at this, emphasize that than actual conditions the depth difference of groove is described.In this structure, be formed with in the both sides of wide and dark auxiliary tank 72 than its narrow and shallow electric field and relax groove 73.Equipotential line is now as shown in the dotted line of Fig. 6, and near the side equipotential line part jumpy bottom of auxiliary tank 72 is removed, thereby does not exist equipotential line to present part jumpy.That is, in the structure of Fig. 6, even in the case of using wide and dark auxiliary tank 72, also can not form the region of electric field local enhancement, thereby withstand voltage raising.Wherein, do not need to make the depth ratio auxiliary tank 72 of electric field mitigation groove 73 shallow.In the case of their degree of depth is identical, can realize the situation of Fig. 5 (a), still can relax electric field and concentrate, thereby their degree of depth also can be identical.
Therefore,, in order to obtain above-mentioned effect, in aforesaid groove 10, between adjacent auxiliary tank 14, form the electric field extending along the vertical direction and relax groove.Now, to relax cross sectional shape and device groove 11, circumferential groove 12, link slot 13, the auxiliary tank 14 of groove inside identical for electric field.One example of the flat shape of this groove as shown in Figure 7.Fig. 7 and Fig. 1 (a) (b) represent the vertical view of this groove accordingly, and (a) of Fig. 7 represents the shaped position relation of groove and route bus 35 etc., and (b) of Fig. 7 only represents the flat shape of groove.
In this structure, be provided with electric field at every auxiliary tank and relax groove 15.Electric field relaxes groove 15 and is formed as from the local auxiliary tank 14 that broadens and form of left and right sides clamping.Therefore,, as shown in Fig. 7 (b), electric field relaxes groove 15 and has the part 1 151 that approaches auxiliary tank 14 in left side and the part 2 152 that approaches auxiliary tank 14 on right side.And, thering is the 3rd part 153 in the opposition side of circumferential groove 12, part 1 151 and part 2 152 link into an integrated entity by the 3rd part 153.
The width that preferably electric field relaxes groove 15 and device groove 11, circumferential groove 12, link slot 13 are identical, and in this case, its width is narrower than the width of auxiliary tank 14.And all electric field mitigation groove 15 is connected with circumferential groove 12.According to this structure, obviously around auxiliary tank 14, realize the situation shown in Figure 16., thus, the electric field of auxiliary tank 14 peripheries is concentrated and is relaxed.In addition, obviously can be identically formed with aforesaid groove 10 groove of structure shown in Fig. 7, and can similarly form in an identical manner polysilicon layer (gate electrode) 32, polysilicon layer (polysilicon wire) 50.
In addition, even if simplify the structure of electric field mitigation groove 15, adopt the structure after the 3rd part 153 of having removed in electric field mitigation groove 15, obviously also can obtain relaxing the concentrated effect of electric field.Fig. 8 is the figure that represents in the same manner the shape of the groove of this structure (the 1st variation) with Fig. 7.In this case, compared with the structure of Fig. 7, groove entirety can be reduced, chip size can be reduced.
In addition, in the case of the polysilicon layer in auxiliary tank 72 (polysilicon wire) 50 is made as and is swum current potential, also can obtain the effect of Fig. 6.Therefore, also can adopt the structure that auxiliary tank 14 is not become one with device groove 11, circumferential groove 12, link slot 13.Fig. 9 represents that the electric field in structure shown in Fig. 7 is relaxed to groove 15 to be separated, the figure of the example (the 2nd variation) when it is not become one with device groove 11, circumferential groove 12, link slot 13 in the same manner with Fig. 7.Equally, Figure 10 is the figure of the example (the 3rd variation) while representing in the same manner electric field in structure shown in Fig. 8 to relax groove 15 and separate with Fig. 7.In addition, electric field relaxes groove 15 and obviously also brings into play identical effect for link slot 13, thereby, also can form than its shallow electric field mitigation groove 15 darker in the situation that in link slot 13 entirety.
In above-mentioned example, make electric field relax the width (degree of depth) of groove 15 and be less than auxiliary tank 14, still, in the case of make their width identical, as previously mentioned, still can relax electric field and concentrate.Therefore, also can make the shape of electric field mitigation groove 15 identical with auxiliary tank 14.Figure 11 is illustrated in the example (the 4th variation) that makes part 1 151, part 2 152 be out of shape like this in structure shown in Fig. 7.This structure is out of shape, with the 1st variation in the same manner, electric field relax groove 15 be only configured to surround auxiliary tank 14 in left and right example (the 5th variation) as shown in figure 12.In addition, structure shown in Figure 11 (the 4th variation) is out of shape, with the 2nd variation in the same manner, electric field is relaxed to example (the 6th variation) that groove 15 separates as shown in figure 13.In addition, the example (the 7th variation) when the electric field mitigation groove 15 in structure shown in Figure 12 (the 5th variation) separation as shown in figure 14.
Like this, in the 2nd execution mode, in the case of likely produce result from part broaden the electric field of auxiliary tank that forms concentrated, relax groove by suitably configure electric field around auxiliary tank, can relax this electric field and concentrate.Obviously can be identically formed with the 1st execution mode the groove of aforesaid any shape.That is, do not need thus to append especially photo-mask process, the shape that only changes groove can realize above-mentioned structure.Therefore, can easily manufacture above-mentioned semiconductor device.
In addition, in the structure of chip entirety, can only concentrate the most debatable position that electric field is set at electric field and relax groove, not need, with whole auxiliary tanks, electric field is set accordingly and relax groove.
Above-mentioned semiconductor device is IGBT, and still, as long as having the semiconductor device of groove gate type of many grooves, said structure is exactly obviously effective.For example, in power MOSFET, said structure is also effective.
Claims (7)
1. a semiconductor device, it has following structure: many device grooves that form inside separately on the surface of semiconductor layer and have gate electrode, these many device grooves are the surperficial slot parts that are formed at semiconductor layer along a direction extension, multiple described gate electrodes are connected with route bus side by side, it is characterized in that
Be formed with on the surface of described semiconductor layer groove integrated to described device groove, circumferential groove, link slot and auxiliary tank and that obtain,
Described circumferential groove is along the slot part of the direction extension intersecting with a described direction, connects described many device grooves one end separately,
Described link slot is the slot part extending along described direction, is connected with described circumferential groove in the opposition side of a side of the described device groove of being connected with of described circumferential groove,
Described auxiliary tank is located at the end of the opposition side of the side being connected with described circumferential groove of described link slot,
In described groove, the wiring material that forms described gate electrode is filled into the position lower than the surface of described semiconductor layer,
In described auxiliary tank, connect described wiring material and described route bus.
2. semiconductor device according to claim 1, is characterized in that, in described groove, the width of described auxiliary tank is wider than the width in the direction vertical with bearing of trend of described link slot.
3. semiconductor device according to claim 2, is characterized in that, in described groove, the interval of 2 adjacent described link slots is wider than the interval of 2 adjacent described device grooves.
4. semiconductor device according to claim 3, is characterized in that, in described groove, described link slot is not connected the position of described device groove and described circumferential groove in the direction vertical with a described direction, is connected with described circumferential groove.
5. according to the semiconductor device described in any one in claim 1～4, it is characterized in that, between 2 adjacent described auxiliary tanks, be formed with electric field and relax groove, it is surface and the inner slot part that is filled with described wiring material that is formed at described semiconductor layer along described direction extension that this electric field relaxes groove.
6. semiconductor device according to claim 5, is characterized in that, described electric field relaxes groove and in described semiconductor layer, forms more shallowly than described auxiliary tank and/or described link slot.
7. according to the semiconductor device described in claim 5 or 6, it is characterized in that, the width in the direction vertical with bearing of trend of described electric field mitigation groove broadens in the part, position adjacent with described auxiliary tank.
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| CN105702654A (en) * | 2014-12-16 | 2016-06-22 | 英飞凌科技美国公司 | Power FET Having Reduced Gate Resistance |
| CN106463524A (en) * | 2014-12-19 | 2017-02-22 | 富士电机株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| CN107958906A (en) * | 2016-10-14 | 2018-04-24 | 富士电机株式会社 | Semiconductor device |
| CN112086517A (en) * | 2020-10-29 | 2020-12-15 | 珠海迈巨微电子有限责任公司 | Groove gate power semiconductor device and preparation method thereof |
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| JP6477885B2 (en) | 2015-07-16 | 2019-03-06 | 富士電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| JP2018074126A (en) * | 2016-11-04 | 2018-05-10 | トヨタ自動車株式会社 | Semiconductor device |
| CN116325175A (en) * | 2020-09-30 | 2023-06-23 | 三菱电机株式会社 | Semiconductor device and method for manufacturing semiconductor device |
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