CN103997393A - Reconfigurable OFDM signal-to-noise-ratio strengthen system based on FPGA - Google Patents
Reconfigurable OFDM signal-to-noise-ratio strengthen system based on FPGA Download PDFInfo
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- CN103997393A CN103997393A CN201410243251.2A CN201410243251A CN103997393A CN 103997393 A CN103997393 A CN 103997393A CN 201410243251 A CN201410243251 A CN 201410243251A CN 103997393 A CN103997393 A CN 103997393A
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Abstract
The invention relates to a reconfigurable OFDM signal-to-noise-ratio strengthen system based on an FPGA. The reconfigurable OFDM signal-to-noise-ratio strengthen system based on the FPGA comprises a transmitting terminal and a receiving terminal. The transmitting terminal comprises a clock generation module, a long and short sequence generation module, a fast Fourier inversion transform module and a cyclic prefix and peak windowing processing module. The clock generation module is used for generating a clock signal. The long and short sequence generation module is used for forming a long training sequence and a short training sequence. The fast Fourier inversion transform module is used for calling IP core implementation provided by the FPGA. The cyclic prefix and peak windowing processing module processes the cyclic prefix according to the method that after the fast Fourier inversion transform sample value is worked out, the cyclic prefix is added before the sample value to form a cyclic OFDM signal. According to peak windowing processing, a non-linear rectangular window function is selected to be multiplied by a signal. According to the system, the FPGA is adopted, an ASIC circuit does not need to be designed, integration and reliability of the system can be improved, and implementation cost and difficulty can be reduced.
Description
Technical field
The present invention relates to wireless communication technology field, particularly relate to a kind of based on the reconfigurable OFDM signal to noise ratio enhancing of FPGA system.
Background technology
Along with the develop rapidly of the communication technology, the efficiency of transmission problem of data becomes especially outstanding.The update of radio communication is exactly in fact continuing to optimize and improving of transmission rate and efficiency.Orthogonal frequency division multiplexi OFDM (Orthogonal FrequencyDivisionMultiplexing) has shown the using value that it is important just in this process.
OFDM is a kind of method of simultaneously transmitting data, uses Fourier's modulation and demodulation conversion process in a plurality of parallel carrier frequencies.OFDM provides a lot of advantages to multicarrier high data rate transfers, particularly in mobile communication application.Therefore, ofdm system is becoming a key technology and is being widely deployed in the wireless communication system of broadband access, as WLAN (wireless local area network), digital audio and digital video broadcasting, wireless network, WiMAX and LTE etc.
Constantly soaring to the demand of information rate and efficiency, domestic consumer urgently wishes to obtain the information flow-rate service of more convenient high speed, requires data access more easily, higher message transmission rate.Therefore the key of problem is to select suitable modulation technique and mode.OFDM technology has slowly become the optimal solution in wireless communication transmission.
Although there are these advantages, ofdm system also has some drawbacks, as peak-to-average power ratio (PAPR) and subcarrier synchronous.Papr problem is a ubiquitous problem in multicarrier modulation system, the key factor that Zhe Yeshi equipment vendors consider.Because it is very high that the too high meeting of PAPR makes transmitting terminal require the linearity of power amplifier, this just means the size that excess power, battery backup will be provided and expand equipment, and then increases the cost of base station and subscriber equipment.
A kind of special circumstances as multi-carrier modulation.Ofdm signal is comprised of a plurality of sub-carrier signals, these sub-carrier signals are by different modulation symbol separate modulation, although the phase place of each subcarrier is separate, but when subcarrier number increases, if each sub-carrier signal is regarded as to the random cosine signal of phase place, it is indefinite that the ofdm signal envelope that all sub-carrier signal stacks obtain will rise and fall, and inevitably produce many higher peak values, cause signal peak-to-average power power ratio very high.
High PAPR value requires power amplifier to be operated under high-power compensating coefficient on the one hand, and this is low especially by the efficiency of power amplifier, thereby has improved greatly the cost of transmitter; On the other hand, because mobile terminal energy is very limited, thereby require efficient power amplification.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of based on the reconfigurable OFDM signal to noise ratio enhancing of FPGA system, with reducing peak-to-average power ratio (PAPR) value, improves system signal noise ratio, reduction realizes simultaneously difficulty and complexity.
The technical solution adopted for the present invention to solve the technical problems is: provide a kind of and strengthen system based on the reconfigurable OFDM signal to noise ratio of FPGA, comprise transmitting terminal and receiving terminal, described transmitting terminal is divided into some sequences by initial data, and modulate different subcarriers, utilizing fully under the prerequisite of frequency resource, a plurality of subcarriers are stacked up and launched; Described receiving terminal recovers a plurality of carrier waves, and by the data demodulates of each subcarrier out, described transmitting terminal comprises clock generating module, length sequence generation module, inverse fast Fourier transform module and Cyclic Prefix and peak window processing module; Described clock generating module is for generated clock signal; Described length sequence generation module is used to form long training sequence and short training sequence; The IP kernel that described inverse fast Fourier transform module is called FPGA to be provided is realized; In described Cyclic Prefix and peak window processing module, circulation prefix processing is for after calculating invert fast fourier transformation sample value, a Cyclic Prefix is added to before sample value, form the ofdm signal of a circulation, peak window is treated to selects nonlinear rectangular window function and signal to multiply each other.
Described transmitting terminal also comprises data symbol modulation module, and described data symbol modulation module is dissolved into 16QAM modulation in Signal Pretreatment, and independently two-way baseband signal is modulated simultaneously.
Described receiving terminal is set a sampling clock value, gives up data, according to closing on the approximate compensation that data complete deviation when calculating when the phase deviation of pilot tone is greater than sampling clock value.
Described short training sequence is used for carrying out input, and automatic gain is controlled, Symbol Timing and coarse frequency estimation of deviation; Described long training sequence is for accurate frequency offset estimation and channel estimating.
The high-performance clock administration module generated clock signal that described clock generating module provides with FPGA.
Beneficial effect
Owing to having adopted above-mentioned technical scheme, the present invention compared with prior art, there is following advantage and good effect: the present invention adopts very important part FPGA (Field-ProgrammableGateArray), i.e. field programmable gate array in EDA technology.Because its inside has abundant functional module and logic module resource, therefore no longer need ASIC design circuit, again because there is abundant I/O pin its inside, thereby can improve level of integrated system and reliability.Therefore the Base-Band Processing of ofdm system being designed in single low and middle-end fpga chip and realize, reduced the cost and the difficulty that realize, is the fusion of EDA technology and wireless communication technology.
Accompanying drawing explanation
Fig. 1 is OFDM baseband system block architecture diagram;
Fig. 2 is ofdm system block diagram.
Embodiment
Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiment are only not used in and limit the scope of the invention for the present invention is described.In addition should be understood that those skilled in the art can make various changes or modifications the present invention after having read the content of the present invention's instruction, these equivalent form of values fall within the application's appended claims limited range equally.
The ofdm system of the present invention's design adopts a plurality of carrier waves and a plurality of channel at transmitting terminal, initial data is divided into some sequences, and modulates different subcarriers, utilizing fully under the prerequisite of frequency resource, a plurality of subcarriers is stacked up and is launched.Receiving terminal recovers a plurality of carrier waves, and by the data demodulates of each subcarrier out.Whole system block diagram as shown in Figure 2.
Transmitting terminal agent structure is divided into digital processing part and modulating part, and system is processed into another kind of data flow output by raw digital signal, and whole modulated process is considered as a procedure function.The process of design ofdm system realizes letter transformation of variable.Process and the transmitting terminal of receiving terminal are similar, carry out the phase inverse operation of process.
The following describes specific implementation method of the present invention, as shown in Figure 1, be divided into two large modules of transmitting terminal and receiving terminal and show, due to receiving terminal and transmitting terminal similar, be the reverse process of transmitting terminal, so more detailed to the explanation of transmitting terminal.
One, transmitting terminal part
The signal of whole transmitting terminal is processed primary module and is comprised clock generating module, length sequence generation module, data symbol modulation module, IFFT module, Cyclic Prefix and peak window processing module.
(1) clock generating module:
The ofdm system of the present invention design is that this all has high requirements for cycle, duty ratio, time delay and shake of controlling clock based on the synchronizing sequential circuit of edging trigger all the time mostly.In order to improve clock signal quality, the high-performance clock administration module (DCM) that the present invention provides with FPGA generates clock signal, has improved the quality of clock signal, again for design is provided convenience.
(2) length sequence generation module:
The main application of short training sequence is to carry out input, and automatic gain is controlled (AGC), Symbol Timing and coarse frequency estimation of deviation.Long training sequence is mainly used in accurate frequency offset estimation and channel estimating.
Length training sequence generation module adopts the Base-Band Processing clock of 20MHz, reset signal is a reset signal of Low level effective, the control signal STS_ACK sending here from MCU is used for starting module and starts working, STS_ACK can continue to draw high 161 clocks, in fact STS_ACK is exactly the enable signal of module work, 16 time domain sample values of module one-period are stored in the interior ROM of sheet, the address signal of ROM has the counter of a mould 16 to generate, when STS_ACK is while being high, the address control signal generating is controlled ROM 16 module sample values of wherein storage is repeated to read 10 cycles, form the short training sequence of prescribed by standard.The generation method of long training sequence and the generation method of short training sequence are similar, in the sheet of short training sequence, ROM is 16 word * 16, in the sheet of long training sequence, ROM is set to 64 word * 16, while reading, by the sample value of the control of ReadAddrsee first being exported in rear 32 address spaces, form CP, then the sample value in whole ROM repeats to read twice in order, thereby forms whole long training sequence.
(3) data symbol modulation module---16QAM
According to different rate requirement, the subcarrier of ofdm system needs different modulation system, in the present invention, will use 16QAM modulation, compares with other modulation techniques, can obtain higher spectrum efficiency, and noise resisting ability is also stronger.QAM is a kind of amplitude and phase combining keying, two kinds of signals is convergeed to the modulator approach of a channel.By two-way baseband signal independently, to mutually orthogonal two, with carrier waves frequently, carry out amplitude modulation, utilize the orthogonality in same bandwidth, realize the transmission of the parallel digital information of two-way.The amplitude of signal and phase place as two independently parameter modulated simultaneously, reduced to a great extent the error rate.
(4) inverse fast Fourier transform IFFT
IFFT/FFT is the core of whole system, is related to the correctness of whole system algorithm.In order to guarantee the accuracy of operation result, the ofdm system of the present invention's design completes the IP kernel that directly calls FPGA inside the realization of IFFT/FFT module.
(5) Cyclic Prefix
In the present invention's design, add Cyclic Prefix technology and can effectively solve symbol-interference and interchannel interference problem.Concrete methods of realizing is, after calculating invert fast fourier transformation sample value, a Cyclic Prefix is added to before sample value, forms the ofdm signal of a circulation, can effectively solve the interference problem between subcarrier.
(6) peak window is processed
It is the optimization of direct margining amplitude technique that peak window is processed, and in direct margining amplitude technique, the signal amplitude that is greater than threshold value, by reduction by force, has brought larger band and out-of-band noise.Key modules of the present invention is exactly to reduce the module of ofdm system PAPR value, and the method for the reduction PAPR value that the present invention selects is that peak window is processed, and the method had both realized simply, effective again.Concrete methods of realizing is to select nonlinear rectangular window function and signal to multiply each other, and can reduce PAPR value, can reduce noise again.
Be not difficult to find, FPGA can provide hardware necessity speed and stability, and the large scale investment of using without the huge front-end fee of similar customed ASIC design.FPGA utilizes the parallel advantage of hardware, has broken the pattern of sequentially carrying out, and completes more Processing tasks within each clock cycle, and abundant input and output (I/O) provide response time and specialized function faster for meeting application demand.FPGA is not used operating system, has real executed in parallel and the certainty hardware of being absorbed in each task, has greatly improved its stability.
Two, receiving terminal part
Process and the transmitting terminal of receiving terminal are similar, comprise that synchronously, Cyclic Prefix is removed, FFT, subcarrier demodulation part.Owing to being synchronously all vital part in the design of any communication system, the design of receiving terminal, except to contrary processing of data radiating portion, focuses on the synchronous and demodulation of input.
Receiving terminal constantly carries out the detection of signal at one's leisure, to have judged whether that signal arrives.After arrival, receive the related operation of signal and Short Training symbol, complete frame and detect and sign synchronization.Even if there is again high precision and algorithm for design, deviation between cancellation receiver and transmitter completely, and then cause the deviation in FFT cycle, thus there is the interference of interchannel.Solution is to set a sampling clock value, gives up data, according to closing on the approximate compensation that data complete deviation when calculating when the phase deviation of pilot tone is greater than sampling clock.Processing has deviation certainly like this, thereby systematic function is exerted an influence, but has reduced like this complexity of using and realizing of hardware, has improved the arithmetic speed of algorithm.
As can be seen here, the present invention utilizes ripe field programmable gate technology, take the inner abundant functional module of FPGA and logic module resource as basis, complete the design to ofdm system, SOC (system on a chip) is connected by system high-speed bus with control chip module, saves internal resource and simplifies circuit design.
Claims (5)
1. one kind strengthens system based on the reconfigurable OFDM signal to noise ratio of FPGA, comprise transmitting terminal and receiving terminal, described transmitting terminal is divided into some sequences by initial data, and modulates different subcarriers, utilizing fully under the prerequisite of frequency resource, a plurality of subcarriers are stacked up and launched; Described receiving terminal recovers a plurality of carrier waves, and by the data demodulates of each subcarrier out, it is characterized in that, described transmitting terminal comprises clock generating module, length sequence generation module, inverse fast Fourier transform module and Cyclic Prefix and peak window processing module; Described clock generating module is for generated clock signal; Described length sequence generation module is used to form long training sequence and short training sequence; The IP kernel that described inverse fast Fourier transform module is called FPGA to be provided is realized; In described Cyclic Prefix and peak window processing module, circulation prefix processing is for after calculating invert fast fourier transformation sample value, a Cyclic Prefix is added to before sample value, form the ofdm signal of a circulation, peak window is treated to selects nonlinear rectangular window function and signal to multiply each other.
2. according to claim 1 based on the reconfigurable OFDM signal to noise ratio enhancing of FPGA system, it is characterized in that, described transmitting terminal also comprises data symbol modulation module, described data symbol modulation module is dissolved into 16QAM modulation in Signal Pretreatment, and independently two-way baseband signal is modulated simultaneously.
3. according to claim 1 based on the reconfigurable OFDM signal to noise ratio enhancing of FPGA system, it is characterized in that, described receiving terminal is set a sampling clock value, gives up data, according to closing on the approximate compensation that data complete deviation when calculating when the phase deviation of pilot tone is greater than sampling clock value.
4. according to claim 1ly based on the reconfigurable OFDM signal to noise ratio of FPGA, strengthen system, it is characterized in that, described short training sequence is used for carrying out input, and automatic gain is controlled, Symbol Timing and coarse frequency estimation of deviation; Described long training sequence is for accurate frequency offset estimation and channel estimating.
5. according to claim 1 based on the reconfigurable OFDM signal to noise ratio enhancing of FPGA system, it is characterized in that the high-performance clock administration module generated clock signal that described clock generating module provides with FPGA.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108768908A (en) * | 2018-06-07 | 2018-11-06 | 重庆大学 | A kind of expansible lightweight OFDM system design method based on FPGA |
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Application publication date: 20140820 |