CN203039714U - A high efficient MIMO-OFDM wireless communication system - Google Patents
A high efficient MIMO-OFDM wireless communication system Download PDFInfo
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Abstract
The utility model belongs to the field of communication systems and discloses a high efficient MIMO-OFDM wireless communication system. A multi-antenna transmitter and a multi-antenna receiver are established on a FPGA and a radio frequency platform of the system. The transmitter comprises a radio-frequency emitting part and a base-band data processing FPGA. The FPGA comprises various encoders, a pilot frequency interposer, an IFFT converter, and a training sequence generator. The receiver comprises a radio-frequency receiving part and a base-band data processing FPGA. The FPGA comprises various synchronizers and compensators, a FFT converter, and various decoders. The transmission rate of the system may reach more than 54Mbps and the theoretic transmission rate of the system may reach 216 Mbps. The high efficient MIMO-OFDM wireless communication system provides a transmission scheme with high rate for 4G and wireless local area networks, substantially overcomes channel fading, and reduces code error rate. The high efficient MIMO-OFDM wireless communication system based on programmable hardware has characteristics of high portability, easy upgrading, and a small size.
Description
Technical field
The utility model relates to field of wireless communications, more specifically, relates to the wireless communication system of a kind of efficient MIMO-OFDM.
Background technology
Be accompanied by the continuous development of RFDC and multimedia application, wireless transmitting system also correspondingly improves constantly the requirement of aspects such as transmission rate and QoS assurance.Wherein as the key technology in the 4th third-generation mobile communication, OFDM (OFDM) and multiple-input, multiple-output (MIMO) just more and more are subjected to people's attention in novel physical layer transmission technology.OFDM can resist the multidiameter delay expansion effectively and eliminate intersymbol interference (ISI), and the availability of frequency spectrum satisfies the requirement of needs physical layer data high-speed transfer in the communication near the Nyquist limit, reduces the error rate.And MIMO can effectively utilize or alleviate multipath fading, eliminates altogether that the road disturbs, and can promote the rate of information throughput exponentially than SISO under the condition that does not increase bandwidth.Therefore the wireless communication system of realizing an efficient MIMO-OFDM with OFDM and MIMO technology in the communication of a new generation is necessary.
The difficult point that realizes OFDM and MIMO technology is, design a suitable emission and detection algorithm, keep each subcarrier to satisfy the orthogonality of frequency, avoid frequency departure to cause and disturb (ICI) and higher peak-to-average power to cause signal distortion than (PAPR) between subcarrier.
Summary of the invention
In order to overcome the deficiencies in the prior art, the utility model proposes the wireless communication system of a kind of efficient MIMO-OFDM, the utlity model has characteristics such as high transfer rate, high spectrum utilization, low channel fading, low error rate, antijamming capability are strong.
To achieve these goals, the technical solution of the utility model is:
The wireless communication system of a kind of MIMO-OFDM comprises MCU, transmitter and receiver, and MCU controls transmitter and receiver;
Described transmitter comprises the first base band data processing section and the radio-frequency transmissions part that connects in turn, and the described first base band data processing section comprises first module and second module; The output of described first module connects the input of second module and the input of radio-frequency transmissions part respectively;
Described first module comprises scrambler, channel encoder, interleaver, QAM mapper, pilot tone inserter, IFFT converter and windowing and the prefix maker that connects in turn; Described second module is the training sequence maker; Described radio-frequency transmissions comprises that partly AD converter, IQ modulator, gain controller, the height of connection are put device and reflector in turn;
Described receiver comprises radio frequency receiving unit and the second base band data processing section, and described radio frequency receiving unit comprises receiver, LNA device, IQ demodulator, DA transducer and the AFC clock recovery that connects in turn; Another input of output termination IQ demodulator of AFC clock recovery; The described second base band data processing section comprises packet detector, carrier synchronization device, symbol synchronizer, CP remover, FFT converter, channel equalizer, sample frequency synchronizer, excess phase tracker, QAM de-mapping device, deinterleaver, channel decoder and the descrambler that connects in turn; Wherein the output of carrier synchronization device also connects the input of excess phase tracker, and channel equalizer also connects the QAM de-mapping device;
The input of the output termination packet detector of described DA transducer.
Adopt the first base band data processing section that the data of input are handled, partly send wireless signal by radio-frequency transmissions then; The radio frequency receiving unit receives wireless signal, and this wireless signal is input to the second base band data processing section handles.Wherein the characteristics of the first base band data processing section are that transmitting terminal Additional Preamble signal is the length training sequence, use windowing prefixing and multiple coding techniques, make it have high-transmission efficient, high spectrum utilization, low channel fading, low error rate, antijamming capability strong; The characteristics of the second base band data processing section be carry out multiple synchronously and compensation guarantee that the subcarrier that receives satisfies orthogonality, and correct error code during decoding, greatly reduced the error rate, strengthened antijamming capability.
Further, described reflector is transmitting antenna.
Further, carry out at FPGA described first and second base band data processing section.
Further, described scrambler comprises parallel-to-serial converter and the scrambler that connects in turn, and the parallel physical layer protocol cell data that is used for importing is serial data, forms the scrambler of serial output then;
Described channel encoder comprises convolution code maker, 2/3 rate convolutional code maker, the 3/4 rate convolutional code maker of 1/2 code check, and wherein the output of the convolution code maker of 1/2 code check selects to be connected to the input of 2/3 rate convolutional code maker, 3/4 rate convolutional code maker under the control of MCU;
Described interleaver comprises the one-level interleaver of being made up of write address maker, mould 384 counters, the first twoport block RAM and the secondary interleaver of being made up of read/write address maker, mould 24 counters, the second twoport block RAM, wherein write address maker and mould 384 counters are the write-read address input end of the first twoport block RAM in the one-level interleaver, the output of the first twoport block RAM is connecting the second twoport block RAM of secondary interleaver, and the read/write address of the second twoport block RAM of secondary interleaver is provided by the read/write address maker of mould 24 counter controls;
Described QAM mapper is the 16QAM modulator;
Described pilot tone inserter comprises first scrambler, look-up table, mould 64 counters and the 3rd twoport block RAM composition, wherein first scrambler is controlled by MCU, its output is controlled the data input pin of the 3rd twoport block RAM, and the read/write address of the 3rd twoport block RAM is provided by mould 64 counters and look-up table;
Described training sequence maker comprises that based on the short training sequence maker of IEEE802.11 standard and long training sequence maker wherein the output of the output of short training sequence maker and long training sequence maker is by MCU control output.
Further, described packet detector comprises cache module, master control module, postpones correlation energy computing module, correlation window energy computing module and frame search module, wherein cache module is connecting the input that postpones correlation energy computing module and correlation window energy computing module under the control of master control module, and postpone the correlation energy computing module is being connected the frame search module with the output of correlation window energy computing module input, the frame search module provides and feeds back signal to the master control module;
Described carrier synchronization device comprises data distribution module, Nonlinear Transformation in Frequency Offset Estimation module, data cache module, carrier wave frequency deviation compensating module and data aggregate output module, wherein three of the data distribution module outputs are carried the input of ripple frequency deviation estimating modules, data cache module and carrier wave frequency deviation compensating module respectively, the output of Nonlinear Transformation in Frequency Offset Estimation module is connecting another input of carrier wave frequency deviation compensating module, and data cache module is being connected the input of data aggregate output module with the output of carrier wave frequency deviation compensating module;
Described symbol synchronizer comprises quantization modules, matched filtering module and the symbol output module that connects in turn;
Described channel equalizer comprises long training symbol extraction module, energy computing module, channel estimation block, channel compensation block, wherein the output of long training symbol extraction module is connecting the input of energy computing module, channel estimation block and channel compensation block respectively, and the output of channel estimation block is connecting another input of channel compensation block, and the energy output of energy computing module is connected to the input of QAM de-mapping device;
Described sample frequency synchronizer comprises pilot extraction module, data cache module, pilot tone correlation module, frequency deviation estimating modules, compensate of frequency deviation module and order adjusting module, wherein pilot extraction module, data cache module, compensate of frequency deviation module and order adjusting module are connected in turn, the pilot tone output termination pilot tone correlation module of described pilot extraction module, the correlation output termination frequency deviation estimating modules of pilot tone correlation module, the input of the output termination compensate of frequency deviation module of the angle output of frequency deviation estimating modules and pilot tone buffer memory;
Described excess phase tracker comprises pilot extraction module, data cache module, Phase Tracking compensating factor computing module and excess phase compensating module, wherein pilot extraction module, data cache module and excess phase compensating module are connected in turn, and described pilot extraction module also connects the excess phase compensating module by Phase Tracking compensating factor computing module;
Described QAM de-mapping device comprises decision threshold adjusting module, data cache module and the 16QAM demodulation module that connects in turn, the input of the output termination decision threshold adjusting module of the energy computing module of channel equalizer wherein, the input of the output termination 16QAM demodulation module of the output of the energy computing module of channel equalizer and excess phase tracker;
Described channel decoder adopts Viterbi decoder, comprise that Hamming distance computing module, ACS module, minimum value select module, path memory module, survival RAM and path to recall module, wherein Hamming distance computing module, ACS module, minimum value selection module are recalled module with the path and are connected in turn, the input of the output termination path memory module of ACS module, the path memory module is received survival RAM, and the path memory module is received the path and recalled module.
Compared with prior art, of the present utility model have a following beneficial effect: wireless communication system of the present utility model is based on 802.11, utilize OFDM, MIMO, multiple encoding and decoding technique, synchronously and alignment technique build; Adding targeting signal at transmitter is the length training sequence, uses windowing prefixing and multiple coding techniques; And receiver carry out multiple synchronously and compensation guarantee that the subcarrier that receives satisfies orthogonality, and correct error code during decoding, greatly reduced the error rate, strengthened antijamming capability.Have characteristics such as high transfer rate, high spectrum utilization, low channel fading, low error rate, antijamming capability are strong.
Description of drawings
Fig. 1 is the structural representation of transmitter of the present utility model.
Fig. 2 is the structural representation of receiver of the present utility model.
Fig. 3 is the structural representation of scrambler of the present utility model.
Fig. 4 is the structural representation of channel encoder of the present utility model.
Fig. 5 is the structural representation of interleaver of the present utility model.
Fig. 6 is the structural representation of pilot tone inserter of the present utility model.
Fig. 7 is the structural representation of IFFT converter of the present utility model.
Fig. 8 is the structural representation of training sequence maker of the present utility model.
Fig. 9 is the structural representation of packet detector of the present utility model.
Figure 10 is the structural representation of carrier synchronization device of the present utility model.
Figure 11 is the structural representation of symbol synchronizer of the present utility model.
Figure 12 is the structural representation of channel equalizer of the present utility model.
Figure 13 is the structural representation of sample frequency synchronizer of the present utility model.
Figure 14 is the structural representation of excess phase tracker of the present utility model.
Figure 15 is the structural representation of QAM de-mapping device of the present utility model.
Figure 16 is the structural representation of Viterbi decoder of the present utility model.
Specific embodiment
Below in conjunction with accompanying drawing the utility model is described further, but execution mode of the present utility model is not limited to this.OFDM is based on the IEEE802.11 standard: number of subcarriers is 52, and pilot number is that 4, OFDM symbol lengths is 4us, and protection is spaced apart 800ns, and subcarrier spacing is 312.5kHz, and signal bandwidth is 16.66MHz, and channel spacing is 20MHz.
As shown in Figure 1, transmitter 1 comprises the first base band data processing section and the radio-frequency transmissions part that connects in turn, and the described first base band data processing section comprises first module and second module; The output of described first module connects the input of second module and the input of radio-frequency transmissions part respectively;
Described first module comprises scrambler 3, channel encoder 4, interleaver 5, QAM mapper 6, pilot tone inserter 7, IFFT converter 8 and windowing and the prefix maker 9 that connects in turn; Described second module is training sequence maker 10; Described radio-frequency transmissions comprises that partly AD converter 11, IQ modulator 12, gain controller, the height of connection are put device and reflector in turn;
As shown in Figure 2, described receiver comprises radio frequency receiving unit and the second base band data processing section, and described radio frequency receiving unit comprises receiver, LNA device, IQ demodulator 13, DA transducer 14 and the AFC clock recovery that connects in turn; Output termination IQ demodulator 13 another inputs of AFC clock recovery; The described second base band data processing section comprises packet detector 15, carrier synchronization device 16, symbol synchronizer 17, CP remover 18, FFT converter 19, channel equalizer 20, sample frequency synchronizer 21, excess phase tracker 22, QAM de-mapping device 23, deinterleaver 24, channel decoder 25 and the descrambler 26 that connects in turn; Wherein the output of carrier synchronization device 16 also connects the input of excess phase tracker 22, and channel equalizer 20 also connects QAM de-mapping device 23;
The input of the output termination packet detector 15 of described DA transducer 14.
In this example, the operation of transmitter is as follows:
(101) scrambler 3: comprise the parallel-to-serial converter 111 and the scrambler 112 that connect in turn, as shown in Figure 3;
At first, the parallel physical layer data of parallel-to-serial converter 111 control input converts serial data to, is characterized in LSB preceding, MSB after.Then, scrambler 112 scrambled data generated frequencies are the scrambler data of 60MHz.Make it have the statistical property of approximate white noise.
(102) channel encoder 4: the convolution code maker 121,2/3 rate convolutional code maker, the 3/4 rate convolutional code maker that comprise 1/2 code check, wherein the output of the convolution code maker 121 of 1/2 code check selects to be connected to the input of 2/3 rate convolutional code maker, 3/4 rate convolutional code maker under the control of MCU, as shown in Figure 4;
(103) interleaver 5: comprise by the write address maker, mould 384 counters, the one-level interleaver 131 that the first twoport block RAM is formed and by the read/write address maker, mould 24 counters, the secondary interleaver 132 that the second twoport block RAM is formed, wherein write address maker and mould 384 counters are the write-read address input end of the first twoport block RAM in the one-level interleaver 131, the output of the first twoport block RAM is connecting the second twoport block RAM of secondary interleaver 132, the read/write address of the second twoport block RAM of secondary interleaver 132 is provided by the read/write address maker of mould 24 counter controls, as shown in Figure 5.
One-level interleaver 131 uses calibrated bolck to interweave, and the result of counter is as the address of reading of the first twoport block RAM; The degree of depth of the first twoport block RAM is 2 times of interleave depth, realizes pile line operation with this.The characteristics of one-level interleaver 131 be write address out of order, read sequence of addresses.Secondary interleaver 132, deinterleaving method are to be a unit with 24 bits, and preceding 12 orders are constant, back 12 every adjacent two switches, and wherein, the generation of the read/write address of the second twoport block RAM is provided respectively by two mould 24 counters.
(104) QAM mapper 6:QAM mapper 6 is the 16QAM modulator,
(105) the pilot tone inserter 7: comprise first scrambler 141, look-up table 142, mould 64 counters 143 and the 3rd twoport block RAM 144 compositions, wherein first scrambler 141 is controlled by MCU, its output is controlled the data input pin of the 3rd twoport block RAM 144, and the read/write address of the 3rd twoport block RAM 144 is provided by mould 64 counters 143 and look-up table 142, as shown in Figure 6;
At first, at specific first scrambler 141, the polarity of these first scrambler, 141 controls, four tunnel pilot tones.
Then, by the IQ two paths of data that mapping obtains, eight groups of data of every Lu Sishi, 8 bit wides of every group of data, frequency is 20MHz.4 tunnel pilot signal IQ two-way correspond to 43,57,7,21 of IFFT64 input port under look-up table 142 and 143 controls of mould 64 counters, and 48 road I/Q data after the mapping correspond to 38 to 63 and 1 to 26 of IFFT64 input port, and all the other IFFT input ports put 0.
(106) the IFFT converter 8:, as shown in Figure 7,
The carrier wave and the zero carrier that insert pilot tone constitute 64 way carrier waves, carry out conversion in IFFT converter 8.
The utility model has improved the speed of IFFT conversion.At first, elder generation heightens the frequency of the data of input and is 60MHz.Then, realize the IFFT conversion of the Radix-4 of input data at the IFFT converter.At last, read data after the conversion according to the clock of 20MHz.
(107) windowing and prefix maker 9:
At first, control two degree of depth and be writing and reading of 64 RAM, wherein deposit the data of IFFT converter 8 outputs.The former frame data are during from first RAM output, and it is 64 RAM that back one frame data just can deposit second degree of depth in, realization pile line operation.Data prefixing to the output of IFFT converter, formed an OFDM symbol, its generation type is: deposit preceding 48 data of 64 tunnel IFFT data of importing in one of them RAM, since the 49th data, deposit this RAM on the one hand in, on the one hand directly output.Import this RAM to the 64th data and finish, from this RAM, call over 64 data.Characteristics are the effects with anti-symbol-interference and channel disturbance.
At last, the OFDM symbol is carried out windowing, be about to one of last data shift right, make the range value at symbol period edge carry out the transition to zero gradually, make the power spectral density of OFDM outside bandwidth descend sooner.
(108) the training sequence maker 10: comprise short training sequence maker 161 and long training sequence maker 162 based on the IEEE802.11 standard, wherein the output of the output of short training sequence maker 161 and long training sequence maker 162 is by MCU control output, as shown in Figure 8.
(109) radio-frequency transmissions part:
At first, DA transducer 11 converts the base band data after FPGA handles to analogue data.Then, IQ modulator 12 is loaded into the I/Q two paths of data on the carrier wave.Then carry out height and put, launch finally by antenna.
MCU control data send, and control is output short training sequence symbol earlier, exports the long training sequence symbol again, exports a plurality of OFDM symbols again.Data are sent into the radio frequency platform emission of building transmitter in the first base band data processing section.
In the present embodiment, the operation of receiver is as follows:
(201) radio frequency receiving unit:
At first, the data that receive are carried out LNA.Then, IQ demodulator 13 becomes the I/Q two-way with data demodulates.Then, DA transducer 14 converts analogue data to digital signal.At last, the control figure signal enters the base band data processing platform.
(202) in packet detector 15: whether have new data to arrive on the channel of detection burst transfer mode.
At first, data are sent into cache module 211,16 groups of data are equivalent to a Short Training symbol carry out buffer memory, buffer memory is 16 grades and 48 grades respectively.
Then, postponing correlation energy computing module 213 multiplies each other data in buffer one by one with the data of arrival and carries out correlation computations, utilizes sliding window to calculate relevantly to add up, utilize the amplitude simplification to ask for absolute value.Simultaneously, correlation window energy computing module 214 will be imported data and be correlated with, and comprise that energy calculates i.e. relevant, energy accumulation, data buffer memory.
In frame search module 215, delay correlation energy result calculated and correlation window energy result calculated are divided by and are obtained at last
, if less than threshold value T, then valid data do not arrive, and then export data if having.As shown in Figure 9.
(203) the carrier synchronization device 16: compensation is because the incomplete same frequency departure that causes of Doppler frequency shift and transmitting-receiving crystal oscillator is determined the orthogonality between subcarrier.As shown in figure 10.
The novel carrier synchronization of this example has adopted the time domain mode, need not calculate the DFT of two replicators, thereby has saved amount of calculation, and because it finishes all very short times that only need synchronously in leading time, comparing other receiver has certain advantage.
At first, use data distribution module 221, the data of input are shunted, wherein 5 Short Training symbols are sent to carrier frequency offset estimator, long training symbol and OFDM data symbol are sent into the carrier wave frequency deviation compensator, and all Short Training symbols are sent into data buffer simultaneously.
Then, carrier wave frequency deviation is estimated module 222 to data postpone to be correlated with, correlated results adds up, estimation of deviation obtains frequency deviation phase value.
Then, at carrier wave frequency deviation compensating module 224, then carry out the compensate of frequency deviation factor by this phase value and calculate, the result multiply by long training symbol and the OFDM data symbol compensates.The Short Training data of the data aggregate buffer memory after compensation output at last.
(204) symbol synchronizer 17 and CP remover 18: the precise time of trying to achieve single OFDM sign-on and end.
At first, simplify, quantize in 231 pairs of data of quantization modules, namely greater than 0 be quantized into 1, less than 0 be quantized into-1.
Then, carry out the filtering coupling at matched filter 232.Data after quantizing are correlated with and are added up, accumulation result is carried out the amplitude simplification, seeks peak value.Adopt above-mentioned shortcut calculation to carry out when adding up.
At last, remove CP and output symbol by symbol output module 233.
(205) the FFT converter 19: operate opposite with transmitting terminal.Still adopt the method for high frequency FFT conversion.
(206) channel equalizer 20: eliminate amplitude and phase effect that each sub-carrier channels is introduced.
At first, data obtain two long training symbols through long training symbol extraction module 241; Then, carry out channel estimating in channel estimation block 243; Then, adopt energy computing module 242 to carry out energy and calculate, adopt channel compensation block 244 to carry out channel compensation simultaneously; Output at last.
(207) the sample frequency synchronizer 21: it is synchronous to carry out sample frequency, revises the deviation between both sampling intervals that the device for sending and receiving crystal oscillator produces.
(208) the excess phase tracker 22: carry out tracking and the compensation of excess phase, proofread and correct carrier wave frequency deviation and proofread and correct the phase deviation that data remaining deviation in back causes.
(209) the QAM de-mapping device 23.
(210) deinterleaver 24 is used for process information is carried out twice deinterleaving.
(211) channel decoder 25 is used for deconvolution,
At first, when the convolutional encoding of 2 parallel-by-bits was carried out decoder, Hamming distance computing module 281 calculated 64 groups, every group 2 Hamming distance value according to input data and current state.
Then, two adder calculating path branch's distances of ACS module 282 design and previous moment cumulative distance sum, select again cumulative distance and smaller value.
Then, use path storage 284 to deposit the survivor path value that the ACS module produces.
Then, carry out minimum value and select, when decoding time reaches decoding depth, 64 survivor paths are compared, select the path of a minimum.
At last, carry out the path and recall, according to the final state of minimal path and each corresponding survivor path value constantly, determine the back tracking point of previous stage, recall up to whole L levels and finish, give fullpath and survival value for change.The survival value sequence is exactly the inverted sequence sequence of decoding sequence.
(212) descrambler 26, adopt descrambler 26 to carry out descrambling.
(213) finish above-mentioned processing, the data that receive namely have been reduced into the MAC layer data.
Above-described execution mode of the present utility model does not constitute the restriction to the utility model protection range.Any modification of within spiritual principles of the present utility model, having done, be equal to and replace and improvement etc., all should be included within the claim protection range of the present utility model.
Claims (5)
1. the wireless communication system of a MIMO-OFDM comprises MCU, transmitter and receiver, and MCU controls transmitter and receiver; It is characterized in that,
Described transmitter comprises the first base band data processing section and the radio-frequency transmissions part that connects in turn, and the described first base band data processing section comprises first module and second module; The output of described first module connects the input of second module and the input of radio-frequency transmissions part respectively;
Described first module comprises scrambler, channel encoder, interleaver, QAM mapper, pilot tone inserter, IFFT converter and windowing and the prefix maker that connects in turn; Described second module is the training sequence maker; Described radio-frequency transmissions comprises that partly AD converter, IQ modulator, gain controller, the height of connection are put device and reflector in turn;
Described receiver comprises radio frequency receiving unit and the second base band data processing section, and described radio frequency receiving unit comprises receiver, LNA device, IQ demodulator, DA transducer and the AFC clock recovery that connects in turn; Another input of output termination IQ demodulator of AFC clock recovery; The described second base band data processing section comprises packet detector, carrier synchronization device, symbol synchronizer, CP remover, FFT converter, channel equalizer, sample frequency synchronizer, excess phase tracker, QAM de-mapping device, deinterleaver, channel decoder and the descrambler that connects in turn; Wherein the output of carrier synchronization device also connects the input of excess phase tracker, and channel equalizer also connects the QAM de-mapping device;
The input of the output termination packet detector of described DA transducer.
2. the wireless communication system of MIMO-OFDM according to claim 1 is characterized in that, described reflector is transmitting antenna.
3. the wireless communication system of MIMO-OFDM according to claim 2 is characterized in that, carry out at FPGA described first and second base band data processing section.
4. the wireless communication system of MIMO-OFDM according to claim 1 is characterized in that,
Described scrambler comprises parallel-to-serial converter and the scrambler that connects in turn;
Described channel encoder comprises convolution code maker, 2/3 rate convolutional code maker, the 3/4 rate convolutional code maker of 1/2 code check, and wherein the output of the convolution code maker of 1/2 code check selects to be connected to the input of 2/3 rate convolutional code maker, 3/4 rate convolutional code maker under the control of MCU;
Described interleaver comprises the one-level interleaver of being made up of write address maker, mould 384 counters, the first twoport block RAM and the secondary interleaver of being made up of read/write address maker, mould 24 counters, the second twoport block RAM, wherein write address maker and mould 384 counters are the write-read address input end of the first twoport block RAM in the one-level interleaver, the output of the first twoport block RAM is connecting the second twoport block RAM of secondary interleaver, and the read/write address of the second twoport block RAM of secondary interleaver is provided by the read/write address maker of mould 24 counter controls;
Described QAM mapper is the 16QAM modulator;
Described pilot tone inserter comprises first scrambler, look-up table, mould 64 counters and the 3rd twoport block RAM composition, wherein first scrambler is controlled by MCU, its output is controlled the data input pin of the 3rd twoport block RAM, and the read/write address of the 3rd twoport block RAM is provided by mould 64 counters and look-up table;
Described training sequence maker comprises that based on the short training sequence maker of IEEE802.11 standard and long training sequence maker wherein the output of the output of short training sequence maker and long training sequence maker is by MCU control output.
5. the wireless communication system of MIMO-OFDM according to claim 1 is characterized in that,
Described packet detector comprises cache module, master control module, postpones correlation energy computing module, correlation window energy computing module and frame search module, wherein cache module is connecting the input that postpones correlation energy computing module and correlation window energy computing module under the control of master control module, and postpone the correlation energy computing module is being connected the frame search module with the output of correlation window energy computing module input, the frame search module provides and feeds back signal to the master control module;
Described carrier synchronization device comprises data distribution module, Nonlinear Transformation in Frequency Offset Estimation module, data cache module, carrier wave frequency deviation compensating module and data aggregate output module, wherein three of the data distribution module outputs are carried the input of ripple frequency deviation estimating modules, data cache module and carrier wave frequency deviation compensating module respectively, the output of Nonlinear Transformation in Frequency Offset Estimation module is connecting another input of carrier wave frequency deviation compensating module, and data cache module is being connected the input of data aggregate output module with the output of carrier wave frequency deviation compensating module;
Described symbol synchronizer comprises quantization modules, matched filtering module and the symbol output module that connects in turn;
Described channel equalizer comprises long training symbol extraction module, energy computing module, channel estimation block, channel compensation block, wherein the output of long training symbol extraction module is connecting the input of energy computing module, channel estimation block and channel compensation block respectively, and the output of channel estimation block is connecting another input of channel compensation block, and the energy output of energy computing module is connected to the input of QAM de-mapping device;
Described sample frequency synchronizer comprises pilot extraction module, data cache module, pilot tone correlation module, frequency deviation estimating modules, compensate of frequency deviation module and order adjusting module, wherein pilot extraction module, data cache module, compensate of frequency deviation module and order adjusting module are connected in turn, the pilot tone output termination pilot tone correlation module of described pilot extraction module, the correlation output termination frequency deviation estimating modules of pilot tone correlation module, the input of the output termination compensate of frequency deviation module of the angle output of frequency deviation estimating modules and pilot tone buffer memory;
Described excess phase tracker comprises pilot extraction module, data cache module, Phase Tracking compensating factor computing module and excess phase compensating module, wherein pilot extraction module, data cache module and excess phase compensating module are connected in turn, and described pilot extraction module also connects the excess phase compensating module by Phase Tracking compensating factor computing module;
Described QAM de-mapping device comprises decision threshold adjusting module, data cache module and the 16QAM demodulation module that connects in turn, the input of the output termination decision threshold adjusting module of the energy computing module of channel equalizer wherein, the input of the output termination 16QAM demodulation module of the output of the energy computing module of channel equalizer and excess phase tracker;
Described channel decoder adopts Viterbi decoder, comprise that Hamming distance computing module, ACS module, minimum value select module, path memory module, survival RAM and path to recall module, wherein Hamming distance computing module, ACS module, minimum value selection module are recalled module with the path and are connected in turn, the input of the output termination path memory module of ACS module, the path memory module is received survival RAM, and the path memory module is received the path and recalled module.
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|---|---|---|---|---|
| CN103997393A (en) * | 2014-06-03 | 2014-08-20 | 东华大学 | Reconfigurable OFDM signal-to-noise-ratio strengthen system based on FPGA |
| CN104836765A (en) * | 2015-03-25 | 2015-08-12 | 南方科技大学 | Multi-carrier broadband information energy simultaneous transmission sending system and receiving system |
-
2013
- 2013-02-05 CN CN 201320065983 patent/CN203039714U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103997393A (en) * | 2014-06-03 | 2014-08-20 | 东华大学 | Reconfigurable OFDM signal-to-noise-ratio strengthen system based on FPGA |
| CN104836765A (en) * | 2015-03-25 | 2015-08-12 | 南方科技大学 | Multi-carrier broadband information energy simultaneous transmission sending system and receiving system |
| CN104836765B (en) * | 2015-03-25 | 2018-10-02 | 南方科技大学 | Multi-carrier broadband information energy simultaneous transmission sending system and receiving system |
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